Jisheng Zhang 07c1c8e320 riscv: mm: fix wrong phys_ram_base value for RV64 ... commit b0fd4b1bf9 upstream. Currently, if 64BIT and !XIP_KERNEL, the phys_ram_base is always 0, no matter the real start of dram reported by memblock is. Fixes: 6d7f91d914 ("riscv: Get rid of CONFIG_PHYS_RAM_BASE in kernel physical address conversion") Signed-off-by: Jisheng Zhang <jszhang@kernel.org> Reviewed-by: Alexandre Ghiti <alex@ghiti.fr> Cc: stable@vger.kernel.org Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>		2022-01-27 11:02:50 +01:00
..
boot	riscv: dts: unmatched: Add gpio card detect to mmc-spi-slot	2021-12-22 09:32:48 +01:00
configs	riscv: Get rid of MAXPHYSMEM configs	2022-01-27 11:02:49 +01:00
errata	riscv: skip errata_cip_453.o if CONFIG_ERRATA_SIFIVE_CIP_453 is disabled	2021-06-01 21:16:41 -07:00
include	RISC-V: Use common riscv_cpuid_to_hartid_mask() for both SMP=y and SMP=n	2022-01-27 11:02:50 +01:00
kernel	riscv: use hart id instead of cpu id on machine_kexec	2022-01-27 11:02:50 +01:00
lib	riscv: __asm_copy_to-from_user: Fix: Typos in comments	2021-07-23 17:49:12 -07:00
mm	riscv: mm: fix wrong phys_ram_base value for RV64	2022-01-27 11:02:50 +01:00
net	riscv, bpf: Fix potential NULL dereference	2021-10-28 08:14:30 -07:00
Kbuild	riscv: Allow device trees to be built into the kernel	2020-05-18 11:38:05 -07:00
Kconfig	riscv: Get rid of MAXPHYSMEM configs	2022-01-27 11:02:49 +01:00
Kconfig.debug	RISC-V: Remove EARLY_PRINTK support	2018-12-17 10:23:46 -08:00
Kconfig.erratas	riscv: enable SiFive errata CIP-453 and CIP-1200 Kconfig only if CONFIG_64BIT=y	2021-05-06 09:40:13 -07:00
Kconfig.socs	riscv: sifive: fix Kconfig errata warning	2021-06-12 17:20:50 -07:00
Makefile	riscv: fix building external modules	2021-11-25 09:48:40 +01:00