174 строки
4.8 KiB
C
174 строки
4.8 KiB
C
/*
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* arch/arm/mach-ks8695/time.c
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*
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* Copyright (C) 2006 Ben Dooks <ben@simtec.co.uk>
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* Copyright (C) 2006 Simtec Electronics
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#include <linux/init.h>
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#include <linux/interrupt.h>
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#include <linux/irq.h>
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#include <linux/kernel.h>
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#include <linux/sched.h>
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#include <linux/io.h>
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#include <linux/clockchips.h>
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#include <asm/mach/time.h>
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#include <asm/system_misc.h>
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#include <mach/regs-irq.h>
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#include "generic.h"
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#define KS8695_TMR_OFFSET (0xF0000 + 0xE400)
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#define KS8695_TMR_VA (KS8695_IO_VA + KS8695_TMR_OFFSET)
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#define KS8695_TMR_PA (KS8695_IO_PA + KS8695_TMR_OFFSET)
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/*
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* Timer registers
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*/
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#define KS8695_TMCON (0x00) /* Timer Control Register */
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#define KS8695_T1TC (0x04) /* Timer 1 Timeout Count Register */
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#define KS8695_T0TC (0x08) /* Timer 0 Timeout Count Register */
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#define KS8695_T1PD (0x0C) /* Timer 1 Pulse Count Register */
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#define KS8695_T0PD (0x10) /* Timer 0 Pulse Count Register */
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/* Timer Control Register */
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#define TMCON_T1EN (1 << 1) /* Timer 1 Enable */
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#define TMCON_T0EN (1 << 0) /* Timer 0 Enable */
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/* Timer0 Timeout Counter Register */
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#define T0TC_WATCHDOG (0xff) /* Enable watchdog mode */
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static void ks8695_set_mode(enum clock_event_mode mode,
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struct clock_event_device *evt)
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{
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u32 tmcon;
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if (mode == CLOCK_EVT_FEAT_PERIODIC) {
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u32 rate = DIV_ROUND_CLOSEST(KS8695_CLOCK_RATE, HZ);
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u32 half = DIV_ROUND_CLOSEST(rate, 2);
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/* Disable timer 1 */
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tmcon = readl_relaxed(KS8695_TMR_VA + KS8695_TMCON);
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tmcon &= ~TMCON_T1EN;
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writel_relaxed(tmcon, KS8695_TMR_VA + KS8695_TMCON);
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/* Both registers need to count down */
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writel_relaxed(half, KS8695_TMR_VA + KS8695_T1TC);
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writel_relaxed(half, KS8695_TMR_VA + KS8695_T1PD);
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/* Re-enable timer1 */
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tmcon |= TMCON_T1EN;
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writel_relaxed(tmcon, KS8695_TMR_VA + KS8695_TMCON);
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}
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}
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static int ks8695_set_next_event(unsigned long cycles,
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struct clock_event_device *evt)
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{
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u32 half = DIV_ROUND_CLOSEST(cycles, 2);
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u32 tmcon;
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/* Disable timer 1 */
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tmcon = readl_relaxed(KS8695_TMR_VA + KS8695_TMCON);
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tmcon &= ~TMCON_T1EN;
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writel_relaxed(tmcon, KS8695_TMR_VA + KS8695_TMCON);
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/* Both registers need to count down */
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writel_relaxed(half, KS8695_TMR_VA + KS8695_T1TC);
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writel_relaxed(half, KS8695_TMR_VA + KS8695_T1PD);
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/* Re-enable timer1 */
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tmcon |= TMCON_T1EN;
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writel_relaxed(tmcon, KS8695_TMR_VA + KS8695_TMCON);
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return 0;
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}
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static struct clock_event_device clockevent_ks8695 = {
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.name = "ks8695_t1tc",
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.rating = 300, /* Reasonably fast and accurate clock event */
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.features = CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_PERIODIC,
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.set_next_event = ks8695_set_next_event,
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.set_mode = ks8695_set_mode,
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};
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/*
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* IRQ handler for the timer.
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*/
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static irqreturn_t ks8695_timer_interrupt(int irq, void *dev_id)
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{
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struct clock_event_device *evt = &clockevent_ks8695;
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evt->event_handler(evt);
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return IRQ_HANDLED;
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}
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static struct irqaction ks8695_timer_irq = {
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.name = "ks8695_tick",
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.flags = IRQF_DISABLED | IRQF_TIMER,
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.handler = ks8695_timer_interrupt,
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};
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static void ks8695_timer_setup(void)
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{
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unsigned long tmcon;
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/* Disable timer 0 and 1 */
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tmcon = readl_relaxed(KS8695_TMR_VA + KS8695_TMCON);
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tmcon &= ~TMCON_T0EN;
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tmcon &= ~TMCON_T1EN;
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writel_relaxed(tmcon, KS8695_TMR_VA + KS8695_TMCON);
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/*
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* Use timer 1 to fire IRQs on the timeline, minimum 2 cycles
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* (one on each counter) maximum 2*2^32, but the API will only
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* accept up to a 32bit full word (0xFFFFFFFFU).
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*/
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clockevents_config_and_register(&clockevent_ks8695,
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KS8695_CLOCK_RATE, 2,
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0xFFFFFFFFU);
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}
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void __init ks8695_timer_init(void)
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{
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ks8695_timer_setup();
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/* Enable timer interrupts */
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setup_irq(KS8695_IRQ_TIMER1, &ks8695_timer_irq);
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}
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void ks8695_restart(char mode, const char *cmd)
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{
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unsigned int reg;
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if (mode == 's')
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soft_restart(0);
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/* disable timer0 */
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reg = readl_relaxed(KS8695_TMR_VA + KS8695_TMCON);
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writel_relaxed(reg & ~TMCON_T0EN, KS8695_TMR_VA + KS8695_TMCON);
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/* enable watchdog mode */
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writel_relaxed((10 << 8) | T0TC_WATCHDOG, KS8695_TMR_VA + KS8695_T0TC);
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/* re-enable timer0 */
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writel_relaxed(reg | TMCON_T0EN, KS8695_TMR_VA + KS8695_TMCON);
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}
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