456 строки
12 KiB
C
456 строки
12 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* MUSB OTG driver - support for Mentor's DMA controller
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*
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* Copyright 2005 Mentor Graphics Corporation
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* Copyright (C) 2005-2007 by Texas Instruments
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*/
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#include <linux/device.h>
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#include <linux/interrupt.h>
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#include <linux/platform_device.h>
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#include <linux/slab.h>
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#include "musb_core.h"
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#include "musb_dma.h"
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#define MUSB_HSDMA_CHANNEL_OFFSET(_bchannel, _offset) \
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(MUSB_HSDMA_BASE + (_bchannel << 4) + _offset)
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#define musb_read_hsdma_addr(mbase, bchannel) \
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musb_readl(mbase, \
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MUSB_HSDMA_CHANNEL_OFFSET(bchannel, MUSB_HSDMA_ADDRESS))
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#define musb_write_hsdma_addr(mbase, bchannel, addr) \
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musb_writel(mbase, \
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MUSB_HSDMA_CHANNEL_OFFSET(bchannel, MUSB_HSDMA_ADDRESS), \
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addr)
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#define musb_read_hsdma_count(mbase, bchannel) \
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musb_readl(mbase, \
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MUSB_HSDMA_CHANNEL_OFFSET(bchannel, MUSB_HSDMA_COUNT))
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#define musb_write_hsdma_count(mbase, bchannel, len) \
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musb_writel(mbase, \
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MUSB_HSDMA_CHANNEL_OFFSET(bchannel, MUSB_HSDMA_COUNT), \
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len)
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/* control register (16-bit): */
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#define MUSB_HSDMA_ENABLE_SHIFT 0
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#define MUSB_HSDMA_TRANSMIT_SHIFT 1
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#define MUSB_HSDMA_MODE1_SHIFT 2
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#define MUSB_HSDMA_IRQENABLE_SHIFT 3
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#define MUSB_HSDMA_ENDPOINT_SHIFT 4
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#define MUSB_HSDMA_BUSERROR_SHIFT 8
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#define MUSB_HSDMA_BURSTMODE_SHIFT 9
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#define MUSB_HSDMA_BURSTMODE (3 << MUSB_HSDMA_BURSTMODE_SHIFT)
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#define MUSB_HSDMA_BURSTMODE_UNSPEC 0
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#define MUSB_HSDMA_BURSTMODE_INCR4 1
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#define MUSB_HSDMA_BURSTMODE_INCR8 2
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#define MUSB_HSDMA_BURSTMODE_INCR16 3
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#define MUSB_HSDMA_CHANNELS 8
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struct musb_dma_controller;
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struct musb_dma_channel {
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struct dma_channel channel;
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struct musb_dma_controller *controller;
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u32 start_addr;
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u32 len;
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u16 max_packet_sz;
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u8 idx;
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u8 epnum;
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u8 transmit;
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};
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struct musb_dma_controller {
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struct dma_controller controller;
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struct musb_dma_channel channel[MUSB_HSDMA_CHANNELS];
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void *private_data;
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void __iomem *base;
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u8 channel_count;
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u8 used_channels;
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int irq;
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};
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static void dma_channel_release(struct dma_channel *channel);
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static void dma_controller_stop(struct musb_dma_controller *controller)
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{
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struct musb *musb = controller->private_data;
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struct dma_channel *channel;
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u8 bit;
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if (controller->used_channels != 0) {
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dev_err(musb->controller,
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"Stopping DMA controller while channel active\n");
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for (bit = 0; bit < MUSB_HSDMA_CHANNELS; bit++) {
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if (controller->used_channels & (1 << bit)) {
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channel = &controller->channel[bit].channel;
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dma_channel_release(channel);
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if (!controller->used_channels)
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break;
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}
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}
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}
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}
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static struct dma_channel *dma_channel_allocate(struct dma_controller *c,
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struct musb_hw_ep *hw_ep, u8 transmit)
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{
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struct musb_dma_controller *controller = container_of(c,
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struct musb_dma_controller, controller);
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struct musb_dma_channel *musb_channel = NULL;
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struct dma_channel *channel = NULL;
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u8 bit;
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for (bit = 0; bit < MUSB_HSDMA_CHANNELS; bit++) {
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if (!(controller->used_channels & (1 << bit))) {
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controller->used_channels |= (1 << bit);
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musb_channel = &(controller->channel[bit]);
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musb_channel->controller = controller;
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musb_channel->idx = bit;
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musb_channel->epnum = hw_ep->epnum;
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musb_channel->transmit = transmit;
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channel = &(musb_channel->channel);
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channel->private_data = musb_channel;
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channel->status = MUSB_DMA_STATUS_FREE;
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channel->max_len = 0x100000;
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/* Tx => mode 1; Rx => mode 0 */
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channel->desired_mode = transmit;
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channel->actual_len = 0;
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break;
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}
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}
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return channel;
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}
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static void dma_channel_release(struct dma_channel *channel)
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{
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struct musb_dma_channel *musb_channel = channel->private_data;
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channel->actual_len = 0;
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musb_channel->start_addr = 0;
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musb_channel->len = 0;
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musb_channel->controller->used_channels &=
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~(1 << musb_channel->idx);
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channel->status = MUSB_DMA_STATUS_UNKNOWN;
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}
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static void configure_channel(struct dma_channel *channel,
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u16 packet_sz, u8 mode,
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dma_addr_t dma_addr, u32 len)
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{
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struct musb_dma_channel *musb_channel = channel->private_data;
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struct musb_dma_controller *controller = musb_channel->controller;
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struct musb *musb = controller->private_data;
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void __iomem *mbase = controller->base;
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u8 bchannel = musb_channel->idx;
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u16 csr = 0;
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musb_dbg(musb, "%p, pkt_sz %d, addr %pad, len %d, mode %d",
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channel, packet_sz, &dma_addr, len, mode);
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if (mode) {
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csr |= 1 << MUSB_HSDMA_MODE1_SHIFT;
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BUG_ON(len < packet_sz);
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}
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csr |= MUSB_HSDMA_BURSTMODE_INCR16
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<< MUSB_HSDMA_BURSTMODE_SHIFT;
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csr |= (musb_channel->epnum << MUSB_HSDMA_ENDPOINT_SHIFT)
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| (1 << MUSB_HSDMA_ENABLE_SHIFT)
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| (1 << MUSB_HSDMA_IRQENABLE_SHIFT)
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| (musb_channel->transmit
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? (1 << MUSB_HSDMA_TRANSMIT_SHIFT)
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: 0);
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/* address/count */
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musb_write_hsdma_addr(mbase, bchannel, dma_addr);
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musb_write_hsdma_count(mbase, bchannel, len);
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/* control (this should start things) */
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musb_writew(mbase,
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MUSB_HSDMA_CHANNEL_OFFSET(bchannel, MUSB_HSDMA_CONTROL),
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csr);
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}
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static int dma_channel_program(struct dma_channel *channel,
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u16 packet_sz, u8 mode,
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dma_addr_t dma_addr, u32 len)
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{
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struct musb_dma_channel *musb_channel = channel->private_data;
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struct musb_dma_controller *controller = musb_channel->controller;
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struct musb *musb = controller->private_data;
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musb_dbg(musb, "ep%d-%s pkt_sz %d, dma_addr %pad length %d, mode %d",
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musb_channel->epnum,
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musb_channel->transmit ? "Tx" : "Rx",
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packet_sz, &dma_addr, len, mode);
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BUG_ON(channel->status == MUSB_DMA_STATUS_UNKNOWN ||
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channel->status == MUSB_DMA_STATUS_BUSY);
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/*
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* The DMA engine in RTL1.8 and above cannot handle
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* DMA addresses that are not aligned to a 4 byte boundary.
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* It ends up masking the last two bits of the address
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* programmed in DMA_ADDR.
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*
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* Fail such DMA transfers, so that the backup PIO mode
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* can carry out the transfer
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*/
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if ((musb->hwvers >= MUSB_HWVERS_1800) && (dma_addr % 4))
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return false;
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channel->actual_len = 0;
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musb_channel->start_addr = dma_addr;
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musb_channel->len = len;
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musb_channel->max_packet_sz = packet_sz;
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channel->status = MUSB_DMA_STATUS_BUSY;
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configure_channel(channel, packet_sz, mode, dma_addr, len);
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return true;
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}
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static int dma_channel_abort(struct dma_channel *channel)
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{
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struct musb_dma_channel *musb_channel = channel->private_data;
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void __iomem *mbase = musb_channel->controller->base;
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struct musb *musb = musb_channel->controller->private_data;
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u8 bchannel = musb_channel->idx;
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int offset;
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u16 csr;
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if (channel->status == MUSB_DMA_STATUS_BUSY) {
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if (musb_channel->transmit) {
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offset = musb->io.ep_offset(musb_channel->epnum,
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MUSB_TXCSR);
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/*
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* The programming guide says that we must clear
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* the DMAENAB bit before the DMAMODE bit...
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*/
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csr = musb_readw(mbase, offset);
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csr &= ~(MUSB_TXCSR_AUTOSET | MUSB_TXCSR_DMAENAB);
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musb_writew(mbase, offset, csr);
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csr &= ~MUSB_TXCSR_DMAMODE;
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musb_writew(mbase, offset, csr);
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} else {
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offset = musb->io.ep_offset(musb_channel->epnum,
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MUSB_RXCSR);
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csr = musb_readw(mbase, offset);
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csr &= ~(MUSB_RXCSR_AUTOCLEAR |
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MUSB_RXCSR_DMAENAB |
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MUSB_RXCSR_DMAMODE);
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musb_writew(mbase, offset, csr);
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}
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musb_writew(mbase,
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MUSB_HSDMA_CHANNEL_OFFSET(bchannel, MUSB_HSDMA_CONTROL),
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0);
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musb_write_hsdma_addr(mbase, bchannel, 0);
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musb_write_hsdma_count(mbase, bchannel, 0);
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channel->status = MUSB_DMA_STATUS_FREE;
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}
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return 0;
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}
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irqreturn_t dma_controller_irq(int irq, void *private_data)
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{
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struct musb_dma_controller *controller = private_data;
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struct musb *musb = controller->private_data;
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struct musb_dma_channel *musb_channel;
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struct dma_channel *channel;
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void __iomem *mbase = controller->base;
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irqreturn_t retval = IRQ_NONE;
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unsigned long flags;
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u8 bchannel;
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u8 int_hsdma;
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u32 addr, count;
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u16 csr;
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spin_lock_irqsave(&musb->lock, flags);
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int_hsdma = musb_clearb(mbase, MUSB_HSDMA_INTR);
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if (!int_hsdma) {
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musb_dbg(musb, "spurious DMA irq");
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for (bchannel = 0; bchannel < MUSB_HSDMA_CHANNELS; bchannel++) {
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musb_channel = (struct musb_dma_channel *)
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&(controller->channel[bchannel]);
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channel = &musb_channel->channel;
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if (channel->status == MUSB_DMA_STATUS_BUSY) {
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count = musb_read_hsdma_count(mbase, bchannel);
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if (count == 0)
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int_hsdma |= (1 << bchannel);
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}
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}
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musb_dbg(musb, "int_hsdma = 0x%x", int_hsdma);
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if (!int_hsdma)
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goto done;
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}
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for (bchannel = 0; bchannel < MUSB_HSDMA_CHANNELS; bchannel++) {
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if (int_hsdma & (1 << bchannel)) {
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musb_channel = (struct musb_dma_channel *)
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&(controller->channel[bchannel]);
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channel = &musb_channel->channel;
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csr = musb_readw(mbase,
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MUSB_HSDMA_CHANNEL_OFFSET(bchannel,
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MUSB_HSDMA_CONTROL));
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if (csr & (1 << MUSB_HSDMA_BUSERROR_SHIFT)) {
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musb_channel->channel.status =
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MUSB_DMA_STATUS_BUS_ABORT;
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} else {
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addr = musb_read_hsdma_addr(mbase,
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bchannel);
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channel->actual_len = addr
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- musb_channel->start_addr;
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musb_dbg(musb, "ch %p, 0x%x -> 0x%x (%zu / %d) %s",
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channel, musb_channel->start_addr,
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addr, channel->actual_len,
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musb_channel->len,
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(channel->actual_len
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< musb_channel->len) ?
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"=> reconfig 0" : "=> complete");
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channel->status = MUSB_DMA_STATUS_FREE;
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/* completed */
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if (musb_channel->transmit &&
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(!channel->desired_mode ||
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(channel->actual_len %
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musb_channel->max_packet_sz))) {
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u8 epnum = musb_channel->epnum;
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int offset = musb->io.ep_offset(epnum,
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MUSB_TXCSR);
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u16 txcsr;
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/*
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* The programming guide says that we
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* must clear DMAENAB before DMAMODE.
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*/
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musb_ep_select(mbase, epnum);
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txcsr = musb_readw(mbase, offset);
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if (channel->desired_mode == 1) {
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txcsr &= ~(MUSB_TXCSR_DMAENAB
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| MUSB_TXCSR_AUTOSET);
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musb_writew(mbase, offset, txcsr);
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/* Send out the packet */
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txcsr &= ~MUSB_TXCSR_DMAMODE;
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txcsr |= MUSB_TXCSR_DMAENAB;
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}
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txcsr |= MUSB_TXCSR_TXPKTRDY;
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musb_writew(mbase, offset, txcsr);
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}
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musb_dma_completion(musb, musb_channel->epnum,
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musb_channel->transmit);
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}
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}
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}
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retval = IRQ_HANDLED;
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done:
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spin_unlock_irqrestore(&musb->lock, flags);
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return retval;
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}
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EXPORT_SYMBOL_GPL(dma_controller_irq);
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void musbhs_dma_controller_destroy(struct dma_controller *c)
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{
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struct musb_dma_controller *controller = container_of(c,
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struct musb_dma_controller, controller);
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dma_controller_stop(controller);
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if (controller->irq)
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free_irq(controller->irq, c);
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kfree(controller);
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}
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EXPORT_SYMBOL_GPL(musbhs_dma_controller_destroy);
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static struct musb_dma_controller *
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dma_controller_alloc(struct musb *musb, void __iomem *base)
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{
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struct musb_dma_controller *controller;
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controller = kzalloc(sizeof(*controller), GFP_KERNEL);
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if (!controller)
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return NULL;
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controller->channel_count = MUSB_HSDMA_CHANNELS;
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controller->private_data = musb;
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controller->base = base;
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controller->controller.channel_alloc = dma_channel_allocate;
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controller->controller.channel_release = dma_channel_release;
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controller->controller.channel_program = dma_channel_program;
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controller->controller.channel_abort = dma_channel_abort;
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return controller;
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}
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struct dma_controller *
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musbhs_dma_controller_create(struct musb *musb, void __iomem *base)
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{
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struct musb_dma_controller *controller;
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struct device *dev = musb->controller;
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struct platform_device *pdev = to_platform_device(dev);
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int irq = platform_get_irq_byname(pdev, "dma");
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if (irq <= 0) {
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dev_err(dev, "No DMA interrupt line!\n");
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return NULL;
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}
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controller = dma_controller_alloc(musb, base);
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if (!controller)
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return NULL;
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if (request_irq(irq, dma_controller_irq, 0,
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dev_name(musb->controller), controller)) {
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dev_err(dev, "request_irq %d failed!\n", irq);
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musb_dma_controller_destroy(&controller->controller);
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return NULL;
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}
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controller->irq = irq;
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return &controller->controller;
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}
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EXPORT_SYMBOL_GPL(musbhs_dma_controller_create);
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struct dma_controller *
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musbhs_dma_controller_create_noirq(struct musb *musb, void __iomem *base)
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{
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struct musb_dma_controller *controller;
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controller = dma_controller_alloc(musb, base);
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if (!controller)
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return NULL;
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return &controller->controller;
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}
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EXPORT_SYMBOL_GPL(musbhs_dma_controller_create_noirq);
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