147 строки
3.6 KiB
C
147 строки
3.6 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* UFS PHY driver for Samsung EXYNOS SoC
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*
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* Copyright (C) 2020 Samsung Electronics Co., Ltd.
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* Author: Seungwon Jeon <essuuj@gmail.com>
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* Author: Alim Akhtar <alim.akhtar@samsung.com>
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*
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*/
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#ifndef _PHY_SAMSUNG_UFS_
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#define _PHY_SAMSUNG_UFS_
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#include <linux/phy/phy.h>
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#include <linux/regmap.h>
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#define PHY_COMN_BLK 1
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#define PHY_TRSV_BLK 2
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#define END_UFS_PHY_CFG { 0 }
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#define PHY_TRSV_CH_OFFSET 0x30
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#define PHY_APB_ADDR(off) ((off) << 2)
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#define PHY_COMN_REG_CFG(o, v, d) { \
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.off_0 = PHY_APB_ADDR((o)), \
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.off_1 = 0, \
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.val = (v), \
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.desc = (d), \
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.id = PHY_COMN_BLK, \
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}
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#define PHY_TRSV_REG_CFG_OFFSET(o, v, d, c) { \
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.off_0 = PHY_APB_ADDR((o)), \
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.off_1 = PHY_APB_ADDR((o) + (c)), \
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.val = (v), \
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.desc = (d), \
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.id = PHY_TRSV_BLK, \
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}
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#define PHY_TRSV_REG_CFG(o, v, d) \
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PHY_TRSV_REG_CFG_OFFSET(o, v, d, PHY_TRSV_CH_OFFSET)
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/* UFS PHY registers */
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#define PHY_PLL_LOCK_STATUS 0x1e
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#define PHY_CDR_LOCK_STATUS 0x5e
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#define PHY_PLL_LOCK_BIT BIT(5)
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#define PHY_CDR_LOCK_BIT BIT(4)
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/* description for PHY calibration */
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enum {
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/* applicable to any */
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PWR_DESC_ANY = 0,
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/* mode */
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PWR_DESC_PWM = 1,
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PWR_DESC_HS = 2,
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/* series */
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PWR_DESC_SER_A = 1,
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PWR_DESC_SER_B = 2,
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/* gear */
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PWR_DESC_G1 = 1,
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PWR_DESC_G2 = 2,
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PWR_DESC_G3 = 3,
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/* field mask */
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MD_MASK = 0x3,
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SR_MASK = 0x3,
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GR_MASK = 0x7,
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};
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#define PWR_MODE_HS_G1_ANY PWR_MODE_HS(PWR_DESC_G1, PWR_DESC_ANY)
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#define PWR_MODE_HS_G1_SER_A PWR_MODE_HS(PWR_DESC_G1, PWR_DESC_SER_A)
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#define PWR_MODE_HS_G1_SER_B PWR_MODE_HS(PWR_DESC_G1, PWR_DESC_SER_B)
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#define PWR_MODE_HS_G2_ANY PWR_MODE_HS(PWR_DESC_G2, PWR_DESC_ANY)
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#define PWR_MODE_HS_G2_SER_A PWR_MODE_HS(PWR_DESC_G2, PWR_DESC_SER_A)
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#define PWR_MODE_HS_G2_SER_B PWR_MODE_HS(PWR_DESC_G2, PWR_DESC_SER_B)
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#define PWR_MODE_HS_G3_ANY PWR_MODE_HS(PWR_DESC_G3, PWR_DESC_ANY)
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#define PWR_MODE_HS_G3_SER_A PWR_MODE_HS(PWR_DESC_G3, PWR_DESC_SER_A)
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#define PWR_MODE_HS_G3_SER_B PWR_MODE_HS(PWR_DESC_G3, PWR_DESC_SER_B)
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#define PWR_MODE(g, s, m) ((((g) & GR_MASK) << 4) |\
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(((s) & SR_MASK) << 2) | ((m) & MD_MASK))
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#define PWR_MODE_PWM_ANY PWR_MODE(PWR_DESC_ANY,\
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PWR_DESC_ANY, PWR_DESC_PWM)
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#define PWR_MODE_HS(g, s) ((((g) & GR_MASK) << 4) |\
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(((s) & SR_MASK) << 2) | PWR_DESC_HS)
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#define PWR_MODE_HS_ANY PWR_MODE(PWR_DESC_ANY,\
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PWR_DESC_ANY, PWR_DESC_HS)
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#define PWR_MODE_ANY PWR_MODE(PWR_DESC_ANY,\
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PWR_DESC_ANY, PWR_DESC_ANY)
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/* PHY calibration point/state */
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enum {
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CFG_PRE_INIT,
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CFG_POST_INIT,
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CFG_PRE_PWR_HS,
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CFG_POST_PWR_HS,
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CFG_TAG_MAX,
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};
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struct samsung_ufs_phy_cfg {
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u32 off_0;
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u32 off_1;
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u32 val;
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u8 desc;
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u8 id;
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};
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struct samsung_ufs_phy_drvdata {
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const struct samsung_ufs_phy_cfg **cfg;
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struct pmu_isol {
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u32 offset;
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u32 mask;
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u32 en;
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} isol;
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bool has_symbol_clk;
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};
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struct samsung_ufs_phy {
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struct device *dev;
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void __iomem *reg_pma;
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struct regmap *reg_pmu;
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struct clk *ref_clk;
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struct clk *ref_clk_parent;
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struct clk *tx0_symbol_clk;
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struct clk *rx0_symbol_clk;
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struct clk *rx1_symbol_clk;
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const struct samsung_ufs_phy_drvdata *drvdata;
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struct samsung_ufs_phy_cfg **cfg;
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const struct pmu_isol *isol;
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u8 lane_cnt;
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int ufs_phy_state;
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enum phy_mode mode;
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};
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static inline struct samsung_ufs_phy *get_samsung_ufs_phy(struct phy *phy)
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{
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return (struct samsung_ufs_phy *)phy_get_drvdata(phy);
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}
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static inline void samsung_ufs_phy_ctrl_isol(
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struct samsung_ufs_phy *phy, u32 isol)
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{
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regmap_update_bits(phy->reg_pmu, phy->isol->offset,
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phy->isol->mask, isol ? 0 : phy->isol->en);
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}
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extern const struct samsung_ufs_phy_drvdata exynos7_ufs_phy;
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extern const struct samsung_ufs_phy_drvdata exynosautov9_ufs_phy;
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#endif /* _PHY_SAMSUNG_UFS_ */
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