701 строка
18 KiB
C
701 строка
18 KiB
C
/*
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* Driver for Nvidia TEGRA spi controller.
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*
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* Copyright (C) 2010 Google, Inc.
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*
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* Author:
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* Erik Gilling <konkers@android.com>
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*
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* This software is licensed under the terms of the GNU General Public
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* License version 2, as published by the Free Software Foundation, and
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* may be copied, distributed, and modified under those terms.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/init.h>
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#include <linux/err.h>
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#include <linux/platform_device.h>
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#include <linux/io.h>
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#include <linux/dma-mapping.h>
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#include <linux/dmapool.h>
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#include <linux/clk.h>
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#include <linux/interrupt.h>
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#include <linux/delay.h>
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#include <linux/spi/spi.h>
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#include <linux/dmaengine.h>
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#include <mach/dma.h>
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#define SLINK_COMMAND 0x000
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#define SLINK_BIT_LENGTH(x) (((x) & 0x1f) << 0)
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#define SLINK_WORD_SIZE(x) (((x) & 0x1f) << 5)
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#define SLINK_BOTH_EN (1 << 10)
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#define SLINK_CS_SW (1 << 11)
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#define SLINK_CS_VALUE (1 << 12)
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#define SLINK_CS_POLARITY (1 << 13)
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#define SLINK_IDLE_SDA_DRIVE_LOW (0 << 16)
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#define SLINK_IDLE_SDA_DRIVE_HIGH (1 << 16)
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#define SLINK_IDLE_SDA_PULL_LOW (2 << 16)
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#define SLINK_IDLE_SDA_PULL_HIGH (3 << 16)
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#define SLINK_IDLE_SDA_MASK (3 << 16)
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#define SLINK_CS_POLARITY1 (1 << 20)
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#define SLINK_CK_SDA (1 << 21)
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#define SLINK_CS_POLARITY2 (1 << 22)
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#define SLINK_CS_POLARITY3 (1 << 23)
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#define SLINK_IDLE_SCLK_DRIVE_LOW (0 << 24)
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#define SLINK_IDLE_SCLK_DRIVE_HIGH (1 << 24)
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#define SLINK_IDLE_SCLK_PULL_LOW (2 << 24)
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#define SLINK_IDLE_SCLK_PULL_HIGH (3 << 24)
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#define SLINK_IDLE_SCLK_MASK (3 << 24)
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#define SLINK_M_S (1 << 28)
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#define SLINK_WAIT (1 << 29)
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#define SLINK_GO (1 << 30)
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#define SLINK_ENB (1 << 31)
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#define SLINK_COMMAND2 0x004
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#define SLINK_LSBFE (1 << 0)
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#define SLINK_SSOE (1 << 1)
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#define SLINK_SPIE (1 << 4)
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#define SLINK_BIDIROE (1 << 6)
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#define SLINK_MODFEN (1 << 7)
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#define SLINK_INT_SIZE(x) (((x) & 0x1f) << 8)
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#define SLINK_CS_ACTIVE_BETWEEN (1 << 17)
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#define SLINK_SS_EN_CS(x) (((x) & 0x3) << 18)
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#define SLINK_SS_SETUP(x) (((x) & 0x3) << 20)
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#define SLINK_FIFO_REFILLS_0 (0 << 22)
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#define SLINK_FIFO_REFILLS_1 (1 << 22)
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#define SLINK_FIFO_REFILLS_2 (2 << 22)
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#define SLINK_FIFO_REFILLS_3 (3 << 22)
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#define SLINK_FIFO_REFILLS_MASK (3 << 22)
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#define SLINK_WAIT_PACK_INT(x) (((x) & 0x7) << 26)
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#define SLINK_SPC0 (1 << 29)
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#define SLINK_TXEN (1 << 30)
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#define SLINK_RXEN (1 << 31)
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#define SLINK_STATUS 0x008
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#define SLINK_COUNT(val) (((val) >> 0) & 0x1f)
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#define SLINK_WORD(val) (((val) >> 5) & 0x1f)
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#define SLINK_BLK_CNT(val) (((val) >> 0) & 0xffff)
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#define SLINK_MODF (1 << 16)
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#define SLINK_RX_UNF (1 << 18)
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#define SLINK_TX_OVF (1 << 19)
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#define SLINK_TX_FULL (1 << 20)
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#define SLINK_TX_EMPTY (1 << 21)
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#define SLINK_RX_FULL (1 << 22)
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#define SLINK_RX_EMPTY (1 << 23)
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#define SLINK_TX_UNF (1 << 24)
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#define SLINK_RX_OVF (1 << 25)
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#define SLINK_TX_FLUSH (1 << 26)
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#define SLINK_RX_FLUSH (1 << 27)
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#define SLINK_SCLK (1 << 28)
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#define SLINK_ERR (1 << 29)
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#define SLINK_RDY (1 << 30)
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#define SLINK_BSY (1 << 31)
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#define SLINK_MAS_DATA 0x010
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#define SLINK_SLAVE_DATA 0x014
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#define SLINK_DMA_CTL 0x018
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#define SLINK_DMA_BLOCK_SIZE(x) (((x) & 0xffff) << 0)
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#define SLINK_TX_TRIG_1 (0 << 16)
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#define SLINK_TX_TRIG_4 (1 << 16)
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#define SLINK_TX_TRIG_8 (2 << 16)
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#define SLINK_TX_TRIG_16 (3 << 16)
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#define SLINK_TX_TRIG_MASK (3 << 16)
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#define SLINK_RX_TRIG_1 (0 << 18)
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#define SLINK_RX_TRIG_4 (1 << 18)
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#define SLINK_RX_TRIG_8 (2 << 18)
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#define SLINK_RX_TRIG_16 (3 << 18)
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#define SLINK_RX_TRIG_MASK (3 << 18)
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#define SLINK_PACKED (1 << 20)
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#define SLINK_PACK_SIZE_4 (0 << 21)
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#define SLINK_PACK_SIZE_8 (1 << 21)
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#define SLINK_PACK_SIZE_16 (2 << 21)
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#define SLINK_PACK_SIZE_32 (3 << 21)
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#define SLINK_PACK_SIZE_MASK (3 << 21)
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#define SLINK_IE_TXC (1 << 26)
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#define SLINK_IE_RXC (1 << 27)
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#define SLINK_DMA_EN (1 << 31)
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#define SLINK_STATUS2 0x01c
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#define SLINK_TX_FIFO_EMPTY_COUNT(val) (((val) & 0x3f) >> 0)
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#define SLINK_RX_FIFO_FULL_COUNT(val) (((val) & 0x3f) >> 16)
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#define SLINK_TX_FIFO 0x100
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#define SLINK_RX_FIFO 0x180
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static const unsigned long spi_tegra_req_sels[] = {
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TEGRA_DMA_REQ_SEL_SL2B1,
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TEGRA_DMA_REQ_SEL_SL2B2,
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TEGRA_DMA_REQ_SEL_SL2B3,
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TEGRA_DMA_REQ_SEL_SL2B4,
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};
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#define BB_LEN 32
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struct spi_tegra_data {
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struct spi_master *master;
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struct platform_device *pdev;
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spinlock_t lock;
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struct clk *clk;
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void __iomem *base;
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unsigned long phys;
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u32 cur_speed;
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struct list_head queue;
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struct spi_transfer *cur;
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unsigned cur_pos;
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unsigned cur_len;
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unsigned cur_bytes_per_word;
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/* The tegra spi controller has a bug which causes the first word
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* in PIO transactions to be garbage. Since packed DMA transactions
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* require transfers to be 4 byte aligned we need a bounce buffer
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* for the generic case.
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*/
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int dma_req_len;
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#if defined(CONFIG_TEGRA_SYSTEM_DMA)
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struct tegra_dma_req rx_dma_req;
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struct tegra_dma_channel *rx_dma;
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#else
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struct dma_chan *rx_dma;
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struct dma_slave_config sconfig;
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struct dma_async_tx_descriptor *rx_dma_desc;
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dma_cookie_t rx_cookie;
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#endif
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u32 *rx_bb;
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dma_addr_t rx_bb_phys;
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};
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#if !defined(CONFIG_TEGRA_SYSTEM_DMA)
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static void tegra_spi_rx_dma_complete(void *args);
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#endif
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static inline unsigned long spi_tegra_readl(struct spi_tegra_data *tspi,
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unsigned long reg)
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{
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return readl(tspi->base + reg);
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}
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static inline void spi_tegra_writel(struct spi_tegra_data *tspi,
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unsigned long val,
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unsigned long reg)
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{
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writel(val, tspi->base + reg);
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}
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static void spi_tegra_go(struct spi_tegra_data *tspi)
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{
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unsigned long val;
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wmb();
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val = spi_tegra_readl(tspi, SLINK_DMA_CTL);
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val &= ~SLINK_DMA_BLOCK_SIZE(~0) & ~SLINK_DMA_EN;
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val |= SLINK_DMA_BLOCK_SIZE(tspi->dma_req_len / 4 - 1);
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spi_tegra_writel(tspi, val, SLINK_DMA_CTL);
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#if defined(CONFIG_TEGRA_SYSTEM_DMA)
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tspi->rx_dma_req.size = tspi->dma_req_len;
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tegra_dma_enqueue_req(tspi->rx_dma, &tspi->rx_dma_req);
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#else
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tspi->rx_dma_desc = dmaengine_prep_slave_single(tspi->rx_dma,
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tspi->rx_bb_phys, tspi->dma_req_len,
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DMA_DEV_TO_MEM, DMA_PREP_INTERRUPT);
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if (!tspi->rx_dma_desc) {
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dev_err(&tspi->pdev->dev, "dmaengine slave prep failed\n");
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return;
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}
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tspi->rx_dma_desc->callback = tegra_spi_rx_dma_complete;
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tspi->rx_dma_desc->callback_param = tspi;
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tspi->rx_cookie = dmaengine_submit(tspi->rx_dma_desc);
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dma_async_issue_pending(tspi->rx_dma);
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#endif
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val |= SLINK_DMA_EN;
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spi_tegra_writel(tspi, val, SLINK_DMA_CTL);
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}
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static unsigned spi_tegra_fill_tx_fifo(struct spi_tegra_data *tspi,
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struct spi_transfer *t)
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{
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unsigned len = min(t->len - tspi->cur_pos, BB_LEN *
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tspi->cur_bytes_per_word);
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u8 *tx_buf = (u8 *)t->tx_buf + tspi->cur_pos;
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int i, j;
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unsigned long val;
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val = spi_tegra_readl(tspi, SLINK_COMMAND);
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val &= ~SLINK_WORD_SIZE(~0);
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val |= SLINK_WORD_SIZE(len / tspi->cur_bytes_per_word - 1);
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spi_tegra_writel(tspi, val, SLINK_COMMAND);
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for (i = 0; i < len; i += tspi->cur_bytes_per_word) {
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val = 0;
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for (j = 0; j < tspi->cur_bytes_per_word; j++)
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val |= tx_buf[i + j] << j * 8;
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spi_tegra_writel(tspi, val, SLINK_TX_FIFO);
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}
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tspi->dma_req_len = len / tspi->cur_bytes_per_word * 4;
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return len;
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}
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static unsigned spi_tegra_drain_rx_fifo(struct spi_tegra_data *tspi,
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struct spi_transfer *t)
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{
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unsigned len = tspi->cur_len;
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u8 *rx_buf = (u8 *)t->rx_buf + tspi->cur_pos;
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int i, j;
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unsigned long val;
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for (i = 0; i < len; i += tspi->cur_bytes_per_word) {
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val = tspi->rx_bb[i / tspi->cur_bytes_per_word];
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for (j = 0; j < tspi->cur_bytes_per_word; j++)
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rx_buf[i + j] = (val >> (j * 8)) & 0xff;
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}
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return len;
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}
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static void spi_tegra_start_transfer(struct spi_device *spi,
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struct spi_transfer *t)
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{
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struct spi_tegra_data *tspi = spi_master_get_devdata(spi->master);
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u32 speed;
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u8 bits_per_word;
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unsigned long val;
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speed = t->speed_hz ? t->speed_hz : spi->max_speed_hz;
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bits_per_word = t->bits_per_word ? t->bits_per_word :
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spi->bits_per_word;
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tspi->cur_bytes_per_word = (bits_per_word - 1) / 8 + 1;
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if (speed != tspi->cur_speed)
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clk_set_rate(tspi->clk, speed);
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if (tspi->cur_speed == 0)
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clk_prepare_enable(tspi->clk);
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tspi->cur_speed = speed;
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val = spi_tegra_readl(tspi, SLINK_COMMAND2);
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val &= ~SLINK_SS_EN_CS(~0) | SLINK_RXEN | SLINK_TXEN;
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if (t->rx_buf)
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val |= SLINK_RXEN;
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if (t->tx_buf)
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val |= SLINK_TXEN;
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val |= SLINK_SS_EN_CS(spi->chip_select);
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val |= SLINK_SPIE;
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spi_tegra_writel(tspi, val, SLINK_COMMAND2);
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val = spi_tegra_readl(tspi, SLINK_COMMAND);
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val &= ~SLINK_BIT_LENGTH(~0);
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val |= SLINK_BIT_LENGTH(bits_per_word - 1);
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/* FIXME: should probably control CS manually so that we can be sure
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* it does not go low between transfer and to support delay_usecs
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* correctly.
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*/
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val &= ~SLINK_IDLE_SCLK_MASK & ~SLINK_CK_SDA & ~SLINK_CS_SW;
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if (spi->mode & SPI_CPHA)
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val |= SLINK_CK_SDA;
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if (spi->mode & SPI_CPOL)
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val |= SLINK_IDLE_SCLK_DRIVE_HIGH;
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else
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val |= SLINK_IDLE_SCLK_DRIVE_LOW;
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val |= SLINK_M_S;
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spi_tegra_writel(tspi, val, SLINK_COMMAND);
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spi_tegra_writel(tspi, SLINK_RX_FLUSH | SLINK_TX_FLUSH, SLINK_STATUS);
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tspi->cur = t;
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tspi->cur_pos = 0;
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tspi->cur_len = spi_tegra_fill_tx_fifo(tspi, t);
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spi_tegra_go(tspi);
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}
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static void spi_tegra_start_message(struct spi_device *spi,
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struct spi_message *m)
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{
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struct spi_transfer *t;
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m->actual_length = 0;
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m->status = 0;
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t = list_first_entry(&m->transfers, struct spi_transfer, transfer_list);
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spi_tegra_start_transfer(spi, t);
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}
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static void handle_spi_rx_dma_complete(struct spi_tegra_data *tspi)
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{
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unsigned long flags;
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struct spi_message *m;
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struct spi_device *spi;
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int timeout = 0;
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unsigned long val;
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/* the SPI controller may come back with both the BSY and RDY bits
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* set. In this case we need to wait for the BSY bit to clear so
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* that we are sure the DMA is finished. 1000 reads was empirically
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* determined to be long enough.
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*/
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while (timeout++ < 1000) {
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if (!(spi_tegra_readl(tspi, SLINK_STATUS) & SLINK_BSY))
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break;
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}
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spin_lock_irqsave(&tspi->lock, flags);
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val = spi_tegra_readl(tspi, SLINK_STATUS);
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val |= SLINK_RDY;
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spi_tegra_writel(tspi, val, SLINK_STATUS);
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m = list_first_entry(&tspi->queue, struct spi_message, queue);
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if (timeout >= 1000)
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m->status = -EIO;
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spi = m->state;
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tspi->cur_pos += spi_tegra_drain_rx_fifo(tspi, tspi->cur);
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m->actual_length += tspi->cur_pos;
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if (tspi->cur_pos < tspi->cur->len) {
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tspi->cur_len = spi_tegra_fill_tx_fifo(tspi, tspi->cur);
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spi_tegra_go(tspi);
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} else if (!list_is_last(&tspi->cur->transfer_list,
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&m->transfers)) {
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tspi->cur = list_first_entry(&tspi->cur->transfer_list,
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struct spi_transfer,
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transfer_list);
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spi_tegra_start_transfer(spi, tspi->cur);
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} else {
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list_del(&m->queue);
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m->complete(m->context);
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if (!list_empty(&tspi->queue)) {
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m = list_first_entry(&tspi->queue, struct spi_message,
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queue);
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spi = m->state;
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spi_tegra_start_message(spi, m);
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} else {
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clk_disable_unprepare(tspi->clk);
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tspi->cur_speed = 0;
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}
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}
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spin_unlock_irqrestore(&tspi->lock, flags);
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}
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#if defined(CONFIG_TEGRA_SYSTEM_DMA)
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static void tegra_spi_rx_dma_complete(struct tegra_dma_req *req)
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{
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struct spi_tegra_data *tspi = req->dev;
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handle_spi_rx_dma_complete(tspi);
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}
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#else
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static void tegra_spi_rx_dma_complete(void *args)
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{
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struct spi_tegra_data *tspi = args;
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handle_spi_rx_dma_complete(tspi);
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}
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#endif
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static int spi_tegra_setup(struct spi_device *spi)
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{
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struct spi_tegra_data *tspi = spi_master_get_devdata(spi->master);
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unsigned long cs_bit;
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unsigned long val;
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unsigned long flags;
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dev_dbg(&spi->dev, "setup %d bpw, %scpol, %scpha, %dHz\n",
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spi->bits_per_word,
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spi->mode & SPI_CPOL ? "" : "~",
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spi->mode & SPI_CPHA ? "" : "~",
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spi->max_speed_hz);
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switch (spi->chip_select) {
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case 0:
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cs_bit = SLINK_CS_POLARITY;
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break;
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case 1:
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cs_bit = SLINK_CS_POLARITY1;
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break;
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case 2:
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cs_bit = SLINK_CS_POLARITY2;
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break;
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case 4:
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cs_bit = SLINK_CS_POLARITY3;
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break;
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default:
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return -EINVAL;
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}
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spin_lock_irqsave(&tspi->lock, flags);
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val = spi_tegra_readl(tspi, SLINK_COMMAND);
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if (spi->mode & SPI_CS_HIGH)
|
|
val |= cs_bit;
|
|
else
|
|
val &= ~cs_bit;
|
|
spi_tegra_writel(tspi, val, SLINK_COMMAND);
|
|
|
|
spin_unlock_irqrestore(&tspi->lock, flags);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int spi_tegra_transfer(struct spi_device *spi, struct spi_message *m)
|
|
{
|
|
struct spi_tegra_data *tspi = spi_master_get_devdata(spi->master);
|
|
struct spi_transfer *t;
|
|
unsigned long flags;
|
|
int was_empty;
|
|
|
|
if (list_empty(&m->transfers) || !m->complete)
|
|
return -EINVAL;
|
|
|
|
list_for_each_entry(t, &m->transfers, transfer_list) {
|
|
if (t->bits_per_word < 0 || t->bits_per_word > 32)
|
|
return -EINVAL;
|
|
|
|
if (t->len == 0)
|
|
return -EINVAL;
|
|
|
|
if (!t->rx_buf && !t->tx_buf)
|
|
return -EINVAL;
|
|
}
|
|
|
|
m->state = spi;
|
|
|
|
spin_lock_irqsave(&tspi->lock, flags);
|
|
was_empty = list_empty(&tspi->queue);
|
|
list_add_tail(&m->queue, &tspi->queue);
|
|
|
|
if (was_empty)
|
|
spi_tegra_start_message(spi, m);
|
|
|
|
spin_unlock_irqrestore(&tspi->lock, flags);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int __devinit spi_tegra_probe(struct platform_device *pdev)
|
|
{
|
|
struct spi_master *master;
|
|
struct spi_tegra_data *tspi;
|
|
struct resource *r;
|
|
int ret;
|
|
#if !defined(CONFIG_TEGRA_SYSTEM_DMA)
|
|
dma_cap_mask_t mask;
|
|
#endif
|
|
|
|
master = spi_alloc_master(&pdev->dev, sizeof *tspi);
|
|
if (master == NULL) {
|
|
dev_err(&pdev->dev, "master allocation failed\n");
|
|
return -ENOMEM;
|
|
}
|
|
|
|
/* the spi->mode bits understood by this driver: */
|
|
master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
|
|
|
|
master->bus_num = pdev->id;
|
|
|
|
master->setup = spi_tegra_setup;
|
|
master->transfer = spi_tegra_transfer;
|
|
master->num_chipselect = 4;
|
|
|
|
dev_set_drvdata(&pdev->dev, master);
|
|
tspi = spi_master_get_devdata(master);
|
|
tspi->master = master;
|
|
tspi->pdev = pdev;
|
|
spin_lock_init(&tspi->lock);
|
|
|
|
r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
|
if (r == NULL) {
|
|
ret = -ENODEV;
|
|
goto err0;
|
|
}
|
|
|
|
if (!request_mem_region(r->start, resource_size(r),
|
|
dev_name(&pdev->dev))) {
|
|
ret = -EBUSY;
|
|
goto err0;
|
|
}
|
|
|
|
tspi->phys = r->start;
|
|
tspi->base = ioremap(r->start, resource_size(r));
|
|
if (!tspi->base) {
|
|
dev_err(&pdev->dev, "can't ioremap iomem\n");
|
|
ret = -ENOMEM;
|
|
goto err1;
|
|
}
|
|
|
|
tspi->clk = clk_get(&pdev->dev, NULL);
|
|
if (IS_ERR(tspi->clk)) {
|
|
dev_err(&pdev->dev, "can not get clock\n");
|
|
ret = PTR_ERR(tspi->clk);
|
|
goto err2;
|
|
}
|
|
|
|
INIT_LIST_HEAD(&tspi->queue);
|
|
|
|
#if defined(CONFIG_TEGRA_SYSTEM_DMA)
|
|
tspi->rx_dma = tegra_dma_allocate_channel(TEGRA_DMA_MODE_ONESHOT);
|
|
if (!tspi->rx_dma) {
|
|
dev_err(&pdev->dev, "can not allocate rx dma channel\n");
|
|
ret = -ENODEV;
|
|
goto err3;
|
|
}
|
|
#else
|
|
dma_cap_zero(mask);
|
|
dma_cap_set(DMA_SLAVE, mask);
|
|
tspi->rx_dma = dma_request_channel(mask, NULL, NULL);
|
|
if (!tspi->rx_dma) {
|
|
dev_err(&pdev->dev, "can not allocate rx dma channel\n");
|
|
ret = -ENODEV;
|
|
goto err3;
|
|
}
|
|
|
|
#endif
|
|
|
|
tspi->rx_bb = dma_alloc_coherent(&pdev->dev, sizeof(u32) * BB_LEN,
|
|
&tspi->rx_bb_phys, GFP_KERNEL);
|
|
if (!tspi->rx_bb) {
|
|
dev_err(&pdev->dev, "can not allocate rx bounce buffer\n");
|
|
ret = -ENOMEM;
|
|
goto err4;
|
|
}
|
|
|
|
#if defined(CONFIG_TEGRA_SYSTEM_DMA)
|
|
tspi->rx_dma_req.complete = tegra_spi_rx_dma_complete;
|
|
tspi->rx_dma_req.to_memory = 1;
|
|
tspi->rx_dma_req.dest_addr = tspi->rx_bb_phys;
|
|
tspi->rx_dma_req.dest_bus_width = 32;
|
|
tspi->rx_dma_req.source_addr = tspi->phys + SLINK_RX_FIFO;
|
|
tspi->rx_dma_req.source_bus_width = 32;
|
|
tspi->rx_dma_req.source_wrap = 4;
|
|
tspi->rx_dma_req.req_sel = spi_tegra_req_sels[pdev->id];
|
|
tspi->rx_dma_req.dev = tspi;
|
|
#else
|
|
/* Dmaengine Dma slave config */
|
|
tspi->sconfig.src_addr = tspi->phys + SLINK_RX_FIFO;
|
|
tspi->sconfig.dst_addr = tspi->phys + SLINK_RX_FIFO;
|
|
tspi->sconfig.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
|
|
tspi->sconfig.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
|
|
tspi->sconfig.slave_id = spi_tegra_req_sels[pdev->id];
|
|
tspi->sconfig.src_maxburst = 1;
|
|
tspi->sconfig.dst_maxburst = 1;
|
|
ret = dmaengine_device_control(tspi->rx_dma,
|
|
DMA_SLAVE_CONFIG, (unsigned long) &tspi->sconfig);
|
|
if (ret < 0) {
|
|
dev_err(&pdev->dev, "can not do slave configure for dma %d\n",
|
|
ret);
|
|
goto err4;
|
|
}
|
|
#endif
|
|
|
|
master->dev.of_node = pdev->dev.of_node;
|
|
ret = spi_register_master(master);
|
|
|
|
if (ret < 0)
|
|
goto err5;
|
|
|
|
return ret;
|
|
|
|
err5:
|
|
dma_free_coherent(&pdev->dev, sizeof(u32) * BB_LEN,
|
|
tspi->rx_bb, tspi->rx_bb_phys);
|
|
err4:
|
|
#if defined(CONFIG_TEGRA_SYSTEM_DMA)
|
|
tegra_dma_free_channel(tspi->rx_dma);
|
|
#else
|
|
dma_release_channel(tspi->rx_dma);
|
|
#endif
|
|
err3:
|
|
clk_put(tspi->clk);
|
|
err2:
|
|
iounmap(tspi->base);
|
|
err1:
|
|
release_mem_region(r->start, resource_size(r));
|
|
err0:
|
|
spi_master_put(master);
|
|
return ret;
|
|
}
|
|
|
|
static int __devexit spi_tegra_remove(struct platform_device *pdev)
|
|
{
|
|
struct spi_master *master;
|
|
struct spi_tegra_data *tspi;
|
|
struct resource *r;
|
|
|
|
master = dev_get_drvdata(&pdev->dev);
|
|
tspi = spi_master_get_devdata(master);
|
|
|
|
spi_unregister_master(master);
|
|
#if defined(CONFIG_TEGRA_SYSTEM_DMA)
|
|
tegra_dma_free_channel(tspi->rx_dma);
|
|
#else
|
|
dma_release_channel(tspi->rx_dma);
|
|
#endif
|
|
|
|
dma_free_coherent(&pdev->dev, sizeof(u32) * BB_LEN,
|
|
tspi->rx_bb, tspi->rx_bb_phys);
|
|
|
|
clk_put(tspi->clk);
|
|
iounmap(tspi->base);
|
|
|
|
r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
|
release_mem_region(r->start, resource_size(r));
|
|
|
|
return 0;
|
|
}
|
|
|
|
MODULE_ALIAS("platform:spi_tegra");
|
|
|
|
#ifdef CONFIG_OF
|
|
static struct of_device_id spi_tegra_of_match_table[] __devinitdata = {
|
|
{ .compatible = "nvidia,tegra20-spi", },
|
|
{}
|
|
};
|
|
MODULE_DEVICE_TABLE(of, spi_tegra_of_match_table);
|
|
#else /* CONFIG_OF */
|
|
#define spi_tegra_of_match_table NULL
|
|
#endif /* CONFIG_OF */
|
|
|
|
static struct platform_driver spi_tegra_driver = {
|
|
.driver = {
|
|
.name = "spi_tegra",
|
|
.owner = THIS_MODULE,
|
|
.of_match_table = spi_tegra_of_match_table,
|
|
},
|
|
.probe = spi_tegra_probe,
|
|
.remove = __devexit_p(spi_tegra_remove),
|
|
};
|
|
module_platform_driver(spi_tegra_driver);
|
|
|
|
MODULE_LICENSE("GPL");
|