203 строки
4.4 KiB
C
203 строки
4.4 KiB
C
/*
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* linux/arch/alpha/kernel/core_polaris.c
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*
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* POLARIS chip-specific code
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*/
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#define __EXTERN_INLINE inline
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#include <asm/io.h>
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#include <asm/core_polaris.h>
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#undef __EXTERN_INLINE
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#include <linux/types.h>
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#include <linux/pci.h>
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#include <linux/sched.h>
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#include <linux/init.h>
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#include <asm/ptrace.h>
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#include "proto.h"
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#include "pci_impl.h"
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/*
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* BIOS32-style PCI interface:
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*/
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#define DEBUG_CONFIG 0
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#if DEBUG_CONFIG
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# define DBG_CFG(args) printk args
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#else
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# define DBG_CFG(args)
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#endif
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/*
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* Given a bus, device, and function number, compute resulting
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* configuration space address. This is fairly straightforward
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* on POLARIS, since the chip itself generates Type 0 or Type 1
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* cycles automatically depending on the bus number (Bus 0 is
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* hardwired to Type 0, all others are Type 1. Peer bridges
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* are not supported).
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*
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* All types:
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*
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* 3 3 3 3|3 3 3 3|3 3 2 2|2 2 2 2|2 2 2 2|1 1 1 1|1 1 1 1|1 1
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* 9 8 7 6|5 4 3 2|1 0 9 8|7 6 5 4|3 2 1 0|9 8 7 6|5 4 3 2|1 0 9 8|7 6 5 4|3 2 1 0
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* +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
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* |1|1|1|1|1|0|0|1|1|1|1|1|1|1|1|0|B|B|B|B|B|B|B|B|D|D|D|D|D|F|F|F|R|R|R|R|R|R|x|x|
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* +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
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*
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* 23:16 bus number (8 bits = 128 possible buses)
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* 15:11 Device number (5 bits)
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* 10:8 function number
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* 7:2 register number
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*
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* Notes:
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* The function number selects which function of a multi-function device
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* (e.g., scsi and ethernet).
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*
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* The register selects a DWORD (32 bit) register offset. Hence it
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* doesn't get shifted by 2 bits as we want to "drop" the bottom two
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* bits.
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*/
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static int
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mk_conf_addr(struct pci_bus *pbus, unsigned int device_fn, int where,
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unsigned long *pci_addr, u8 *type1)
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{
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u8 bus = pbus->number;
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*type1 = (bus == 0) ? 0 : 1;
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*pci_addr = (bus << 16) | (device_fn << 8) | (where) |
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POLARIS_DENSE_CONFIG_BASE;
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DBG_CFG(("mk_conf_addr(bus=%d ,device_fn=0x%x, where=0x%x,"
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" returning address 0x%p\n"
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bus, device_fn, where, *pci_addr));
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return 0;
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}
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static int
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polaris_read_config(struct pci_bus *bus, unsigned int devfn, int where,
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int size, u32 *value)
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{
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unsigned long addr;
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unsigned char type1;
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if (mk_conf_addr(bus, devfn, where, &addr, &type1))
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return PCIBIOS_DEVICE_NOT_FOUND;
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switch (size) {
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case 1:
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*value = __kernel_ldbu(*(vucp)addr);
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break;
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case 2:
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*value = __kernel_ldwu(*(vusp)addr);
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break;
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case 4:
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*value = *(vuip)addr;
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break;
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}
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return PCIBIOS_SUCCESSFUL;
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}
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static int
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polaris_write_config(struct pci_bus *bus, unsigned int devfn, int where,
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int size, u32 value)
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{
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unsigned long addr;
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unsigned char type1;
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if (mk_conf_addr(bus, devfn, where, &addr, &type1))
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return PCIBIOS_DEVICE_NOT_FOUND;
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switch (size) {
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case 1:
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__kernel_stb(value, *(vucp)addr);
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mb();
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__kernel_ldbu(*(vucp)addr);
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break;
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case 2:
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__kernel_stw(value, *(vusp)addr);
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mb();
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__kernel_ldwu(*(vusp)addr);
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break;
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case 4:
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*(vuip)addr = value;
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mb();
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*(vuip)addr;
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break;
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}
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return PCIBIOS_SUCCESSFUL;
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}
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struct pci_ops polaris_pci_ops =
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{
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.read = polaris_read_config,
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.write = polaris_write_config,
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};
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void __init
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polaris_init_arch(void)
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{
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struct pci_controller *hose;
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/* May need to initialize error reporting (see PCICTL0/1), but
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* for now assume that the firmware has done the right thing
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* already.
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*/
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#if 0
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printk("polaris_init_arch(): trusting firmware for setup\n");
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#endif
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/*
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* Create our single hose.
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*/
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pci_isa_hose = hose = alloc_pci_controller();
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hose->io_space = &ioport_resource;
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hose->mem_space = &iomem_resource;
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hose->index = 0;
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hose->sparse_mem_base = 0;
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hose->dense_mem_base = POLARIS_DENSE_MEM_BASE - IDENT_ADDR;
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hose->sparse_io_base = 0;
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hose->dense_io_base = POLARIS_DENSE_IO_BASE - IDENT_ADDR;
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hose->sg_isa = hose->sg_pci = NULL;
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/* The I/O window is fixed at 2G @ 2G. */
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__direct_map_base = 0x80000000;
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__direct_map_size = 0x80000000;
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}
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static inline void
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polaris_pci_clr_err(void)
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{
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*(vusp)POLARIS_W_STATUS;
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/* Write 1's to settable bits to clear errors */
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*(vusp)POLARIS_W_STATUS = 0x7800;
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mb();
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*(vusp)POLARIS_W_STATUS;
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}
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void
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polaris_machine_check(unsigned long vector, unsigned long la_ptr)
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{
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/* Clear the error before any reporting. */
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mb();
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mb();
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draina();
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polaris_pci_clr_err();
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wrmces(0x7);
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mb();
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process_mcheck_info(vector, la_ptr, "POLARIS",
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mcheck_expected(0));
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}
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