241 строка
6.6 KiB
C
241 строка
6.6 KiB
C
/*
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* arch/arm/mach-orion5x/addr-map.c
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*
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* Address map functions for Marvell Orion 5x SoCs
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*
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* Maintainer: Tzachi Perelstein <tzachi@marvell.com>
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/mbus.h>
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#include <asm/hardware.h>
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#include <asm/io.h>
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#include "common.h"
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/*
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* The Orion has fully programable address map. There's a separate address
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* map for each of the device _master_ interfaces, e.g. CPU, PCI, PCIE, USB,
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* Gigabit Ethernet, DMA/XOR engines, etc. Each interface has its own
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* address decode windows that allow it to access any of the Orion resources.
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*
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* CPU address decoding --
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* Linux assumes that it is the boot loader that already setup the access to
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* DDR and internal registers.
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* Setup access to PCI and PCI-E IO/MEM space is issued by this file.
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* Setup access to various devices located on the device bus interface (e.g.
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* flashes, RTC, etc) should be issued by machine-setup.c according to
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* specific board population (by using orion5x_setup_*_win()).
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*
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* Non-CPU Masters address decoding --
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* Unlike the CPU, we setup the access from Orion's master interfaces to DDR
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* banks only (the typical use case).
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* Setup access for each master to DDR is issued by common.c.
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*
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* Note: although orion_setbits() and orion_clrbits() are not atomic
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* no locking is necessary here since code in this file is only called
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* at boot time when there is no concurrency issues.
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*/
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/*
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* Generic Address Decode Windows bit settings
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*/
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#define TARGET_DDR 0
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#define TARGET_DEV_BUS 1
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#define TARGET_PCI 3
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#define TARGET_PCIE 4
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#define ATTR_DDR_CS(n) (((n) ==0) ? 0xe : \
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((n) == 1) ? 0xd : \
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((n) == 2) ? 0xb : \
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((n) == 3) ? 0x7 : 0xf)
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#define ATTR_PCIE_MEM 0x59
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#define ATTR_PCIE_IO 0x51
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#define ATTR_PCIE_WA 0x79
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#define ATTR_PCI_MEM 0x59
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#define ATTR_PCI_IO 0x51
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#define ATTR_DEV_CS0 0x1e
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#define ATTR_DEV_CS1 0x1d
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#define ATTR_DEV_CS2 0x1b
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#define ATTR_DEV_BOOT 0xf
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#define WIN_EN 1
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/*
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* Helpers to get DDR bank info
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*/
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#define DDR_BASE_CS(n) ORION5X_DDR_REG(0x1500 + ((n) * 8))
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#define DDR_SIZE_CS(n) ORION5X_DDR_REG(0x1504 + ((n) * 8))
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#define DDR_MAX_CS 4
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#define DDR_REG_TO_SIZE(reg) (((reg) | 0xffffff) + 1)
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#define DDR_REG_TO_BASE(reg) ((reg) & 0xff000000)
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#define DDR_BANK_EN 1
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/*
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* CPU Address Decode Windows registers
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*/
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#define CPU_WIN_CTRL(n) ORION5X_BRIDGE_REG(0x000 | ((n) << 4))
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#define CPU_WIN_BASE(n) ORION5X_BRIDGE_REG(0x004 | ((n) << 4))
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#define CPU_WIN_REMAP_LO(n) ORION5X_BRIDGE_REG(0x008 | ((n) << 4))
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#define CPU_WIN_REMAP_HI(n) ORION5X_BRIDGE_REG(0x00c | ((n) << 4))
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/*
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* Gigabit Ethernet Address Decode Windows registers
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*/
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#define ETH_WIN_BASE(win) ORION5X_ETH_REG(0x200 + ((win) * 8))
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#define ETH_WIN_SIZE(win) ORION5X_ETH_REG(0x204 + ((win) * 8))
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#define ETH_WIN_REMAP(win) ORION5X_ETH_REG(0x280 + ((win) * 4))
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#define ETH_WIN_EN ORION5X_ETH_REG(0x290)
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#define ETH_WIN_PROT ORION5X_ETH_REG(0x294)
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#define ETH_MAX_WIN 6
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#define ETH_MAX_REMAP_WIN 4
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struct mbus_dram_target_info orion5x_mbus_dram_info;
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static int __init orion5x_cpu_win_can_remap(int win)
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{
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u32 dev, rev;
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orion5x_pcie_id(&dev, &rev);
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if ((dev == MV88F5281_DEV_ID && win < 4)
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|| (dev == MV88F5182_DEV_ID && win < 2)
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|| (dev == MV88F5181_DEV_ID && win < 2))
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return 1;
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return 0;
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}
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static void __init setup_cpu_win(int win, u32 base, u32 size,
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u8 target, u8 attr, int remap)
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{
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orion5x_write(CPU_WIN_BASE(win), base & 0xffff0000);
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orion5x_write(CPU_WIN_CTRL(win),
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((size - 1) & 0xffff0000) | (attr << 8) | (target << 4) | 1);
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if (orion5x_cpu_win_can_remap(win)) {
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if (remap < 0)
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remap = base;
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orion5x_write(CPU_WIN_REMAP_LO(win), remap & 0xffff0000);
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orion5x_write(CPU_WIN_REMAP_HI(win), 0);
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}
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}
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void __init orion5x_setup_cpu_mbus_bridge(void)
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{
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int i;
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int cs;
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/*
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* First, disable and clear windows.
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*/
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for (i = 0; i < 8; i++) {
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orion5x_write(CPU_WIN_BASE(i), 0);
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orion5x_write(CPU_WIN_CTRL(i), 0);
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if (orion5x_cpu_win_can_remap(i)) {
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orion5x_write(CPU_WIN_REMAP_LO(i), 0);
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orion5x_write(CPU_WIN_REMAP_HI(i), 0);
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}
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}
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/*
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* Setup windows for PCI+PCIe IO+MEM space.
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*/
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setup_cpu_win(0, ORION5X_PCIE_IO_PHYS_BASE, ORION5X_PCIE_IO_SIZE,
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TARGET_PCIE, ATTR_PCIE_IO, ORION5X_PCIE_IO_BUS_BASE);
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setup_cpu_win(1, ORION5X_PCI_IO_PHYS_BASE, ORION5X_PCI_IO_SIZE,
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TARGET_PCI, ATTR_PCI_IO, ORION5X_PCI_IO_BUS_BASE);
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setup_cpu_win(2, ORION5X_PCIE_MEM_PHYS_BASE, ORION5X_PCIE_MEM_SIZE,
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TARGET_PCIE, ATTR_PCIE_MEM, -1);
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setup_cpu_win(3, ORION5X_PCI_MEM_PHYS_BASE, ORION5X_PCI_MEM_SIZE,
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TARGET_PCI, ATTR_PCI_MEM, -1);
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/*
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* Setup MBUS dram target info.
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*/
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orion5x_mbus_dram_info.mbus_dram_target_id = TARGET_DDR;
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for (i = 0, cs = 0; i < 4; i++) {
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u32 base = readl(DDR_BASE_CS(i));
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u32 size = readl(DDR_SIZE_CS(i));
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/*
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* Chip select enabled?
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*/
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if (size & 1) {
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struct mbus_dram_window *w;
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w = &orion5x_mbus_dram_info.cs[cs++];
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w->cs_index = i;
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w->mbus_attr = 0xf & ~(1 << i);
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w->base = base & 0xff000000;
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w->size = (size | 0x00ffffff) + 1;
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}
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}
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orion5x_mbus_dram_info.num_cs = cs;
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}
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void __init orion5x_setup_dev_boot_win(u32 base, u32 size)
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{
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setup_cpu_win(4, base, size, TARGET_DEV_BUS, ATTR_DEV_BOOT, -1);
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}
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void __init orion5x_setup_dev0_win(u32 base, u32 size)
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{
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setup_cpu_win(5, base, size, TARGET_DEV_BUS, ATTR_DEV_CS0, -1);
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}
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void __init orion5x_setup_dev1_win(u32 base, u32 size)
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{
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setup_cpu_win(6, base, size, TARGET_DEV_BUS, ATTR_DEV_CS1, -1);
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}
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void __init orion5x_setup_dev2_win(u32 base, u32 size)
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{
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setup_cpu_win(7, base, size, TARGET_DEV_BUS, ATTR_DEV_CS2, -1);
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}
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void __init orion5x_setup_pcie_wa_win(u32 base, u32 size)
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{
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setup_cpu_win(7, base, size, TARGET_PCIE, ATTR_PCIE_WA, -1);
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}
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void __init orion5x_setup_eth_wins(void)
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{
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int i;
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/*
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* First, disable and clear windows
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*/
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for (i = 0; i < ETH_MAX_WIN; i++) {
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orion5x_write(ETH_WIN_BASE(i), 0);
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orion5x_write(ETH_WIN_SIZE(i), 0);
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orion5x_setbits(ETH_WIN_EN, 1 << i);
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orion5x_clrbits(ETH_WIN_PROT, 0x3 << (i * 2));
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if (i < ETH_MAX_REMAP_WIN)
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orion5x_write(ETH_WIN_REMAP(i), 0);
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}
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/*
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* Setup windows for DDR banks.
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*/
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for (i = 0; i < DDR_MAX_CS; i++) {
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u32 base, size;
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size = orion5x_read(DDR_SIZE_CS(i));
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base = orion5x_read(DDR_BASE_CS(i));
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if (size & DDR_BANK_EN) {
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base = DDR_REG_TO_BASE(base);
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size = DDR_REG_TO_SIZE(size);
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orion5x_write(ETH_WIN_SIZE(i), (size-1) & 0xffff0000);
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orion5x_write(ETH_WIN_BASE(i), (base & 0xffff0000) |
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(ATTR_DDR_CS(i) << 8) |
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TARGET_DDR);
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orion5x_clrbits(ETH_WIN_EN, 1 << i);
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orion5x_setbits(ETH_WIN_PROT, 0x3 << (i * 2));
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}
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}
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}
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