476 строки
12 KiB
C
476 строки
12 KiB
C
/*
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* Nvidia AGPGART routines.
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* Based upon a 2.4 agpgart diff by the folks from NVIDIA, and hacked up
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* to work in 2.5 by Dave Jones <davej@redhat.com>
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*/
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#include <linux/module.h>
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#include <linux/pci.h>
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#include <linux/init.h>
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#include <linux/agp_backend.h>
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#include <linux/page-flags.h>
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#include <linux/mm.h>
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#include <linux/jiffies.h>
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#include "agp.h"
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/* NVIDIA registers */
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#define NVIDIA_0_APSIZE 0x80
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#define NVIDIA_1_WBC 0xf0
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#define NVIDIA_2_GARTCTRL 0xd0
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#define NVIDIA_2_APBASE 0xd8
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#define NVIDIA_2_APLIMIT 0xdc
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#define NVIDIA_2_ATTBASE(i) (0xe0 + (i) * 4)
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#define NVIDIA_3_APBASE 0x50
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#define NVIDIA_3_APLIMIT 0x54
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static struct _nvidia_private {
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struct pci_dev *dev_1;
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struct pci_dev *dev_2;
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struct pci_dev *dev_3;
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volatile u32 __iomem *aperture;
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int num_active_entries;
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off_t pg_offset;
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u32 wbc_mask;
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} nvidia_private;
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static int nvidia_fetch_size(void)
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{
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int i;
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u8 size_value;
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struct aper_size_info_8 *values;
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pci_read_config_byte(agp_bridge->dev, NVIDIA_0_APSIZE, &size_value);
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size_value &= 0x0f;
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values = A_SIZE_8(agp_bridge->driver->aperture_sizes);
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for (i = 0; i < agp_bridge->driver->num_aperture_sizes; i++) {
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if (size_value == values[i].size_value) {
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agp_bridge->previous_size =
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agp_bridge->current_size = (void *) (values + i);
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agp_bridge->aperture_size_idx = i;
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return values[i].size;
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}
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}
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return 0;
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}
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#define SYSCFG 0xC0010010
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#define IORR_BASE0 0xC0010016
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#define IORR_MASK0 0xC0010017
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#define AMD_K7_NUM_IORR 2
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static int nvidia_init_iorr(u32 base, u32 size)
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{
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u32 base_hi, base_lo;
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u32 mask_hi, mask_lo;
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u32 sys_hi, sys_lo;
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u32 iorr_addr, free_iorr_addr;
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/* Find the iorr that is already used for the base */
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/* If not found, determine the uppermost available iorr */
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free_iorr_addr = AMD_K7_NUM_IORR;
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for (iorr_addr = 0; iorr_addr < AMD_K7_NUM_IORR; iorr_addr++) {
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rdmsr(IORR_BASE0 + 2 * iorr_addr, base_lo, base_hi);
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rdmsr(IORR_MASK0 + 2 * iorr_addr, mask_lo, mask_hi);
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if ((base_lo & 0xfffff000) == (base & 0xfffff000))
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break;
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if ((mask_lo & 0x00000800) == 0)
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free_iorr_addr = iorr_addr;
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}
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if (iorr_addr >= AMD_K7_NUM_IORR) {
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iorr_addr = free_iorr_addr;
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if (iorr_addr >= AMD_K7_NUM_IORR)
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return -EINVAL;
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}
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base_hi = 0x0;
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base_lo = (base & ~0xfff) | 0x18;
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mask_hi = 0xf;
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mask_lo = ((~(size - 1)) & 0xfffff000) | 0x800;
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wrmsr(IORR_BASE0 + 2 * iorr_addr, base_lo, base_hi);
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wrmsr(IORR_MASK0 + 2 * iorr_addr, mask_lo, mask_hi);
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rdmsr(SYSCFG, sys_lo, sys_hi);
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sys_lo |= 0x00100000;
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wrmsr(SYSCFG, sys_lo, sys_hi);
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return 0;
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}
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static int nvidia_configure(void)
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{
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int i, rc, num_dirs;
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u32 apbase, aplimit;
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struct aper_size_info_8 *current_size;
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u32 temp;
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current_size = A_SIZE_8(agp_bridge->current_size);
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/* aperture size */
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pci_write_config_byte(agp_bridge->dev, NVIDIA_0_APSIZE,
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current_size->size_value);
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/* address to map to */
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pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &apbase);
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apbase &= PCI_BASE_ADDRESS_MEM_MASK;
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agp_bridge->gart_bus_addr = apbase;
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aplimit = apbase + (current_size->size * 1024 * 1024) - 1;
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pci_write_config_dword(nvidia_private.dev_2, NVIDIA_2_APBASE, apbase);
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pci_write_config_dword(nvidia_private.dev_2, NVIDIA_2_APLIMIT, aplimit);
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pci_write_config_dword(nvidia_private.dev_3, NVIDIA_3_APBASE, apbase);
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pci_write_config_dword(nvidia_private.dev_3, NVIDIA_3_APLIMIT, aplimit);
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if (0 != (rc = nvidia_init_iorr(apbase, current_size->size * 1024 * 1024)))
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return rc;
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/* directory size is 64k */
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num_dirs = current_size->size / 64;
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nvidia_private.num_active_entries = current_size->num_entries;
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nvidia_private.pg_offset = 0;
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if (num_dirs == 0) {
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num_dirs = 1;
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nvidia_private.num_active_entries /= (64 / current_size->size);
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nvidia_private.pg_offset = (apbase & (64 * 1024 * 1024 - 1) &
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~(current_size->size * 1024 * 1024 - 1)) / PAGE_SIZE;
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}
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/* attbase */
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for (i = 0; i < 8; i++) {
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pci_write_config_dword(nvidia_private.dev_2, NVIDIA_2_ATTBASE(i),
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(agp_bridge->gatt_bus_addr + (i % num_dirs) * 64 * 1024) | 1);
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}
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/* gtlb control */
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pci_read_config_dword(nvidia_private.dev_2, NVIDIA_2_GARTCTRL, &temp);
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pci_write_config_dword(nvidia_private.dev_2, NVIDIA_2_GARTCTRL, temp | 0x11);
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/* gart control */
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pci_read_config_dword(agp_bridge->dev, NVIDIA_0_APSIZE, &temp);
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pci_write_config_dword(agp_bridge->dev, NVIDIA_0_APSIZE, temp | 0x100);
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/* map aperture */
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nvidia_private.aperture =
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(volatile u32 __iomem *) ioremap(apbase, 33 * PAGE_SIZE);
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if (!nvidia_private.aperture)
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return -ENOMEM;
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return 0;
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}
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static void nvidia_cleanup(void)
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{
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struct aper_size_info_8 *previous_size;
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u32 temp;
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/* gart control */
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pci_read_config_dword(agp_bridge->dev, NVIDIA_0_APSIZE, &temp);
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pci_write_config_dword(agp_bridge->dev, NVIDIA_0_APSIZE, temp & ~(0x100));
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/* gtlb control */
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pci_read_config_dword(nvidia_private.dev_2, NVIDIA_2_GARTCTRL, &temp);
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pci_write_config_dword(nvidia_private.dev_2, NVIDIA_2_GARTCTRL, temp & ~(0x11));
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/* unmap aperture */
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iounmap((void __iomem *) nvidia_private.aperture);
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/* restore previous aperture size */
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previous_size = A_SIZE_8(agp_bridge->previous_size);
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pci_write_config_byte(agp_bridge->dev, NVIDIA_0_APSIZE,
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previous_size->size_value);
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/* restore iorr for previous aperture size */
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nvidia_init_iorr(agp_bridge->gart_bus_addr,
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previous_size->size * 1024 * 1024);
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}
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/*
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* Note we can't use the generic routines, even though they are 99% the same.
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* Aperture sizes <64M still requires a full 64k GART directory, but
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* only use the portion of the TLB entries that correspond to the apertures
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* alignment inside the surrounding 64M block.
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*/
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extern int agp_memory_reserved;
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static int nvidia_insert_memory(struct agp_memory *mem, off_t pg_start, int type)
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{
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int i, j;
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int mask_type;
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mask_type = agp_generic_type_to_mask_type(mem->bridge, type);
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if (mask_type != 0 || type != mem->type)
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return -EINVAL;
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if (mem->page_count == 0)
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return 0;
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if ((pg_start + mem->page_count) >
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(nvidia_private.num_active_entries - agp_memory_reserved/PAGE_SIZE))
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return -EINVAL;
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for (j = pg_start; j < (pg_start + mem->page_count); j++) {
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if (!PGE_EMPTY(agp_bridge, readl(agp_bridge->gatt_table+nvidia_private.pg_offset+j)))
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return -EBUSY;
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}
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if (!mem->is_flushed) {
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global_cache_flush();
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mem->is_flushed = true;
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}
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for (i = 0, j = pg_start; i < mem->page_count; i++, j++) {
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writel(agp_bridge->driver->mask_memory(agp_bridge,
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page_to_phys(mem->pages[i]), mask_type),
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agp_bridge->gatt_table+nvidia_private.pg_offset+j);
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}
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/* PCI Posting. */
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readl(agp_bridge->gatt_table+nvidia_private.pg_offset+j - 1);
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agp_bridge->driver->tlb_flush(mem);
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return 0;
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}
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static int nvidia_remove_memory(struct agp_memory *mem, off_t pg_start, int type)
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{
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int i;
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int mask_type;
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mask_type = agp_generic_type_to_mask_type(mem->bridge, type);
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if (mask_type != 0 || type != mem->type)
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return -EINVAL;
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if (mem->page_count == 0)
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return 0;
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for (i = pg_start; i < (mem->page_count + pg_start); i++)
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writel(agp_bridge->scratch_page, agp_bridge->gatt_table+nvidia_private.pg_offset+i);
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agp_bridge->driver->tlb_flush(mem);
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return 0;
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}
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static void nvidia_tlbflush(struct agp_memory *mem)
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{
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unsigned long end;
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u32 wbc_reg, temp;
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int i;
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/* flush chipset */
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if (nvidia_private.wbc_mask) {
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pci_read_config_dword(nvidia_private.dev_1, NVIDIA_1_WBC, &wbc_reg);
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wbc_reg |= nvidia_private.wbc_mask;
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pci_write_config_dword(nvidia_private.dev_1, NVIDIA_1_WBC, wbc_reg);
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end = jiffies + 3*HZ;
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do {
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pci_read_config_dword(nvidia_private.dev_1,
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NVIDIA_1_WBC, &wbc_reg);
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if (time_before_eq(end, jiffies)) {
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printk(KERN_ERR PFX
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"TLB flush took more than 3 seconds.\n");
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}
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} while (wbc_reg & nvidia_private.wbc_mask);
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}
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/* flush TLB entries */
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for (i = 0; i < 32 + 1; i++)
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temp = readl(nvidia_private.aperture+(i * PAGE_SIZE / sizeof(u32)));
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for (i = 0; i < 32 + 1; i++)
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temp = readl(nvidia_private.aperture+(i * PAGE_SIZE / sizeof(u32)));
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}
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static const struct aper_size_info_8 nvidia_generic_sizes[5] =
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{
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{512, 131072, 7, 0},
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{256, 65536, 6, 8},
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{128, 32768, 5, 12},
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{64, 16384, 4, 14},
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/* The 32M mode still requires a 64k gatt */
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{32, 16384, 4, 15}
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};
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static const struct gatt_mask nvidia_generic_masks[] =
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{
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{ .mask = 1, .type = 0}
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};
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static const struct agp_bridge_driver nvidia_driver = {
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.owner = THIS_MODULE,
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.aperture_sizes = nvidia_generic_sizes,
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.size_type = U8_APER_SIZE,
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.num_aperture_sizes = 5,
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.needs_scratch_page = true,
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.configure = nvidia_configure,
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.fetch_size = nvidia_fetch_size,
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.cleanup = nvidia_cleanup,
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.tlb_flush = nvidia_tlbflush,
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.mask_memory = agp_generic_mask_memory,
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.masks = nvidia_generic_masks,
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.agp_enable = agp_generic_enable,
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.cache_flush = global_cache_flush,
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.create_gatt_table = agp_generic_create_gatt_table,
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.free_gatt_table = agp_generic_free_gatt_table,
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.insert_memory = nvidia_insert_memory,
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.remove_memory = nvidia_remove_memory,
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.alloc_by_type = agp_generic_alloc_by_type,
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.free_by_type = agp_generic_free_by_type,
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.agp_alloc_page = agp_generic_alloc_page,
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.agp_alloc_pages = agp_generic_alloc_pages,
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.agp_destroy_page = agp_generic_destroy_page,
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.agp_destroy_pages = agp_generic_destroy_pages,
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.agp_type_to_mask_type = agp_generic_type_to_mask_type,
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};
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static int agp_nvidia_probe(struct pci_dev *pdev,
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const struct pci_device_id *ent)
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{
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struct agp_bridge_data *bridge;
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u8 cap_ptr;
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nvidia_private.dev_1 =
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pci_get_bus_and_slot((unsigned int)pdev->bus->number, PCI_DEVFN(0, 1));
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nvidia_private.dev_2 =
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pci_get_bus_and_slot((unsigned int)pdev->bus->number, PCI_DEVFN(0, 2));
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nvidia_private.dev_3 =
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pci_get_bus_and_slot((unsigned int)pdev->bus->number, PCI_DEVFN(30, 0));
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if (!nvidia_private.dev_1 || !nvidia_private.dev_2 || !nvidia_private.dev_3) {
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printk(KERN_INFO PFX "Detected an NVIDIA nForce/nForce2 "
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"chipset, but could not find the secondary devices.\n");
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return -ENODEV;
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}
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cap_ptr = pci_find_capability(pdev, PCI_CAP_ID_AGP);
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if (!cap_ptr)
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return -ENODEV;
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switch (pdev->device) {
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case PCI_DEVICE_ID_NVIDIA_NFORCE:
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printk(KERN_INFO PFX "Detected NVIDIA nForce chipset\n");
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nvidia_private.wbc_mask = 0x00010000;
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break;
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case PCI_DEVICE_ID_NVIDIA_NFORCE2:
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printk(KERN_INFO PFX "Detected NVIDIA nForce2 chipset\n");
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nvidia_private.wbc_mask = 0x80000000;
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break;
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default:
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printk(KERN_ERR PFX "Unsupported NVIDIA chipset (device id: %04x)\n",
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pdev->device);
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return -ENODEV;
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}
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bridge = agp_alloc_bridge();
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if (!bridge)
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return -ENOMEM;
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bridge->driver = &nvidia_driver;
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bridge->dev_private_data = &nvidia_private,
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bridge->dev = pdev;
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bridge->capndx = cap_ptr;
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/* Fill in the mode register */
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pci_read_config_dword(pdev,
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bridge->capndx+PCI_AGP_STATUS,
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&bridge->mode);
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pci_set_drvdata(pdev, bridge);
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return agp_add_bridge(bridge);
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}
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static void agp_nvidia_remove(struct pci_dev *pdev)
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{
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struct agp_bridge_data *bridge = pci_get_drvdata(pdev);
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agp_remove_bridge(bridge);
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agp_put_bridge(bridge);
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}
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#ifdef CONFIG_PM
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static int agp_nvidia_suspend(struct pci_dev *pdev, pm_message_t state)
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{
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pci_save_state(pdev);
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pci_set_power_state(pdev, PCI_D3hot);
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return 0;
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}
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static int agp_nvidia_resume(struct pci_dev *pdev)
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{
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/* set power state 0 and restore PCI space */
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pci_set_power_state(pdev, PCI_D0);
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pci_restore_state(pdev);
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/* reconfigure AGP hardware again */
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nvidia_configure();
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return 0;
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}
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#endif
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static struct pci_device_id agp_nvidia_pci_table[] = {
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{
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.class = (PCI_CLASS_BRIDGE_HOST << 8),
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.class_mask = ~0,
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.vendor = PCI_VENDOR_ID_NVIDIA,
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.device = PCI_DEVICE_ID_NVIDIA_NFORCE,
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.subvendor = PCI_ANY_ID,
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.subdevice = PCI_ANY_ID,
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},
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{
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.class = (PCI_CLASS_BRIDGE_HOST << 8),
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.class_mask = ~0,
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.vendor = PCI_VENDOR_ID_NVIDIA,
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.device = PCI_DEVICE_ID_NVIDIA_NFORCE2,
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.subvendor = PCI_ANY_ID,
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.subdevice = PCI_ANY_ID,
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},
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{ }
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};
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MODULE_DEVICE_TABLE(pci, agp_nvidia_pci_table);
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static struct pci_driver agp_nvidia_pci_driver = {
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.name = "agpgart-nvidia",
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.id_table = agp_nvidia_pci_table,
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.probe = agp_nvidia_probe,
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.remove = agp_nvidia_remove,
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#ifdef CONFIG_PM
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.suspend = agp_nvidia_suspend,
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.resume = agp_nvidia_resume,
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#endif
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};
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static int __init agp_nvidia_init(void)
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{
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if (agp_off)
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return -EINVAL;
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return pci_register_driver(&agp_nvidia_pci_driver);
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}
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static void __exit agp_nvidia_cleanup(void)
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{
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pci_unregister_driver(&agp_nvidia_pci_driver);
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pci_dev_put(nvidia_private.dev_1);
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pci_dev_put(nvidia_private.dev_2);
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pci_dev_put(nvidia_private.dev_3);
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}
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module_init(agp_nvidia_init);
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module_exit(agp_nvidia_cleanup);
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MODULE_LICENSE("GPL and additional rights");
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MODULE_AUTHOR("NVIDIA Corporation");
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