357 строки
12 KiB
C
357 строки
12 KiB
C
/* bnx2x_init.h: Broadcom Everest network driver.
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* Structures and macroes needed during the initialization.
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*
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* Copyright (c) 2007-2009 Broadcom Corporation
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation.
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*
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* Maintained by: Eilon Greenstein <eilong@broadcom.com>
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* Written by: Eliezer Tamir
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* Modified by: Vladislav Zolotarov <vladz@broadcom.com>
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*/
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#ifndef BNX2X_INIT_H
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#define BNX2X_INIT_H
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#define COMMON 0x1
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#define PORT0 0x2
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#define PORT1 0x4
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#define INIT_EMULATION 0x1
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#define INIT_FPGA 0x2
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#define INIT_ASIC 0x4
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#define INIT_HARDWARE 0x7
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#define TSTORM_INTMEM_ADDR TSEM_REG_FAST_MEMORY
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#define CSTORM_INTMEM_ADDR CSEM_REG_FAST_MEMORY
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#define XSTORM_INTMEM_ADDR XSEM_REG_FAST_MEMORY
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#define USTORM_INTMEM_ADDR USEM_REG_FAST_MEMORY
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/* RAM0 size in bytes */
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#define STORM_INTMEM_SIZE_E1 0x5800
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#define STORM_INTMEM_SIZE_E1H 0x10000
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#define STORM_INTMEM_SIZE(bp) ((CHIP_IS_E1H(bp) ? STORM_INTMEM_SIZE_E1H : \
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STORM_INTMEM_SIZE_E1) / 4)
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/* Init operation types and structures */
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/* Common for both E1 and E1H */
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#define OP_RD 0x1 /* read single register */
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#define OP_WR 0x2 /* write single register */
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#define OP_IW 0x3 /* write single register using mailbox */
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#define OP_SW 0x4 /* copy a string to the device */
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#define OP_SI 0x5 /* copy a string using mailbox */
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#define OP_ZR 0x6 /* clear memory */
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#define OP_ZP 0x7 /* unzip then copy with DMAE */
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#define OP_WR_64 0x8 /* write 64 bit pattern */
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#define OP_WB 0x9 /* copy a string using DMAE */
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/* FPGA and EMUL specific operations */
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#define OP_WR_EMUL 0xa /* write single register on Emulation */
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#define OP_WR_FPGA 0xb /* write single register on FPGA */
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#define OP_WR_ASIC 0xc /* write single register on ASIC */
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/* Init stages */
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#define COMMON_STAGE 0
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#define PORT0_STAGE 1
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#define PORT1_STAGE 2
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/* Never reorder FUNCx stages !!! */
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#define FUNC0_STAGE 3
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#define FUNC1_STAGE 4
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#define FUNC2_STAGE 5
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#define FUNC3_STAGE 6
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#define FUNC4_STAGE 7
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#define FUNC5_STAGE 8
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#define FUNC6_STAGE 9
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#define FUNC7_STAGE 10
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#define STAGE_IDX_MAX 11
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#define STAGE_START 0
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#define STAGE_END 1
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/* Indices of blocks */
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#define PRS_BLOCK 0
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#define SRCH_BLOCK 1
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#define TSDM_BLOCK 2
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#define TCM_BLOCK 3
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#define BRB1_BLOCK 4
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#define TSEM_BLOCK 5
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#define PXPCS_BLOCK 6
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#define EMAC0_BLOCK 7
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#define EMAC1_BLOCK 8
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#define DBU_BLOCK 9
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#define MISC_BLOCK 10
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#define DBG_BLOCK 11
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#define NIG_BLOCK 12
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#define MCP_BLOCK 13
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#define UPB_BLOCK 14
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#define CSDM_BLOCK 15
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#define USDM_BLOCK 16
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#define CCM_BLOCK 17
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#define UCM_BLOCK 18
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#define USEM_BLOCK 19
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#define CSEM_BLOCK 20
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#define XPB_BLOCK 21
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#define DQ_BLOCK 22
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#define TIMERS_BLOCK 23
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#define XSDM_BLOCK 24
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#define QM_BLOCK 25
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#define PBF_BLOCK 26
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#define XCM_BLOCK 27
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#define XSEM_BLOCK 28
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#define CDU_BLOCK 29
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#define DMAE_BLOCK 30
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#define PXP_BLOCK 31
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#define CFC_BLOCK 32
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#define HC_BLOCK 33
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#define PXP2_BLOCK 34
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#define MISC_AEU_BLOCK 35
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/* Returns the index of start or end of a specific block stage in ops array*/
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#define BLOCK_OPS_IDX(block, stage, end) \
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(2*(((block)*STAGE_IDX_MAX) + (stage)) + (end))
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struct raw_op {
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u32 op:8;
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u32 offset:24;
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u32 raw_data;
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};
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struct op_read {
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u32 op:8;
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u32 offset:24;
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u32 pad;
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};
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struct op_write {
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u32 op:8;
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u32 offset:24;
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u32 val;
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};
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struct op_string_write {
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u32 op:8;
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u32 offset:24;
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#ifdef __LITTLE_ENDIAN
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u16 data_off;
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u16 data_len;
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#else /* __BIG_ENDIAN */
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u16 data_len;
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u16 data_off;
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#endif
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};
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struct op_zero {
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u32 op:8;
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u32 offset:24;
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u32 len;
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};
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union init_op {
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struct op_read read;
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struct op_write write;
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struct op_string_write str_wr;
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struct op_zero zero;
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struct raw_op raw;
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};
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/****************************************************************************
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* PXP
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****************************************************************************/
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/*
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* This code configures the PCI read/write arbiter
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* which implements a weighted round robin
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* between the virtual queues in the chip.
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*
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* The values were derived for each PCI max payload and max request size.
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* since max payload and max request size are only known at run time,
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* this is done as a separate init stage.
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*/
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#define NUM_WR_Q 13
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#define NUM_RD_Q 29
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#define MAX_RD_ORD 3
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#define MAX_WR_ORD 2
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/* configuration for one arbiter queue */
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struct arb_line {
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int l;
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int add;
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int ubound;
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};
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/* derived configuration for each read queue for each max request size */
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static const struct arb_line read_arb_data[NUM_RD_Q][MAX_RD_ORD + 1] = {
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/* 1 */ { {8, 64, 25}, {16, 64, 25}, {32, 64, 25}, {64, 64, 41} },
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{ {4, 8, 4}, {4, 8, 4}, {4, 8, 4}, {4, 8, 4} },
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{ {4, 3, 3}, {4, 3, 3}, {4, 3, 3}, {4, 3, 3} },
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{ {8, 3, 6}, {16, 3, 11}, {16, 3, 11}, {16, 3, 11} },
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{ {8, 64, 25}, {16, 64, 25}, {32, 64, 25}, {64, 64, 41} },
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{ {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {64, 3, 41} },
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{ {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {64, 3, 41} },
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{ {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {64, 3, 41} },
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{ {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {64, 3, 41} },
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/* 10 */{ {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },
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{ {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },
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{ {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },
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{ {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },
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{ {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },
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{ {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },
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{ {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },
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{ {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },
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{ {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },
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{ {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },
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/* 20 */{ {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },
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{ {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },
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{ {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },
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{ {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },
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{ {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },
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{ {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },
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{ {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },
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{ {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },
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{ {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },
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{ {8, 64, 25}, {16, 64, 41}, {32, 64, 81}, {64, 64, 120} }
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};
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/* derived configuration for each write queue for each max request size */
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static const struct arb_line write_arb_data[NUM_WR_Q][MAX_WR_ORD + 1] = {
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/* 1 */ { {4, 6, 3}, {4, 6, 3}, {4, 6, 3} },
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{ {4, 2, 3}, {4, 2, 3}, {4, 2, 3} },
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{ {8, 2, 6}, {16, 2, 11}, {16, 2, 11} },
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{ {8, 2, 6}, {16, 2, 11}, {32, 2, 21} },
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{ {8, 2, 6}, {16, 2, 11}, {32, 2, 21} },
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{ {8, 2, 6}, {16, 2, 11}, {32, 2, 21} },
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{ {8, 64, 25}, {16, 64, 25}, {32, 64, 25} },
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{ {8, 2, 6}, {16, 2, 11}, {16, 2, 11} },
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{ {8, 2, 6}, {16, 2, 11}, {16, 2, 11} },
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/* 10 */{ {8, 9, 6}, {16, 9, 11}, {32, 9, 21} },
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{ {8, 47, 19}, {16, 47, 19}, {32, 47, 21} },
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{ {8, 9, 6}, {16, 9, 11}, {16, 9, 11} },
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{ {8, 64, 25}, {16, 64, 41}, {32, 64, 81} }
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};
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/* register addresses for read queues */
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static const struct arb_line read_arb_addr[NUM_RD_Q-1] = {
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/* 1 */ {PXP2_REG_RQ_BW_RD_L0, PXP2_REG_RQ_BW_RD_ADD0,
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PXP2_REG_RQ_BW_RD_UBOUND0},
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{PXP2_REG_PSWRQ_BW_L1, PXP2_REG_PSWRQ_BW_ADD1,
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PXP2_REG_PSWRQ_BW_UB1},
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{PXP2_REG_PSWRQ_BW_L2, PXP2_REG_PSWRQ_BW_ADD2,
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PXP2_REG_PSWRQ_BW_UB2},
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{PXP2_REG_PSWRQ_BW_L3, PXP2_REG_PSWRQ_BW_ADD3,
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PXP2_REG_PSWRQ_BW_UB3},
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{PXP2_REG_RQ_BW_RD_L4, PXP2_REG_RQ_BW_RD_ADD4,
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PXP2_REG_RQ_BW_RD_UBOUND4},
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{PXP2_REG_RQ_BW_RD_L5, PXP2_REG_RQ_BW_RD_ADD5,
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PXP2_REG_RQ_BW_RD_UBOUND5},
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{PXP2_REG_PSWRQ_BW_L6, PXP2_REG_PSWRQ_BW_ADD6,
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PXP2_REG_PSWRQ_BW_UB6},
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{PXP2_REG_PSWRQ_BW_L7, PXP2_REG_PSWRQ_BW_ADD7,
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PXP2_REG_PSWRQ_BW_UB7},
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{PXP2_REG_PSWRQ_BW_L8, PXP2_REG_PSWRQ_BW_ADD8,
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PXP2_REG_PSWRQ_BW_UB8},
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/* 10 */{PXP2_REG_PSWRQ_BW_L9, PXP2_REG_PSWRQ_BW_ADD9,
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PXP2_REG_PSWRQ_BW_UB9},
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{PXP2_REG_PSWRQ_BW_L10, PXP2_REG_PSWRQ_BW_ADD10,
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PXP2_REG_PSWRQ_BW_UB10},
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{PXP2_REG_PSWRQ_BW_L11, PXP2_REG_PSWRQ_BW_ADD11,
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PXP2_REG_PSWRQ_BW_UB11},
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{PXP2_REG_RQ_BW_RD_L12, PXP2_REG_RQ_BW_RD_ADD12,
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PXP2_REG_RQ_BW_RD_UBOUND12},
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{PXP2_REG_RQ_BW_RD_L13, PXP2_REG_RQ_BW_RD_ADD13,
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PXP2_REG_RQ_BW_RD_UBOUND13},
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{PXP2_REG_RQ_BW_RD_L14, PXP2_REG_RQ_BW_RD_ADD14,
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PXP2_REG_RQ_BW_RD_UBOUND14},
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{PXP2_REG_RQ_BW_RD_L15, PXP2_REG_RQ_BW_RD_ADD15,
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PXP2_REG_RQ_BW_RD_UBOUND15},
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{PXP2_REG_RQ_BW_RD_L16, PXP2_REG_RQ_BW_RD_ADD16,
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PXP2_REG_RQ_BW_RD_UBOUND16},
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{PXP2_REG_RQ_BW_RD_L17, PXP2_REG_RQ_BW_RD_ADD17,
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PXP2_REG_RQ_BW_RD_UBOUND17},
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{PXP2_REG_RQ_BW_RD_L18, PXP2_REG_RQ_BW_RD_ADD18,
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PXP2_REG_RQ_BW_RD_UBOUND18},
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/* 20 */{PXP2_REG_RQ_BW_RD_L19, PXP2_REG_RQ_BW_RD_ADD19,
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PXP2_REG_RQ_BW_RD_UBOUND19},
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{PXP2_REG_RQ_BW_RD_L20, PXP2_REG_RQ_BW_RD_ADD20,
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PXP2_REG_RQ_BW_RD_UBOUND20},
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{PXP2_REG_RQ_BW_RD_L22, PXP2_REG_RQ_BW_RD_ADD22,
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PXP2_REG_RQ_BW_RD_UBOUND22},
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{PXP2_REG_RQ_BW_RD_L23, PXP2_REG_RQ_BW_RD_ADD23,
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PXP2_REG_RQ_BW_RD_UBOUND23},
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{PXP2_REG_RQ_BW_RD_L24, PXP2_REG_RQ_BW_RD_ADD24,
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PXP2_REG_RQ_BW_RD_UBOUND24},
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{PXP2_REG_RQ_BW_RD_L25, PXP2_REG_RQ_BW_RD_ADD25,
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PXP2_REG_RQ_BW_RD_UBOUND25},
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{PXP2_REG_RQ_BW_RD_L26, PXP2_REG_RQ_BW_RD_ADD26,
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PXP2_REG_RQ_BW_RD_UBOUND26},
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{PXP2_REG_RQ_BW_RD_L27, PXP2_REG_RQ_BW_RD_ADD27,
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PXP2_REG_RQ_BW_RD_UBOUND27},
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{PXP2_REG_PSWRQ_BW_L28, PXP2_REG_PSWRQ_BW_ADD28,
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PXP2_REG_PSWRQ_BW_UB28}
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};
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/* register addresses for write queues */
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static const struct arb_line write_arb_addr[NUM_WR_Q-1] = {
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/* 1 */ {PXP2_REG_PSWRQ_BW_L1, PXP2_REG_PSWRQ_BW_ADD1,
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PXP2_REG_PSWRQ_BW_UB1},
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{PXP2_REG_PSWRQ_BW_L2, PXP2_REG_PSWRQ_BW_ADD2,
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PXP2_REG_PSWRQ_BW_UB2},
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{PXP2_REG_PSWRQ_BW_L3, PXP2_REG_PSWRQ_BW_ADD3,
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PXP2_REG_PSWRQ_BW_UB3},
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{PXP2_REG_PSWRQ_BW_L6, PXP2_REG_PSWRQ_BW_ADD6,
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PXP2_REG_PSWRQ_BW_UB6},
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{PXP2_REG_PSWRQ_BW_L7, PXP2_REG_PSWRQ_BW_ADD7,
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PXP2_REG_PSWRQ_BW_UB7},
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{PXP2_REG_PSWRQ_BW_L8, PXP2_REG_PSWRQ_BW_ADD8,
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PXP2_REG_PSWRQ_BW_UB8},
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{PXP2_REG_PSWRQ_BW_L9, PXP2_REG_PSWRQ_BW_ADD9,
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PXP2_REG_PSWRQ_BW_UB9},
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{PXP2_REG_PSWRQ_BW_L10, PXP2_REG_PSWRQ_BW_ADD10,
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PXP2_REG_PSWRQ_BW_UB10},
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{PXP2_REG_PSWRQ_BW_L11, PXP2_REG_PSWRQ_BW_ADD11,
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PXP2_REG_PSWRQ_BW_UB11},
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/* 10 */{PXP2_REG_PSWRQ_BW_L28, PXP2_REG_PSWRQ_BW_ADD28,
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PXP2_REG_PSWRQ_BW_UB28},
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{PXP2_REG_RQ_BW_WR_L29, PXP2_REG_RQ_BW_WR_ADD29,
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PXP2_REG_RQ_BW_WR_UBOUND29},
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{PXP2_REG_RQ_BW_WR_L30, PXP2_REG_RQ_BW_WR_ADD30,
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PXP2_REG_RQ_BW_WR_UBOUND30}
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};
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/****************************************************************************
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* CDU
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****************************************************************************/
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#define CDU_REGION_NUMBER_XCM_AG 2
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#define CDU_REGION_NUMBER_UCM_AG 4
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/**
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* String-to-compress [31:8] = CID (all 24 bits)
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* String-to-compress [7:4] = Region
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* String-to-compress [3:0] = Type
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*/
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#define CDU_VALID_DATA(_cid, _region, _type) \
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(((_cid) << 8) | (((_region) & 0xf) << 4) | (((_type) & 0xf)))
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#define CDU_CRC8(_cid, _region, _type) \
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calc_crc8(CDU_VALID_DATA(_cid, _region, _type), 0xff)
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#define CDU_RSRVD_VALUE_TYPE_A(_cid, _region, _type) \
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(0x80 | (CDU_CRC8(_cid, _region, _type) & 0x7f))
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#define CDU_RSRVD_VALUE_TYPE_B(_crc, _type) \
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(0x80 | ((_type) & 0xf << 3) | (CDU_CRC8(_cid, _region, _type) & 0x7))
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#define CDU_RSRVD_INVALIDATE_CONTEXT_VALUE(_val) ((_val) & ~0x80)
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/* registers addresses are not in order
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so these arrays help simplify the code */
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static const int cm_blocks[9] = {
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MISC_BLOCK, TCM_BLOCK, UCM_BLOCK, CCM_BLOCK, XCM_BLOCK,
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TSEM_BLOCK, USEM_BLOCK, CSEM_BLOCK, XSEM_BLOCK
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};
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#endif /* BNX2X_INIT_H */
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