229 строки
7.8 KiB
C
229 строки
7.8 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* OMAP54XX SCRM registers and bitfields
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*
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* Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com
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*
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* Benoit Cousson (b-cousson@ti.com)
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*
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* This file is automatically generated from the OMAP hardware databases.
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* We respectfully ask that any modifications to this file be coordinated
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* with the public linux-omap@vger.kernel.org mailing list and the
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* authors above to ensure that the autogeneration scripts are kept
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* up-to-date with the file contents.
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*/
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#ifndef __ARCH_ARM_MACH_OMAP2_SCRM_54XX_H
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#define __ARCH_ARM_MACH_OMAP2_SCRM_54XX_H
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#define OMAP5_SCRM_BASE 0x4ae0a000
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#define OMAP54XX_SCRM_REGADDR(reg) \
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OMAP2_L4_IO_ADDRESS(OMAP5_SCRM_BASE + (reg))
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/* SCRM */
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/* SCRM.SCRM register offsets */
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#define OMAP5_SCRM_REVISION_SCRM_OFFSET 0x0000
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#define OMAP5_SCRM_REVISION_SCRM OMAP54XX_SCRM_REGADDR(0x0000)
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#define OMAP5_SCRM_CLKSETUPTIME_OFFSET 0x0100
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#define OMAP5_SCRM_CLKSETUPTIME OMAP54XX_SCRM_REGADDR(0x0100)
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#define OMAP5_SCRM_PMICSETUPTIME_OFFSET 0x0104
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#define OMAP5_SCRM_PMICSETUPTIME OMAP54XX_SCRM_REGADDR(0x0104)
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#define OMAP5_SCRM_ALTCLKSRC_OFFSET 0x0110
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#define OMAP5_SCRM_ALTCLKSRC OMAP54XX_SCRM_REGADDR(0x0110)
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#define OMAP5_SCRM_MODEMCLKM_OFFSET 0x0118
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#define OMAP5_SCRM_MODEMCLKM OMAP54XX_SCRM_REGADDR(0x0118)
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#define OMAP5_SCRM_D2DCLKM_OFFSET 0x011c
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#define OMAP5_SCRM_D2DCLKM OMAP54XX_SCRM_REGADDR(0x011c)
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#define OMAP5_SCRM_EXTCLKREQ_OFFSET 0x0200
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#define OMAP5_SCRM_EXTCLKREQ OMAP54XX_SCRM_REGADDR(0x0200)
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#define OMAP5_SCRM_ACCCLKREQ_OFFSET 0x0204
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#define OMAP5_SCRM_ACCCLKREQ OMAP54XX_SCRM_REGADDR(0x0204)
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#define OMAP5_SCRM_PWRREQ_OFFSET 0x0208
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#define OMAP5_SCRM_PWRREQ OMAP54XX_SCRM_REGADDR(0x0208)
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#define OMAP5_SCRM_AUXCLKREQ0_OFFSET 0x0210
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#define OMAP5_SCRM_AUXCLKREQ0 OMAP54XX_SCRM_REGADDR(0x0210)
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#define OMAP5_SCRM_AUXCLKREQ1_OFFSET 0x0214
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#define OMAP5_SCRM_AUXCLKREQ1 OMAP54XX_SCRM_REGADDR(0x0214)
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#define OMAP5_SCRM_AUXCLKREQ2_OFFSET 0x0218
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#define OMAP5_SCRM_AUXCLKREQ2 OMAP54XX_SCRM_REGADDR(0x0218)
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#define OMAP5_SCRM_AUXCLKREQ3_OFFSET 0x021c
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#define OMAP5_SCRM_AUXCLKREQ3 OMAP54XX_SCRM_REGADDR(0x021c)
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#define OMAP5_SCRM_AUXCLKREQ4_OFFSET 0x0220
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#define OMAP5_SCRM_AUXCLKREQ4 OMAP54XX_SCRM_REGADDR(0x0220)
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#define OMAP5_SCRM_AUXCLKREQ5_OFFSET 0x0224
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#define OMAP5_SCRM_AUXCLKREQ5 OMAP54XX_SCRM_REGADDR(0x0224)
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#define OMAP5_SCRM_D2DCLKREQ_OFFSET 0x0234
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#define OMAP5_SCRM_D2DCLKREQ OMAP54XX_SCRM_REGADDR(0x0234)
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#define OMAP5_SCRM_AUXCLK0_OFFSET 0x0310
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#define OMAP5_SCRM_AUXCLK0 OMAP54XX_SCRM_REGADDR(0x0310)
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#define OMAP5_SCRM_AUXCLK1_OFFSET 0x0314
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#define OMAP5_SCRM_AUXCLK1 OMAP54XX_SCRM_REGADDR(0x0314)
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#define OMAP5_SCRM_AUXCLK2_OFFSET 0x0318
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#define OMAP5_SCRM_AUXCLK2 OMAP54XX_SCRM_REGADDR(0x0318)
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#define OMAP5_SCRM_AUXCLK3_OFFSET 0x031c
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#define OMAP5_SCRM_AUXCLK3 OMAP54XX_SCRM_REGADDR(0x031c)
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#define OMAP5_SCRM_AUXCLK4_OFFSET 0x0320
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#define OMAP5_SCRM_AUXCLK4 OMAP54XX_SCRM_REGADDR(0x0320)
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#define OMAP5_SCRM_AUXCLK5_OFFSET 0x0324
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#define OMAP5_SCRM_AUXCLK5 OMAP54XX_SCRM_REGADDR(0x0324)
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#define OMAP5_SCRM_RSTTIME_OFFSET 0x0400
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#define OMAP5_SCRM_RSTTIME OMAP54XX_SCRM_REGADDR(0x0400)
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#define OMAP5_SCRM_MODEMRSTCTRL_OFFSET 0x0418
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#define OMAP5_SCRM_MODEMRSTCTRL OMAP54XX_SCRM_REGADDR(0x0418)
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#define OMAP5_SCRM_D2DRSTCTRL_OFFSET 0x041c
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#define OMAP5_SCRM_D2DRSTCTRL OMAP54XX_SCRM_REGADDR(0x041c)
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#define OMAP5_SCRM_EXTPWRONRSTCTRL_OFFSET 0x0420
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#define OMAP5_SCRM_EXTPWRONRSTCTRL OMAP54XX_SCRM_REGADDR(0x0420)
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#define OMAP5_SCRM_EXTWARMRSTST_OFFSET 0x0510
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#define OMAP5_SCRM_EXTWARMRSTST OMAP54XX_SCRM_REGADDR(0x0510)
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#define OMAP5_SCRM_APEWARMRSTST_OFFSET 0x0514
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#define OMAP5_SCRM_APEWARMRSTST OMAP54XX_SCRM_REGADDR(0x0514)
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#define OMAP5_SCRM_MODEMWARMRSTST_OFFSET 0x0518
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#define OMAP5_SCRM_MODEMWARMRSTST OMAP54XX_SCRM_REGADDR(0x0518)
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#define OMAP5_SCRM_D2DWARMRSTST_OFFSET 0x051c
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#define OMAP5_SCRM_D2DWARMRSTST OMAP54XX_SCRM_REGADDR(0x051c)
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/*
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* Used by AUXCLKREQ0, AUXCLKREQ1, AUXCLKREQ2, AUXCLKREQ3, AUXCLKREQ4,
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* AUXCLKREQ5, D2DCLKREQ
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*/
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#define OMAP5_ACCURACY_SHIFT 1
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#define OMAP5_ACCURACY_WIDTH 0x1
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#define OMAP5_ACCURACY_MASK (1 << 1)
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/* Used by APEWARMRSTST */
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#define OMAP5_APEWARMRSTST_SHIFT 1
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#define OMAP5_APEWARMRSTST_WIDTH 0x1
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#define OMAP5_APEWARMRSTST_MASK (1 << 1)
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/* Used by AUXCLK0, AUXCLK1, AUXCLK2, AUXCLK3, AUXCLK4, AUXCLK5 */
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#define OMAP5_CLKDIV_SHIFT 16
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#define OMAP5_CLKDIV_WIDTH 0x4
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#define OMAP5_CLKDIV_MASK (0xf << 16)
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/* Used by D2DCLKM, MODEMCLKM */
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#define OMAP5_CLK_32KHZ_SHIFT 0
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#define OMAP5_CLK_32KHZ_WIDTH 0x1
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#define OMAP5_CLK_32KHZ_MASK (1 << 0)
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/* Used by D2DRSTCTRL, MODEMRSTCTRL */
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#define OMAP5_COLDRST_SHIFT 0
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#define OMAP5_COLDRST_WIDTH 0x1
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#define OMAP5_COLDRST_MASK (1 << 0)
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/* Used by D2DWARMRSTST */
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#define OMAP5_D2DWARMRSTST_SHIFT 3
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#define OMAP5_D2DWARMRSTST_WIDTH 0x1
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#define OMAP5_D2DWARMRSTST_MASK (1 << 3)
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/* Used by AUXCLK0 */
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#define OMAP5_DISABLECLK_SHIFT 9
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#define OMAP5_DISABLECLK_WIDTH 0x1
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#define OMAP5_DISABLECLK_MASK (1 << 9)
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/* Used by CLKSETUPTIME */
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#define OMAP5_DOWNTIME_SHIFT 16
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#define OMAP5_DOWNTIME_WIDTH 0x6
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#define OMAP5_DOWNTIME_MASK (0x3f << 16)
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/* Used by AUXCLK0, AUXCLK1, AUXCLK2, AUXCLK3, AUXCLK4, AUXCLK5 */
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#define OMAP5_ENABLE_SHIFT 8
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#define OMAP5_ENABLE_WIDTH 0x1
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#define OMAP5_ENABLE_MASK (1 << 8)
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/* Renamed from ENABLE Used by EXTPWRONRSTCTRL */
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#define OMAP5_ENABLE_0_0_SHIFT 0
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#define OMAP5_ENABLE_0_0_WIDTH 0x1
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#define OMAP5_ENABLE_0_0_MASK (1 << 0)
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/* Used by ALTCLKSRC */
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#define OMAP5_ENABLE_EXT_SHIFT 3
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#define OMAP5_ENABLE_EXT_WIDTH 0x1
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#define OMAP5_ENABLE_EXT_MASK (1 << 3)
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/* Used by ALTCLKSRC */
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#define OMAP5_ENABLE_INT_SHIFT 2
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#define OMAP5_ENABLE_INT_WIDTH 0x1
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#define OMAP5_ENABLE_INT_MASK (1 << 2)
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/* Used by EXTWARMRSTST */
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#define OMAP5_EXTWARMRSTST_SHIFT 0
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#define OMAP5_EXTWARMRSTST_WIDTH 0x1
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#define OMAP5_EXTWARMRSTST_MASK (1 << 0)
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/*
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* Used by AUXCLKREQ0, AUXCLKREQ1, AUXCLKREQ2, AUXCLKREQ3, AUXCLKREQ4,
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* AUXCLKREQ5
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*/
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#define OMAP5_MAPPING_SHIFT 2
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#define OMAP5_MAPPING_WIDTH 0x3
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#define OMAP5_MAPPING_MASK (0x7 << 2)
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/* Used by ALTCLKSRC */
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#define OMAP5_MODE_SHIFT 0
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#define OMAP5_MODE_WIDTH 0x2
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#define OMAP5_MODE_MASK (0x3 << 0)
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/* Used by MODEMWARMRSTST */
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#define OMAP5_MODEMWARMRSTST_SHIFT 2
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#define OMAP5_MODEMWARMRSTST_WIDTH 0x1
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#define OMAP5_MODEMWARMRSTST_MASK (1 << 2)
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/*
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* Used by ACCCLKREQ, AUXCLK0, AUXCLK1, AUXCLK2, AUXCLK3, AUXCLK4, AUXCLK5,
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* AUXCLKREQ0, AUXCLKREQ1, AUXCLKREQ2, AUXCLKREQ3, AUXCLKREQ4, AUXCLKREQ5,
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* D2DCLKREQ, EXTCLKREQ, PWRREQ
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*/
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#define OMAP5_POLARITY_SHIFT 0
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#define OMAP5_POLARITY_WIDTH 0x1
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#define OMAP5_POLARITY_MASK (1 << 0)
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/* Used by EXTPWRONRSTCTRL */
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#define OMAP5_PWRONRST_SHIFT 1
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#define OMAP5_PWRONRST_WIDTH 0x1
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#define OMAP5_PWRONRST_MASK (1 << 1)
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/* Used by REVISION_SCRM */
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#define OMAP5_REV_SHIFT 0
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#define OMAP5_REV_WIDTH 0x8
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#define OMAP5_REV_MASK (0xff << 0)
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/* Used by RSTTIME */
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#define OMAP5_RSTTIME_SHIFT 0
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#define OMAP5_RSTTIME_WIDTH 0x4
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#define OMAP5_RSTTIME_MASK (0xf << 0)
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/* Used by CLKSETUPTIME */
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#define OMAP5_SETUPTIME_SHIFT 0
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#define OMAP5_SETUPTIME_WIDTH 0xc
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#define OMAP5_SETUPTIME_MASK (0xfff << 0)
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/* Used by PMICSETUPTIME */
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#define OMAP5_SLEEPTIME_SHIFT 0
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#define OMAP5_SLEEPTIME_WIDTH 0x6
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#define OMAP5_SLEEPTIME_MASK (0x3f << 0)
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/* Used by AUXCLK0, AUXCLK1, AUXCLK2, AUXCLK3, AUXCLK4, AUXCLK5 */
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#define OMAP5_SRCSELECT_SHIFT 1
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#define OMAP5_SRCSELECT_WIDTH 0x2
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#define OMAP5_SRCSELECT_MASK (0x3 << 1)
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/* Used by D2DCLKM */
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#define OMAP5_SYSCLK_SHIFT 1
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#define OMAP5_SYSCLK_WIDTH 0x1
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#define OMAP5_SYSCLK_MASK (1 << 1)
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/* Used by PMICSETUPTIME */
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#define OMAP5_WAKEUPTIME_SHIFT 16
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#define OMAP5_WAKEUPTIME_WIDTH 0x6
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#define OMAP5_WAKEUPTIME_MASK (0x3f << 16)
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/* Used by D2DRSTCTRL, MODEMRSTCTRL */
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#define OMAP5_WARMRST_SHIFT 1
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#define OMAP5_WARMRST_WIDTH 0x1
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#define OMAP5_WARMRST_MASK (1 << 1)
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#endif
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