microsoft
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WSL2-Linux-Kernel
зеркало из https://github.com/microsoft/WSL2-Linux-Kernel.git
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WSL2-Linux-Kernel/drivers/clk
История
Geert Uytterhoeven ceabbf94c3 clk: renesas: r9a06g032: Drop __packed for portability 
The R9A06G032 clock driver uses an array of packed structures to reduce
kernel size.  However, this array contains pointers, which are no longer
aligned naturally, and cannot be relocated on PPC64.  Hence when
compile-testing this driver on PPC64 with CONFIG_RELOCATABLE=y (e.g.
PowerPC allyesconfig), the following warnings are produced:

    WARNING: 136 bad relocations
    c000000000616be3 R_PPC64_UADDR64   .rodata+0x00000000000cf338
    c000000000616bfe R_PPC64_UADDR64   .rodata+0x00000000000cf370
    ...

Fix this by dropping the __packed attribute from the r9a06g032_clkdesc
definition, trading a small size increase for portability.

This increases the 156-entry clock table by 1 byte per entry, but due to
the compiler generating more efficient code for unpacked accesses, the
net size increase is only 76 bytes (gcc 9.3.0 on arm32).

Reported-by: Stephen Rothwell <sfr@canb.auug.org.au>
Fixes: 4c3d88526e ("clk: renesas: Renesas R9A06G032 clock driver")
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20201130085743.1656317-1-geert+renesas@glider.be
Tested-by: Stephen Rothwell <sfr@canb.auug.org.au> # PowerPC allyesconfig build
Acked-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
 		2020-12-07 13:58:49 -08:00
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actions clk: actions: Add Actions S500 SoC Reset Management Unit support 2020-07-21 01:50:47 -07:00
analogbits
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at91 Merge branches 'clk-ingenic', 'clk-at91', 'clk-kconfig', 'clk-imx', 'clk-qcom', 'clk-prima2' and 'clk-bcm' into clk-next 2020-10-20 11:47:07 -07:00
axis
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axs10x
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baikal-t1 clk: baikal-t1: Mark Ethernet PLL as critical 2020-10-13 19:48:34 -07:00
bcm This pull request contains zero diff to the core framework. It is a collection 2020-10-22 12:53:28 -07:00
berlin
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davinci This pull request contains zero diff to the core framework. It is a collection 2020-10-22 12:53:28 -07:00
h8300
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hisilicon
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imgtec treewide: replace '---help---' in Kconfig files with 'help' 2020-06-14 01:57:21 +09:00
imx clk: imx: scu: fix MXC_CLK_SCU module build break 2020-12-07 13:54:00 -08:00
ingenic clk: ingenic: Respect CLK_SET_RATE_PARENT in .round_rate 2020-10-13 20:04:50 -07:00
keystone clk: keystone: sci-clk: add 10% slack to set_rate 2020-09-22 12:58:52 -07:00
loongson1
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mediatek Merge branches 'clk-simplify', 'clk-ti', 'clk-tegra', 'clk-rockchip' and 'clk-mediatek' into clk-next 2020-10-20 11:46:47 -07:00
meson clk: define to_clk_regmap() as inline function 2020-10-28 16:34:44 -07:00
microchip
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mmp Merge branches 'clk-semicolon', 'clk-axi-clkgen', 'clk-qoriq', 'clk-baikal', 'clk-const' and 'clk-mmp2' into clk-next 2020-10-20 11:47:02 -07:00
mvebu clk: mvebu: ap80x-cpu: use semicolons rather than commas to separate statements 2020-10-13 17:43:05 -07:00
mxs
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nxp
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pistachio
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pxa clk: pxa: Constify static struct clk_ops 2020-10-13 19:49:11 -07:00
qcom clk: define to_clk_regmap() as inline function 2020-10-28 16:34:44 -07:00
renesas clk: renesas: r9a06g032: Drop __packed for portability 2020-12-07 13:58:49 -08:00
rockchip This pull request contains zero diff to the core framework. It is a collection 2020-10-22 12:53:28 -07:00
samsung ARM: SoC platform updates 2020-10-24 10:33:08 -07:00
sifive clk: sifive: allocate sufficient memory for struct __prci_data 2020-06-25 15:04:13 -07:00
sirf clk: clk-prima2: fix return value check in prima2_clk_init() 2020-10-13 19:54:30 -07:00
socfpga This pull request contains zero diff to the core framework. It is a collection 2020-10-22 12:53:28 -07:00
spear clk: spear: Remove uninitialized_var() usage 2020-07-16 12:32:26 -07:00
sprd This time around we have 4 lines of diff in the core framework, removing a 2020-06-10 11:42:19 -07:00
st clk: st: Remove uninitialized_var() usage 2020-07-16 12:32:25 -07:00
sunxi clk: sunxi: Fix incorrect usage of round_down() 2020-04-14 09:21:05 +02:00
sunxi-ng clk: sunxi-ng: sun8i: r40: Use sigma delta modulation for audio PLL 2020-08-25 16:42:55 +02:00
tegra This pull request contains zero diff to the core framework. It is a collection 2020-10-22 12:53:28 -07:00
ti clk: ti: dra7: add missing clkctrl register for SHA2 instance 2020-09-22 13:00:07 -07:00
uniphier clk: uniphier: use semicolons rather than commas to separate statements 2020-10-13 17:43:03 -07:00
ux500 clk: ux500: Fix up the SGA clock for some variants 2020-01-04 23:27:15 -08:00
versatile clk: versatile: Add of_node_put() before return statement 2020-09-10 00:57:42 -07:00
x86 More ACPI updates for 5.9-rc1 2020-08-15 08:18:22 -07:00
zte
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zynq
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zynqmp This time around we have 4 lines of diff in the core framework, removing a 2020-06-10 11:42:19 -07:00
Kconfig Merge branches 'clk-ingenic', 'clk-at91', 'clk-kconfig', 'clk-imx', 'clk-qcom', 'clk-prima2' and 'clk-bcm' into clk-next 2020-10-20 11:47:07 -07:00
Makefile clk: sparx5: Add Sparx5 SoC DPLL clock driver 2020-07-28 18:17:56 -07:00
clk-asm9260.c clk: asm9260: fix __clk_hw_register_fixed_rate_with_accuracy typo 2020-04-13 12:20:06 -07:00
clk-aspeed.c
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clk-aspeed.h
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clk-ast2600.c clk: AST2600: Add mux for EMMC clock 2020-07-11 09:15:33 -07:00
clk-axi-clkgen.c clk: axi-clkgen: Set power bits for fractional mode 2020-10-13 19:44:40 -07:00
clk-axm5516.c
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clk-bd718x7.c clk: bd718x7: Support ROHM BD71828 clk block 2020-01-24 07:22:47 +00:00
clk-bm1880.c
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clk-bulk.c
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clk-cdce706.c Replace HTTP links with HTTPS ones: Common CLK framework 2020-07-10 17:15:34 -07:00
clk-cdce925.c
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clk-clps711x.c
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clk-composite.c clk: composite: Export clk_hw_register_composite() 2020-08-22 12:38:06 +08:00
clk-conf.c
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clk-cs2000-cp.c
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clk-devres.c
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clk-divider.c clk: divider: Add support for specifying parents via DT/pointers 2020-01-07 23:08:02 -08:00
clk-efm32gg.c
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clk-fixed-factor.c clk: fixed: add missing kerneldoc 2020-09-22 12:44:14 -07:00
clk-fixed-mmio.c
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clk-fixed-rate.c clk: fixed: add missing kerneldoc 2020-09-22 12:44:14 -07:00
clk-fractional-divider.c
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clk-fsl-sai.c clk: fsl-sai: new driver 2020-01-28 13:26:48 -08:00
clk-gate.c treewide: Remove uninitialized_var() usage 2020-07-16 12:35:15 -07:00
clk-gemini.c
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clk-gpio.c Replace HTTP links with HTTPS ones: Common CLK framework 2020-07-10 17:15:34 -07:00
clk-hi655x.c
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clk-highbank.c
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clk-hsdk-pll.c CLK: HSDK: CGU: add support for 148.5MHz clock 2020-05-28 21:06:39 -07:00
clk-lochnagar.c
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clk-max9485.c
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clk-max77686.c
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clk-milbeaut.c
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clk-moxart.c
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clk-multiplier.c
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clk-mux.c clk: mux: Add support for specifying parents via DT/pointers 2020-01-06 23:10:05 -08:00
clk-nomadik.c
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clk-npcm7xx.c
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clk-nspire.c
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clk-oxnas.c
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clk-palmas.c
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clk-plldig.c clk: ls1028a: fix a dereference of pointer 'parent' before a null check 2020-02-03 23:03:49 -08:00
clk-pwm.c clk: pwm: Use 64-bit division function 2020-06-17 20:42:10 +02:00
clk-qoriq.c clk: qoriq: modify MAX_PLL_DIV to 32 2020-10-13 19:48:09 -07:00
clk-rk808.c
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clk-s2mps11.c clk: s2mps11: initialize driver via module_platform_driver 2020-09-22 12:30:52 -07:00
clk-scmi.c clk: scmi: Fix min and max rate when registering clocks with discrete rates 2020-07-13 09:40:21 +01:00
clk-scpi.c
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clk-si514.c
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clk-si544.c
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clk-si570.c
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clk-si5341.c clk: si5341: drop unused 'err' variable 2020-09-22 12:44:41 -07:00
clk-si5351.c Replace HTTP links with HTTPS ones: Common CLK framework 2020-07-10 17:15:34 -07:00
clk-si5351.h
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clk-sparx5.c clk: sparx5: Add Sparx5 SoC DPLL clock driver 2020-07-28 18:17:56 -07:00
clk-stm32f4.c
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clk-stm32h7.c
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clk-stm32mp1.c
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clk-tango4.c
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clk-twl6040.c
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clk-u300.c
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clk-versaclock5.c clk: vc5: use a dedicated struct to describe the output drivers 2020-07-23 15:34:21 -07:00
clk-vt8500.c
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clk-wm831x.c
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clk-xgene.c
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clk.c treewide: Convert macro and uses of __section(foo) to __section("foo") 2020-10-25 14:51:49 -07:00
clk.h
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clkdev.c
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