872 строки
23 KiB
C
872 строки
23 KiB
C
/*
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* linux/drivers/ide/setup-pci.c Version 1.10 2002/08/19
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*
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* Copyright (c) 1998-2000 Andre Hedrick <andre@linux-ide.org>
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*
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* Copyright (c) 1995-1998 Mark Lord
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* May be copied or modified under the terms of the GNU General Public License
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*/
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/*
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* This module provides support for automatic detection and
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* configuration of all PCI IDE interfaces present in a system.
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*/
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#include <linux/module.h>
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#include <linux/types.h>
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#include <linux/kernel.h>
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#include <linux/pci.h>
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#include <linux/init.h>
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#include <linux/timer.h>
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#include <linux/mm.h>
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#include <linux/interrupt.h>
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#include <linux/ide.h>
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#include <linux/dma-mapping.h>
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#include <asm/io.h>
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#include <asm/irq.h>
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/**
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* ide_match_hwif - match a PCI IDE against an ide_hwif
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* @io_base: I/O base of device
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* @bootable: set if its bootable
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* @name: name of device
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*
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* Match a PCI IDE port against an entry in ide_hwifs[],
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* based on io_base port if possible. Return the matching hwif,
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* or a new hwif. If we find an error (clashing, out of devices, etc)
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* return NULL
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*
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* FIXME: we need to handle mmio matches here too
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*/
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static ide_hwif_t *ide_match_hwif(unsigned long io_base, u8 bootable, const char *name)
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{
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int h;
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ide_hwif_t *hwif;
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/*
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* Look for a hwif with matching io_base specified using
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* parameters to ide_setup().
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*/
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for (h = 0; h < MAX_HWIFS; ++h) {
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hwif = &ide_hwifs[h];
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if (hwif->io_ports[IDE_DATA_OFFSET] == io_base) {
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if (hwif->chipset == ide_forced)
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return hwif; /* a perfect match */
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}
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}
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/*
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* Look for a hwif with matching io_base default value.
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* If chipset is "ide_unknown", then claim that hwif slot.
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* Otherwise, some other chipset has already claimed it.. :(
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*/
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for (h = 0; h < MAX_HWIFS; ++h) {
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hwif = &ide_hwifs[h];
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if (hwif->io_ports[IDE_DATA_OFFSET] == io_base) {
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if (hwif->chipset == ide_unknown)
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return hwif; /* match */
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printk(KERN_ERR "%s: port 0x%04lx already claimed by %s\n",
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name, io_base, hwif->name);
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return NULL; /* already claimed */
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}
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}
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/*
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* Okay, there is no hwif matching our io_base,
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* so we'll just claim an unassigned slot.
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* Give preference to claiming other slots before claiming ide0/ide1,
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* just in case there's another interface yet-to-be-scanned
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* which uses ports 1f0/170 (the ide0/ide1 defaults).
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*
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* Unless there is a bootable card that does not use the standard
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* ports 1f0/170 (the ide0/ide1 defaults). The (bootable) flag.
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*/
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if (bootable) {
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for (h = 0; h < MAX_HWIFS; ++h) {
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hwif = &ide_hwifs[h];
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if (hwif->chipset == ide_unknown)
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return hwif; /* pick an unused entry */
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}
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} else {
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for (h = 2; h < MAX_HWIFS; ++h) {
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hwif = ide_hwifs + h;
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if (hwif->chipset == ide_unknown)
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return hwif; /* pick an unused entry */
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}
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}
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for (h = 0; h < 2 && h < MAX_HWIFS; ++h) {
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hwif = ide_hwifs + h;
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if (hwif->chipset == ide_unknown)
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return hwif; /* pick an unused entry */
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}
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printk(KERN_ERR "%s: too many IDE interfaces, no room in table\n", name);
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return NULL;
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}
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/**
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* ide_setup_pci_baseregs - place a PCI IDE controller native
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* @dev: PCI device of interface to switch native
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* @name: Name of interface
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*
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* We attempt to place the PCI interface into PCI native mode. If
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* we succeed the BARs are ok and the controller is in PCI mode.
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* Returns 0 on success or an errno code.
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*
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* FIXME: if we program the interface and then fail to set the BARS
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* we don't switch it back to legacy mode. Do we actually care ??
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*/
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static int ide_setup_pci_baseregs (struct pci_dev *dev, const char *name)
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{
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u8 progif = 0;
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/*
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* Place both IDE interfaces into PCI "native" mode:
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*/
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if (pci_read_config_byte(dev, PCI_CLASS_PROG, &progif) ||
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(progif & 5) != 5) {
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if ((progif & 0xa) != 0xa) {
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printk(KERN_INFO "%s: device not capable of full "
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"native PCI mode\n", name);
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return -EOPNOTSUPP;
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}
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printk("%s: placing both ports into native PCI mode\n", name);
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(void) pci_write_config_byte(dev, PCI_CLASS_PROG, progif|5);
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if (pci_read_config_byte(dev, PCI_CLASS_PROG, &progif) ||
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(progif & 5) != 5) {
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printk(KERN_ERR "%s: rewrite of PROGIF failed, wanted "
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"0x%04x, got 0x%04x\n",
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name, progif|5, progif);
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return -EOPNOTSUPP;
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}
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}
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return 0;
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}
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#ifdef CONFIG_BLK_DEV_IDEDMA_PCI
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#ifdef CONFIG_BLK_DEV_IDEDMA_FORCED
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/*
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* Long lost data from 2.0.34 that is now in 2.0.39
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*
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* This was used in ./drivers/block/triton.c to do DMA Base address setup
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* when PnP failed. Oh the things we forget. I believe this was part
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* of SFF-8038i that has been withdrawn from public access... :-((
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*/
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#define DEFAULT_BMIBA 0xe800 /* in case BIOS did not init it */
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#define DEFAULT_BMCRBA 0xcc00 /* VIA's default value */
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#define DEFAULT_BMALIBA 0xd400 /* ALI's default value */
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#endif /* CONFIG_BLK_DEV_IDEDMA_FORCED */
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/**
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* ide_get_or_set_dma_base - setup BMIBA
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* @hwif: Interface
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*
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* Fetch the DMA Bus-Master-I/O-Base-Address (BMIBA) from PCI space:
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* If need be we set up the DMA base. Where a device has a partner that
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* is already in DMA mode we check and enforce IDE simplex rules.
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*/
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static unsigned long ide_get_or_set_dma_base (ide_hwif_t *hwif)
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{
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unsigned long dma_base = 0;
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struct pci_dev *dev = hwif->pci_dev;
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#ifdef CONFIG_BLK_DEV_IDEDMA_FORCED
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int second_chance = 0;
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second_chance_to_dma:
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#endif /* CONFIG_BLK_DEV_IDEDMA_FORCED */
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if (hwif->mmio)
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return hwif->dma_base;
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if (hwif->mate && hwif->mate->dma_base) {
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dma_base = hwif->mate->dma_base - (hwif->channel ? 0 : 8);
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} else {
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dma_base = pci_resource_start(dev, 4);
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if (!dma_base) {
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printk(KERN_ERR "%s: dma_base is invalid\n",
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hwif->cds->name);
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}
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}
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#ifdef CONFIG_BLK_DEV_IDEDMA_FORCED
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/* FIXME - should use pci_assign_resource surely */
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if ((!dma_base) && (!second_chance)) {
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unsigned long set_bmiba = 0;
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second_chance++;
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switch(dev->vendor) {
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case PCI_VENDOR_ID_AL:
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set_bmiba = DEFAULT_BMALIBA; break;
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case PCI_VENDOR_ID_VIA:
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set_bmiba = DEFAULT_BMCRBA; break;
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case PCI_VENDOR_ID_INTEL:
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set_bmiba = DEFAULT_BMIBA; break;
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default:
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return dma_base;
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}
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pci_write_config_dword(dev, 0x20, set_bmiba|1);
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goto second_chance_to_dma;
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}
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#endif /* CONFIG_BLK_DEV_IDEDMA_FORCED */
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if (dma_base) {
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u8 simplex_stat = 0;
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dma_base += hwif->channel ? 8 : 0;
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switch(dev->device) {
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case PCI_DEVICE_ID_AL_M5219:
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case PCI_DEVICE_ID_AL_M5229:
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case PCI_DEVICE_ID_AMD_VIPER_7409:
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case PCI_DEVICE_ID_CMD_643:
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case PCI_DEVICE_ID_SERVERWORKS_CSB5IDE:
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case PCI_DEVICE_ID_REVOLUTION:
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simplex_stat = hwif->INB(dma_base + 2);
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hwif->OUTB((simplex_stat&0x60),(dma_base + 2));
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simplex_stat = hwif->INB(dma_base + 2);
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if (simplex_stat & 0x80) {
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printk(KERN_INFO "%s: simplex device: "
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"DMA forced\n",
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hwif->cds->name);
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}
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break;
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default:
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/*
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* If the device claims "simplex" DMA,
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* this means only one of the two interfaces
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* can be trusted with DMA at any point in time.
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* So we should enable DMA only on one of the
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* two interfaces.
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*/
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simplex_stat = hwif->INB(dma_base + 2);
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if (simplex_stat & 0x80) {
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/* simplex device? */
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/*
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* At this point we haven't probed the drives so we can't make the
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* appropriate decision. Really we should defer this problem
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* until we tune the drive then try to grab DMA ownership if we want
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* to be the DMA end. This has to be become dynamic to handle hot
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* plug.
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*/
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if (hwif->mate && hwif->mate->dma_base) {
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printk(KERN_INFO "%s: simplex device: "
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"DMA disabled\n",
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hwif->cds->name);
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dma_base = 0;
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}
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}
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}
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}
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return dma_base;
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}
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#endif /* CONFIG_BLK_DEV_IDEDMA_PCI */
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void ide_setup_pci_noise (struct pci_dev *dev, ide_pci_device_t *d)
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{
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printk(KERN_INFO "%s: IDE controller at PCI slot %s\n",
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d->name, pci_name(dev));
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}
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EXPORT_SYMBOL_GPL(ide_setup_pci_noise);
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/**
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* ide_pci_enable - do PCI enables
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* @dev: PCI device
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* @d: IDE pci device data
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*
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* Enable the IDE PCI device. We attempt to enable the device in full
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* but if that fails then we only need BAR4 so we will enable that.
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*
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* Returns zero on success or an error code
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*/
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static int ide_pci_enable(struct pci_dev *dev, ide_pci_device_t *d)
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{
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int ret;
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if (pci_enable_device(dev)) {
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ret = pci_enable_device_bars(dev, 1 << 4);
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if (ret < 0) {
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printk(KERN_WARNING "%s: (ide_setup_pci_device:) "
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"Could not enable device.\n", d->name);
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goto out;
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}
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printk(KERN_WARNING "%s: BIOS configuration fixed.\n", d->name);
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}
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/*
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* assume all devices can do 32-bit dma for now. we can add a
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* dma mask field to the ide_pci_device_t if we need it (or let
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* lower level driver set the dma mask)
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*/
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ret = pci_set_dma_mask(dev, DMA_32BIT_MASK);
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if (ret < 0) {
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printk(KERN_ERR "%s: can't set dma mask\n", d->name);
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goto out;
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}
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/* FIXME: Temporary - until we put in the hotplug interface logic
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Check that the bits we want are not in use by someone else. */
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ret = pci_request_region(dev, 4, "ide_tmp");
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if (ret < 0)
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goto out;
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pci_release_region(dev, 4);
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out:
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return ret;
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}
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/**
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* ide_pci_configure - configure an unconfigured device
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* @dev: PCI device
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* @d: IDE pci device data
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*
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* Enable and configure the PCI device we have been passed.
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* Returns zero on success or an error code.
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*/
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static int ide_pci_configure(struct pci_dev *dev, ide_pci_device_t *d)
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{
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u16 pcicmd = 0;
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/*
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* PnP BIOS was *supposed* to have setup this device, but we
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* can do it ourselves, so long as the BIOS has assigned an IRQ
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* (or possibly the device is using a "legacy header" for IRQs).
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* Maybe the user deliberately *disabled* the device,
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* but we'll eventually ignore it again if no drives respond.
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*/
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if (ide_setup_pci_baseregs(dev, d->name) || pci_write_config_word(dev, PCI_COMMAND, pcicmd|PCI_COMMAND_IO))
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{
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printk(KERN_INFO "%s: device disabled (BIOS)\n", d->name);
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return -ENODEV;
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}
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if (pci_read_config_word(dev, PCI_COMMAND, &pcicmd)) {
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printk(KERN_ERR "%s: error accessing PCI regs\n", d->name);
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return -EIO;
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}
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if (!(pcicmd & PCI_COMMAND_IO)) {
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printk(KERN_ERR "%s: unable to enable IDE controller\n", d->name);
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return -ENXIO;
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}
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return 0;
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}
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/**
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* ide_pci_check_iomem - check a register is I/O
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* @dev: pci device
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* @d: ide_pci_device
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* @bar: bar number
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*
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* Checks if a BAR is configured and points to MMIO space. If so
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* print an error and return an error code. Otherwise return 0
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*/
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static int ide_pci_check_iomem(struct pci_dev *dev, ide_pci_device_t *d, int bar)
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{
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ulong flags = pci_resource_flags(dev, bar);
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/* Unconfigured ? */
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if (!flags || pci_resource_len(dev, bar) == 0)
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return 0;
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/* I/O space */
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if(flags & PCI_BASE_ADDRESS_IO_MASK)
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return 0;
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/* Bad */
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printk(KERN_ERR "%s: IO baseregs (BIOS) are reported "
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"as MEM, report to "
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"<andre@linux-ide.org>.\n", d->name);
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return -EINVAL;
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}
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/**
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* ide_hwif_configure - configure an IDE interface
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* @dev: PCI device holding interface
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* @d: IDE pci data
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* @mate: Paired interface if any
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*
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* Perform the initial set up for the hardware interface structure. This
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* is done per interface port rather than per PCI device. There may be
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* more than one port per device.
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*
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* Returns the new hardware interface structure, or NULL on a failure
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*/
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static ide_hwif_t *ide_hwif_configure(struct pci_dev *dev, ide_pci_device_t *d, ide_hwif_t *mate, int port, int irq)
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{
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unsigned long ctl = 0, base = 0;
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ide_hwif_t *hwif;
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if ((d->host_flags & IDE_HFLAG_ISA_PORTS) == 0) {
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/* Possibly we should fail if these checks report true */
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ide_pci_check_iomem(dev, d, 2*port);
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ide_pci_check_iomem(dev, d, 2*port+1);
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ctl = pci_resource_start(dev, 2*port+1);
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base = pci_resource_start(dev, 2*port);
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if ((ctl && !base) || (base && !ctl)) {
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printk(KERN_ERR "%s: inconsistent baseregs (BIOS) "
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"for port %d, skipping\n", d->name, port);
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return NULL;
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}
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}
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if (!ctl)
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{
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/* Use default values */
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ctl = port ? 0x374 : 0x3f4;
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base = port ? 0x170 : 0x1f0;
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}
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if ((hwif = ide_match_hwif(base, d->bootable, d->name)) == NULL)
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return NULL; /* no room in ide_hwifs[] */
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if (hwif->io_ports[IDE_DATA_OFFSET] != base ||
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hwif->io_ports[IDE_CONTROL_OFFSET] != (ctl | 2)) {
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memset(&hwif->hw, 0, sizeof(hwif->hw));
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#ifndef IDE_ARCH_OBSOLETE_INIT
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ide_std_init_ports(&hwif->hw, base, (ctl | 2));
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hwif->hw.io_ports[IDE_IRQ_OFFSET] = 0;
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#else
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ide_init_hwif_ports(&hwif->hw, base, (ctl | 2), NULL);
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#endif
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memcpy(hwif->io_ports, hwif->hw.io_ports, sizeof(hwif->io_ports));
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hwif->noprobe = !hwif->io_ports[IDE_DATA_OFFSET];
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}
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hwif->chipset = ide_pci;
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hwif->pci_dev = dev;
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hwif->cds = (struct ide_pci_device_s *) d;
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hwif->channel = port;
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if (!hwif->irq)
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hwif->irq = irq;
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if (mate) {
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hwif->mate = mate;
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mate->mate = hwif;
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}
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return hwif;
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}
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/**
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* ide_hwif_setup_dma - configure DMA interface
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* @dev: PCI device
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* @d: IDE pci data
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* @hwif: Hardware interface we are configuring
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*
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* Set up the DMA base for the interface. Enable the master bits as
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* necessary and attempt to bring the device DMA into a ready to use
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* state
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*/
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#ifndef CONFIG_BLK_DEV_IDEDMA_PCI
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static void ide_hwif_setup_dma(struct pci_dev *dev, ide_pci_device_t *d, ide_hwif_t *hwif)
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{
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}
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#else
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static void ide_hwif_setup_dma(struct pci_dev *dev, ide_pci_device_t *d, ide_hwif_t *hwif)
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{
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u16 pcicmd;
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pci_read_config_word(dev, PCI_COMMAND, &pcicmd);
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if ((d->autodma == AUTODMA) ||
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((dev->class >> 8) == PCI_CLASS_STORAGE_IDE &&
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(dev->class & 0x80))) {
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unsigned long dma_base = ide_get_or_set_dma_base(hwif);
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if (dma_base && !(pcicmd & PCI_COMMAND_MASTER)) {
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/*
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* Set up BM-DMA capability
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* (PnP BIOS should have done this)
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*/
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/* default DMA off if we had to configure it here */
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hwif->autodma = 0;
|
|
pci_set_master(dev);
|
|
if (pci_read_config_word(dev, PCI_COMMAND, &pcicmd) || !(pcicmd & PCI_COMMAND_MASTER)) {
|
|
printk(KERN_ERR "%s: %s error updating PCICMD\n",
|
|
hwif->name, d->name);
|
|
dma_base = 0;
|
|
}
|
|
}
|
|
if (dma_base) {
|
|
if (d->init_dma) {
|
|
d->init_dma(hwif, dma_base);
|
|
} else {
|
|
ide_setup_dma(hwif, dma_base, 8);
|
|
}
|
|
} else {
|
|
printk(KERN_INFO "%s: %s Bus-Master DMA disabled "
|
|
"(BIOS)\n", hwif->name, d->name);
|
|
}
|
|
}
|
|
}
|
|
#endif /* CONFIG_BLK_DEV_IDEDMA_PCI*/
|
|
|
|
/**
|
|
* ide_setup_pci_controller - set up IDE PCI
|
|
* @dev: PCI device
|
|
* @d: IDE PCI data
|
|
* @noisy: verbose flag
|
|
* @config: returned as 1 if we configured the hardware
|
|
*
|
|
* Set up the PCI and controller side of the IDE interface. This brings
|
|
* up the PCI side of the device, checks that the device is enabled
|
|
* and enables it if need be
|
|
*/
|
|
|
|
static int ide_setup_pci_controller(struct pci_dev *dev, ide_pci_device_t *d, int noisy, int *config)
|
|
{
|
|
int ret;
|
|
u32 class_rev;
|
|
u16 pcicmd;
|
|
|
|
if (noisy)
|
|
ide_setup_pci_noise(dev, d);
|
|
|
|
ret = ide_pci_enable(dev, d);
|
|
if (ret < 0)
|
|
goto out;
|
|
|
|
ret = pci_read_config_word(dev, PCI_COMMAND, &pcicmd);
|
|
if (ret < 0) {
|
|
printk(KERN_ERR "%s: error accessing PCI regs\n", d->name);
|
|
goto out;
|
|
}
|
|
if (!(pcicmd & PCI_COMMAND_IO)) { /* is device disabled? */
|
|
ret = ide_pci_configure(dev, d);
|
|
if (ret < 0)
|
|
goto out;
|
|
*config = 1;
|
|
printk(KERN_INFO "%s: device enabled (Linux)\n", d->name);
|
|
}
|
|
|
|
pci_read_config_dword(dev, PCI_CLASS_REVISION, &class_rev);
|
|
class_rev &= 0xff;
|
|
if (noisy)
|
|
printk(KERN_INFO "%s: chipset revision %d\n", d->name, class_rev);
|
|
out:
|
|
return ret;
|
|
}
|
|
|
|
/**
|
|
* ide_pci_setup_ports - configure ports/devices on PCI IDE
|
|
* @dev: PCI device
|
|
* @d: IDE pci device info
|
|
* @pciirq: IRQ line
|
|
* @index: ata index to update
|
|
*
|
|
* Scan the interfaces attached to this device and do any
|
|
* necessary per port setup. Attach the devices and ask the
|
|
* generic DMA layer to do its work for us.
|
|
*
|
|
* Normally called automaticall from do_ide_pci_setup_device,
|
|
* but is also used directly as a helper function by some controllers
|
|
* where the chipset setup is not the default PCI IDE one.
|
|
*/
|
|
|
|
void ide_pci_setup_ports(struct pci_dev *dev, ide_pci_device_t *d, int pciirq, ata_index_t *index)
|
|
{
|
|
int channels = (d->host_flags & IDE_HFLAG_SINGLE) ? 1 : 2, port;
|
|
int at_least_one_hwif_enabled = 0;
|
|
ide_hwif_t *hwif, *mate = NULL;
|
|
u8 tmp;
|
|
|
|
index->all = 0xf0f0;
|
|
|
|
/*
|
|
* Set up the IDE ports
|
|
*/
|
|
|
|
for (port = 0; port < channels; ++port) {
|
|
ide_pci_enablebit_t *e = &(d->enablebits[port]);
|
|
|
|
if (e->reg && (pci_read_config_byte(dev, e->reg, &tmp) ||
|
|
(tmp & e->mask) != e->val))
|
|
continue; /* port not enabled */
|
|
|
|
if ((hwif = ide_hwif_configure(dev, d, mate, port, pciirq)) == NULL)
|
|
continue;
|
|
|
|
/* setup proper ancestral information */
|
|
hwif->gendev.parent = &dev->dev;
|
|
|
|
if (hwif->channel) {
|
|
index->b.high = hwif->index;
|
|
} else {
|
|
index->b.low = hwif->index;
|
|
}
|
|
|
|
|
|
if (d->init_iops)
|
|
d->init_iops(hwif);
|
|
|
|
if (d->autodma == NODMA)
|
|
goto bypass_legacy_dma;
|
|
|
|
if(d->init_setup_dma)
|
|
d->init_setup_dma(dev, d, hwif);
|
|
else
|
|
ide_hwif_setup_dma(dev, d, hwif);
|
|
bypass_legacy_dma:
|
|
hwif->host_flags = d->host_flags;
|
|
hwif->pio_mask = d->pio_mask;
|
|
|
|
if (d->init_hwif)
|
|
/* Call chipset-specific routine
|
|
* for each enabled hwif
|
|
*/
|
|
d->init_hwif(hwif);
|
|
|
|
mate = hwif;
|
|
at_least_one_hwif_enabled = 1;
|
|
}
|
|
if (!at_least_one_hwif_enabled)
|
|
printk(KERN_INFO "%s: neither IDE port enabled (BIOS)\n", d->name);
|
|
}
|
|
|
|
EXPORT_SYMBOL_GPL(ide_pci_setup_ports);
|
|
|
|
/*
|
|
* ide_setup_pci_device() looks at the primary/secondary interfaces
|
|
* on a PCI IDE device and, if they are enabled, prepares the IDE driver
|
|
* for use with them. This generic code works for most PCI chipsets.
|
|
*
|
|
* One thing that is not standardized is the location of the
|
|
* primary/secondary interface "enable/disable" bits. For chipsets that
|
|
* we "know" about, this information is in the ide_pci_device_t struct;
|
|
* for all other chipsets, we just assume both interfaces are enabled.
|
|
*/
|
|
static int do_ide_setup_pci_device(struct pci_dev *dev, ide_pci_device_t *d,
|
|
ata_index_t *index, u8 noisy)
|
|
{
|
|
static ata_index_t ata_index = { .b = { .low = 0xff, .high = 0xff } };
|
|
int tried_config = 0;
|
|
int pciirq, ret;
|
|
|
|
ret = ide_setup_pci_controller(dev, d, noisy, &tried_config);
|
|
if (ret < 0)
|
|
goto out;
|
|
|
|
/*
|
|
* Can we trust the reported IRQ?
|
|
*/
|
|
pciirq = dev->irq;
|
|
|
|
/* Is it an "IDE storage" device in non-PCI mode? */
|
|
if ((dev->class >> 8) == PCI_CLASS_STORAGE_IDE && (dev->class & 5) != 5) {
|
|
if (noisy)
|
|
printk(KERN_INFO "%s: not 100%% native mode: "
|
|
"will probe irqs later\n", d->name);
|
|
/*
|
|
* This allows offboard ide-pci cards the enable a BIOS,
|
|
* verify interrupt settings of split-mirror pci-config
|
|
* space, place chipset into init-mode, and/or preserve
|
|
* an interrupt if the card is not native ide support.
|
|
*/
|
|
ret = d->init_chipset ? d->init_chipset(dev, d->name) : 0;
|
|
if (ret < 0)
|
|
goto out;
|
|
pciirq = ret;
|
|
} else if (tried_config) {
|
|
if (noisy)
|
|
printk(KERN_INFO "%s: will probe irqs later\n", d->name);
|
|
pciirq = 0;
|
|
} else if (!pciirq) {
|
|
if (noisy)
|
|
printk(KERN_WARNING "%s: bad irq (%d): will probe later\n",
|
|
d->name, pciirq);
|
|
pciirq = 0;
|
|
} else {
|
|
if (d->init_chipset) {
|
|
ret = d->init_chipset(dev, d->name);
|
|
if (ret < 0)
|
|
goto out;
|
|
}
|
|
if (noisy)
|
|
printk(KERN_INFO "%s: 100%% native mode on irq %d\n",
|
|
d->name, pciirq);
|
|
}
|
|
|
|
/* FIXME: silent failure can happen */
|
|
|
|
*index = ata_index;
|
|
ide_pci_setup_ports(dev, d, pciirq, index);
|
|
out:
|
|
return ret;
|
|
}
|
|
|
|
int ide_setup_pci_device(struct pci_dev *dev, ide_pci_device_t *d)
|
|
{
|
|
ide_hwif_t *hwif = NULL, *mate = NULL;
|
|
ata_index_t index_list;
|
|
int ret;
|
|
|
|
ret = do_ide_setup_pci_device(dev, d, &index_list, 1);
|
|
if (ret < 0)
|
|
goto out;
|
|
|
|
if ((index_list.b.low & 0xf0) != 0xf0)
|
|
hwif = &ide_hwifs[index_list.b.low];
|
|
if ((index_list.b.high & 0xf0) != 0xf0)
|
|
mate = &ide_hwifs[index_list.b.high];
|
|
|
|
if (hwif)
|
|
probe_hwif_init_with_fixup(hwif, d->fixup);
|
|
if (mate)
|
|
probe_hwif_init_with_fixup(mate, d->fixup);
|
|
|
|
if (hwif)
|
|
ide_proc_register_port(hwif);
|
|
if (mate)
|
|
ide_proc_register_port(mate);
|
|
out:
|
|
return ret;
|
|
}
|
|
|
|
EXPORT_SYMBOL_GPL(ide_setup_pci_device);
|
|
|
|
int ide_setup_pci_devices(struct pci_dev *dev1, struct pci_dev *dev2,
|
|
ide_pci_device_t *d)
|
|
{
|
|
struct pci_dev *pdev[] = { dev1, dev2 };
|
|
ata_index_t index_list[2];
|
|
int ret, i;
|
|
|
|
for (i = 0; i < 2; i++) {
|
|
ret = do_ide_setup_pci_device(pdev[i], d, index_list + i, !i);
|
|
/*
|
|
* FIXME: Mom, mom, they stole me the helper function to undo
|
|
* do_ide_setup_pci_device() on the first device!
|
|
*/
|
|
if (ret < 0)
|
|
goto out;
|
|
}
|
|
|
|
for (i = 0; i < 2; i++) {
|
|
u8 idx[2] = { index_list[i].b.low, index_list[i].b.high };
|
|
int j;
|
|
|
|
for (j = 0; j < 2; j++) {
|
|
if ((idx[j] & 0xf0) != 0xf0)
|
|
probe_hwif_init(ide_hwifs + idx[j]);
|
|
}
|
|
}
|
|
|
|
for (i = 0; i < 2; i++) {
|
|
u8 idx[2] = { index_list[i].b.low, index_list[i].b.high };
|
|
int j;
|
|
|
|
for (j = 0; j < 2; j++) {
|
|
if ((idx[j] & 0xf0) != 0xf0)
|
|
ide_proc_register_port(ide_hwifs + idx[j]);
|
|
}
|
|
}
|
|
out:
|
|
return ret;
|
|
}
|
|
|
|
EXPORT_SYMBOL_GPL(ide_setup_pci_devices);
|
|
|
|
#ifdef CONFIG_IDEPCI_PCIBUS_ORDER
|
|
/*
|
|
* Module interfaces
|
|
*/
|
|
|
|
static int pre_init = 1; /* Before first ordered IDE scan */
|
|
static LIST_HEAD(ide_pci_drivers);
|
|
|
|
/*
|
|
* __ide_pci_register_driver - attach IDE driver
|
|
* @driver: pci driver
|
|
* @module: owner module of the driver
|
|
*
|
|
* Registers a driver with the IDE layer. The IDE layer arranges that
|
|
* boot time setup is done in the expected device order and then
|
|
* hands the controllers off to the core PCI code to do the rest of
|
|
* the work.
|
|
*
|
|
* The driver_data of the driver table must point to an ide_pci_device_t
|
|
* describing the interface.
|
|
*
|
|
* Returns are the same as for pci_register_driver
|
|
*/
|
|
|
|
int __ide_pci_register_driver(struct pci_driver *driver, struct module *module,
|
|
const char *mod_name)
|
|
{
|
|
if(!pre_init)
|
|
return __pci_register_driver(driver, module, mod_name);
|
|
driver->driver.owner = module;
|
|
list_add_tail(&driver->node, &ide_pci_drivers);
|
|
return 0;
|
|
}
|
|
|
|
EXPORT_SYMBOL_GPL(__ide_pci_register_driver);
|
|
|
|
/**
|
|
* ide_scan_pcidev - find an IDE driver for a device
|
|
* @dev: PCI device to check
|
|
*
|
|
* Look for an IDE driver to handle the device we are considering.
|
|
* This is only used during boot up to get the ordering correct. After
|
|
* boot up the pci layer takes over the job.
|
|
*/
|
|
|
|
static int __init ide_scan_pcidev(struct pci_dev *dev)
|
|
{
|
|
struct list_head *l;
|
|
struct pci_driver *d;
|
|
|
|
list_for_each(l, &ide_pci_drivers) {
|
|
d = list_entry(l, struct pci_driver, node);
|
|
if (d->id_table) {
|
|
const struct pci_device_id *id = pci_match_id(d->id_table,
|
|
dev);
|
|
if (id != NULL && d->probe(dev, id) >= 0) {
|
|
dev->driver = d;
|
|
pci_dev_get(dev);
|
|
return 1;
|
|
}
|
|
}
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
/**
|
|
* ide_scan_pcibus - perform the initial IDE driver scan
|
|
* @scan_direction: set for reverse order scanning
|
|
*
|
|
* Perform the initial bus rather than driver ordered scan of the
|
|
* PCI drivers. After this all IDE pci handling becomes standard
|
|
* module ordering not traditionally ordered.
|
|
*/
|
|
|
|
void __init ide_scan_pcibus (int scan_direction)
|
|
{
|
|
struct pci_dev *dev = NULL;
|
|
struct pci_driver *d;
|
|
struct list_head *l, *n;
|
|
|
|
pre_init = 0;
|
|
if (!scan_direction)
|
|
while ((dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev)) != NULL)
|
|
ide_scan_pcidev(dev);
|
|
else
|
|
while ((dev = pci_get_device_reverse(PCI_ANY_ID, PCI_ANY_ID, dev))
|
|
!= NULL)
|
|
ide_scan_pcidev(dev);
|
|
|
|
/*
|
|
* Hand the drivers over to the PCI layer now we
|
|
* are post init.
|
|
*/
|
|
|
|
list_for_each_safe(l, n, &ide_pci_drivers) {
|
|
list_del(l);
|
|
d = list_entry(l, struct pci_driver, node);
|
|
if (__pci_register_driver(d, d->driver.owner, d->driver.mod_name))
|
|
printk(KERN_ERR "%s: failed to register driver for %s\n",
|
|
__FUNCTION__, d->driver.mod_name);
|
|
}
|
|
}
|
|
#endif
|