588 строки
15 KiB
C
588 строки
15 KiB
C
/*
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* Designware SPI core controller driver (refer pxa2xx_spi.c)
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*
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* Copyright (c) 2009, Intel Corporation.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*/
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#include <linux/dma-mapping.h>
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#include <linux/interrupt.h>
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#include <linux/module.h>
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#include <linux/highmem.h>
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#include <linux/delay.h>
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#include <linux/slab.h>
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#include <linux/spi/spi.h>
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#include <linux/gpio.h>
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#include "spi-dw.h"
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#ifdef CONFIG_DEBUG_FS
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#include <linux/debugfs.h>
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#endif
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/* Slave spi_dev related */
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struct chip_data {
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u8 tmode; /* TR/TO/RO/EEPROM */
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u8 type; /* SPI/SSP/MicroWire */
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u8 poll_mode; /* 1 means use poll mode */
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u16 clk_div; /* baud rate divider */
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u32 speed_hz; /* baud rate */
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void (*cs_control)(u32 command);
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};
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#ifdef CONFIG_DEBUG_FS
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#define SPI_REGS_BUFSIZE 1024
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static ssize_t dw_spi_show_regs(struct file *file, char __user *user_buf,
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size_t count, loff_t *ppos)
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{
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struct dw_spi *dws = file->private_data;
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char *buf;
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u32 len = 0;
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ssize_t ret;
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buf = kzalloc(SPI_REGS_BUFSIZE, GFP_KERNEL);
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if (!buf)
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return 0;
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len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
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"%s registers:\n", dev_name(&dws->master->dev));
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len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
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"=================================\n");
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len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
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"CTRL0: \t\t0x%08x\n", dw_readl(dws, DW_SPI_CTRL0));
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len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
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"CTRL1: \t\t0x%08x\n", dw_readl(dws, DW_SPI_CTRL1));
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len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
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"SSIENR: \t0x%08x\n", dw_readl(dws, DW_SPI_SSIENR));
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len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
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"SER: \t\t0x%08x\n", dw_readl(dws, DW_SPI_SER));
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len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
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"BAUDR: \t\t0x%08x\n", dw_readl(dws, DW_SPI_BAUDR));
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len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
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"TXFTLR: \t0x%08x\n", dw_readl(dws, DW_SPI_TXFLTR));
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len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
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"RXFTLR: \t0x%08x\n", dw_readl(dws, DW_SPI_RXFLTR));
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len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
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"TXFLR: \t\t0x%08x\n", dw_readl(dws, DW_SPI_TXFLR));
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len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
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"RXFLR: \t\t0x%08x\n", dw_readl(dws, DW_SPI_RXFLR));
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len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
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"SR: \t\t0x%08x\n", dw_readl(dws, DW_SPI_SR));
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len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
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"IMR: \t\t0x%08x\n", dw_readl(dws, DW_SPI_IMR));
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len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
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"ISR: \t\t0x%08x\n", dw_readl(dws, DW_SPI_ISR));
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len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
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"DMACR: \t\t0x%08x\n", dw_readl(dws, DW_SPI_DMACR));
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len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
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"DMATDLR: \t0x%08x\n", dw_readl(dws, DW_SPI_DMATDLR));
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len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
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"DMARDLR: \t0x%08x\n", dw_readl(dws, DW_SPI_DMARDLR));
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len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
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"=================================\n");
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ret = simple_read_from_buffer(user_buf, count, ppos, buf, len);
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kfree(buf);
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return ret;
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}
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static const struct file_operations dw_spi_regs_ops = {
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.owner = THIS_MODULE,
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.open = simple_open,
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.read = dw_spi_show_regs,
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.llseek = default_llseek,
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};
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static int dw_spi_debugfs_init(struct dw_spi *dws)
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{
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char name[32];
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snprintf(name, 32, "dw_spi%d", dws->master->bus_num);
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dws->debugfs = debugfs_create_dir(name, NULL);
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if (!dws->debugfs)
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return -ENOMEM;
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debugfs_create_file("registers", S_IFREG | S_IRUGO,
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dws->debugfs, (void *)dws, &dw_spi_regs_ops);
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return 0;
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}
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static void dw_spi_debugfs_remove(struct dw_spi *dws)
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{
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debugfs_remove_recursive(dws->debugfs);
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}
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#else
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static inline int dw_spi_debugfs_init(struct dw_spi *dws)
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{
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return 0;
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}
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static inline void dw_spi_debugfs_remove(struct dw_spi *dws)
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{
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}
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#endif /* CONFIG_DEBUG_FS */
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void dw_spi_set_cs(struct spi_device *spi, bool enable)
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{
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struct dw_spi *dws = spi_controller_get_devdata(spi->controller);
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struct chip_data *chip = spi_get_ctldata(spi);
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/* Chip select logic is inverted from spi_set_cs() */
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if (chip && chip->cs_control)
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chip->cs_control(!enable);
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if (!enable)
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dw_writel(dws, DW_SPI_SER, BIT(spi->chip_select));
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}
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EXPORT_SYMBOL_GPL(dw_spi_set_cs);
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/* Return the max entries we can fill into tx fifo */
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static inline u32 tx_max(struct dw_spi *dws)
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{
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u32 tx_left, tx_room, rxtx_gap;
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tx_left = (dws->tx_end - dws->tx) / dws->n_bytes;
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tx_room = dws->fifo_len - dw_readl(dws, DW_SPI_TXFLR);
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/*
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* Another concern is about the tx/rx mismatch, we
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* though to use (dws->fifo_len - rxflr - txflr) as
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* one maximum value for tx, but it doesn't cover the
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* data which is out of tx/rx fifo and inside the
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* shift registers. So a control from sw point of
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* view is taken.
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*/
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rxtx_gap = ((dws->rx_end - dws->rx) - (dws->tx_end - dws->tx))
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/ dws->n_bytes;
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return min3(tx_left, tx_room, (u32) (dws->fifo_len - rxtx_gap));
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}
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/* Return the max entries we should read out of rx fifo */
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static inline u32 rx_max(struct dw_spi *dws)
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{
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u32 rx_left = (dws->rx_end - dws->rx) / dws->n_bytes;
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return min_t(u32, rx_left, dw_readl(dws, DW_SPI_RXFLR));
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}
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static void dw_writer(struct dw_spi *dws)
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{
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u32 max = tx_max(dws);
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u16 txw = 0;
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while (max--) {
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/* Set the tx word if the transfer's original "tx" is not null */
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if (dws->tx_end - dws->len) {
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if (dws->n_bytes == 1)
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txw = *(u8 *)(dws->tx);
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else
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txw = *(u16 *)(dws->tx);
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}
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dw_write_io_reg(dws, DW_SPI_DR, txw);
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dws->tx += dws->n_bytes;
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}
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}
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static void dw_reader(struct dw_spi *dws)
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{
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u32 max = rx_max(dws);
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u16 rxw;
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while (max--) {
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rxw = dw_read_io_reg(dws, DW_SPI_DR);
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/* Care rx only if the transfer's original "rx" is not null */
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if (dws->rx_end - dws->len) {
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if (dws->n_bytes == 1)
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*(u8 *)(dws->rx) = rxw;
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else
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*(u16 *)(dws->rx) = rxw;
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}
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dws->rx += dws->n_bytes;
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}
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}
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static void int_error_stop(struct dw_spi *dws, const char *msg)
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{
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spi_reset_chip(dws);
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dev_err(&dws->master->dev, "%s\n", msg);
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dws->master->cur_msg->status = -EIO;
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spi_finalize_current_transfer(dws->master);
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}
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static irqreturn_t interrupt_transfer(struct dw_spi *dws)
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{
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u16 irq_status = dw_readl(dws, DW_SPI_ISR);
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/* Error handling */
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if (irq_status & (SPI_INT_TXOI | SPI_INT_RXOI | SPI_INT_RXUI)) {
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dw_readl(dws, DW_SPI_ICR);
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int_error_stop(dws, "interrupt_transfer: fifo overrun/underrun");
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return IRQ_HANDLED;
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}
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dw_reader(dws);
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if (dws->rx_end == dws->rx) {
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spi_mask_intr(dws, SPI_INT_TXEI);
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spi_finalize_current_transfer(dws->master);
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return IRQ_HANDLED;
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}
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if (irq_status & SPI_INT_TXEI) {
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spi_mask_intr(dws, SPI_INT_TXEI);
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dw_writer(dws);
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/* Enable TX irq always, it will be disabled when RX finished */
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spi_umask_intr(dws, SPI_INT_TXEI);
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}
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return IRQ_HANDLED;
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}
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static irqreturn_t dw_spi_irq(int irq, void *dev_id)
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{
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struct spi_controller *master = dev_id;
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struct dw_spi *dws = spi_controller_get_devdata(master);
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u16 irq_status = dw_readl(dws, DW_SPI_ISR) & 0x3f;
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if (!irq_status)
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return IRQ_NONE;
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if (!master->cur_msg) {
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spi_mask_intr(dws, SPI_INT_TXEI);
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return IRQ_HANDLED;
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}
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return dws->transfer_handler(dws);
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}
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/* Must be called inside pump_transfers() */
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static int poll_transfer(struct dw_spi *dws)
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{
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do {
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dw_writer(dws);
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dw_reader(dws);
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cpu_relax();
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} while (dws->rx_end > dws->rx);
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return 0;
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}
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static int dw_spi_transfer_one(struct spi_controller *master,
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struct spi_device *spi, struct spi_transfer *transfer)
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{
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struct dw_spi *dws = spi_controller_get_devdata(master);
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struct chip_data *chip = spi_get_ctldata(spi);
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u8 imask = 0;
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u16 txlevel = 0;
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u32 cr0;
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int ret;
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dws->dma_mapped = 0;
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dws->tx = (void *)transfer->tx_buf;
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dws->tx_end = dws->tx + transfer->len;
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dws->rx = transfer->rx_buf;
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dws->rx_end = dws->rx + transfer->len;
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dws->len = transfer->len;
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spi_enable_chip(dws, 0);
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/* Handle per transfer options for bpw and speed */
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if (transfer->speed_hz != dws->current_freq) {
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if (transfer->speed_hz != chip->speed_hz) {
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/* clk_div doesn't support odd number */
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chip->clk_div = (DIV_ROUND_UP(dws->max_freq, transfer->speed_hz) + 1) & 0xfffe;
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chip->speed_hz = transfer->speed_hz;
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}
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dws->current_freq = transfer->speed_hz;
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spi_set_clk(dws, chip->clk_div);
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}
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if (transfer->bits_per_word == 8) {
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dws->n_bytes = 1;
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dws->dma_width = 1;
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} else if (transfer->bits_per_word == 16) {
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dws->n_bytes = 2;
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dws->dma_width = 2;
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} else {
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return -EINVAL;
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}
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/* Default SPI mode is SCPOL = 0, SCPH = 0 */
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cr0 = (transfer->bits_per_word - 1)
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| (chip->type << SPI_FRF_OFFSET)
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| (spi->mode << SPI_MODE_OFFSET)
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| (chip->tmode << SPI_TMOD_OFFSET);
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/*
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* Adjust transfer mode if necessary. Requires platform dependent
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* chipselect mechanism.
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*/
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if (chip->cs_control) {
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if (dws->rx && dws->tx)
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chip->tmode = SPI_TMOD_TR;
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else if (dws->rx)
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chip->tmode = SPI_TMOD_RO;
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else
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chip->tmode = SPI_TMOD_TO;
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cr0 &= ~SPI_TMOD_MASK;
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cr0 |= (chip->tmode << SPI_TMOD_OFFSET);
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}
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dw_writel(dws, DW_SPI_CTRL0, cr0);
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/* Check if current transfer is a DMA transaction */
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if (master->can_dma && master->can_dma(master, spi, transfer))
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dws->dma_mapped = master->cur_msg_mapped;
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/* For poll mode just disable all interrupts */
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spi_mask_intr(dws, 0xff);
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/*
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* Interrupt mode
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* we only need set the TXEI IRQ, as TX/RX always happen syncronizely
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*/
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if (dws->dma_mapped) {
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ret = dws->dma_ops->dma_setup(dws, transfer);
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if (ret < 0) {
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spi_enable_chip(dws, 1);
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return ret;
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}
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} else if (!chip->poll_mode) {
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txlevel = min_t(u16, dws->fifo_len / 2, dws->len / dws->n_bytes);
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dw_writel(dws, DW_SPI_TXFLTR, txlevel);
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/* Set the interrupt mask */
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imask |= SPI_INT_TXEI | SPI_INT_TXOI |
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SPI_INT_RXUI | SPI_INT_RXOI;
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spi_umask_intr(dws, imask);
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dws->transfer_handler = interrupt_transfer;
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}
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spi_enable_chip(dws, 1);
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if (dws->dma_mapped) {
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ret = dws->dma_ops->dma_transfer(dws, transfer);
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if (ret < 0)
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return ret;
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}
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if (chip->poll_mode)
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return poll_transfer(dws);
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return 1;
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}
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static void dw_spi_handle_err(struct spi_controller *master,
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struct spi_message *msg)
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{
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struct dw_spi *dws = spi_controller_get_devdata(master);
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if (dws->dma_mapped)
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dws->dma_ops->dma_stop(dws);
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spi_reset_chip(dws);
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}
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/* This may be called twice for each spi dev */
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static int dw_spi_setup(struct spi_device *spi)
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{
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struct dw_spi_chip *chip_info = NULL;
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struct chip_data *chip;
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int ret;
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/* Only alloc on first setup */
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chip = spi_get_ctldata(spi);
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if (!chip) {
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chip = kzalloc(sizeof(struct chip_data), GFP_KERNEL);
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if (!chip)
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return -ENOMEM;
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spi_set_ctldata(spi, chip);
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}
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/*
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* Protocol drivers may change the chip settings, so...
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* if chip_info exists, use it
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*/
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chip_info = spi->controller_data;
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/* chip_info doesn't always exist */
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if (chip_info) {
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if (chip_info->cs_control)
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chip->cs_control = chip_info->cs_control;
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chip->poll_mode = chip_info->poll_mode;
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chip->type = chip_info->type;
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}
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chip->tmode = SPI_TMOD_TR;
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if (gpio_is_valid(spi->cs_gpio)) {
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ret = gpio_direction_output(spi->cs_gpio,
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!(spi->mode & SPI_CS_HIGH));
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if (ret)
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return ret;
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}
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return 0;
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}
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static void dw_spi_cleanup(struct spi_device *spi)
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{
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struct chip_data *chip = spi_get_ctldata(spi);
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kfree(chip);
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spi_set_ctldata(spi, NULL);
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}
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/* Restart the controller, disable all interrupts, clean rx fifo */
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static void spi_hw_init(struct device *dev, struct dw_spi *dws)
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{
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spi_reset_chip(dws);
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/*
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* Try to detect the FIFO depth if not set by interface driver,
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* the depth could be from 2 to 256 from HW spec
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*/
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if (!dws->fifo_len) {
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u32 fifo;
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for (fifo = 1; fifo < 256; fifo++) {
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dw_writel(dws, DW_SPI_TXFLTR, fifo);
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if (fifo != dw_readl(dws, DW_SPI_TXFLTR))
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break;
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}
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dw_writel(dws, DW_SPI_TXFLTR, 0);
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dws->fifo_len = (fifo == 1) ? 0 : fifo;
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dev_dbg(dev, "Detected FIFO size: %u bytes\n", dws->fifo_len);
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}
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}
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int dw_spi_add_host(struct device *dev, struct dw_spi *dws)
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{
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struct spi_controller *master;
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int ret;
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BUG_ON(dws == NULL);
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|
|
|
master = spi_alloc_master(dev, 0);
|
|
if (!master)
|
|
return -ENOMEM;
|
|
|
|
dws->master = master;
|
|
dws->type = SSI_MOTO_SPI;
|
|
dws->dma_inited = 0;
|
|
dws->dma_addr = (dma_addr_t)(dws->paddr + DW_SPI_DR);
|
|
|
|
spi_controller_set_devdata(master, dws);
|
|
|
|
ret = request_irq(dws->irq, dw_spi_irq, IRQF_SHARED, dev_name(dev),
|
|
master);
|
|
if (ret < 0) {
|
|
dev_err(dev, "can not get IRQ\n");
|
|
goto err_free_master;
|
|
}
|
|
|
|
master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LOOP;
|
|
master->bits_per_word_mask = SPI_BPW_MASK(8) | SPI_BPW_MASK(16);
|
|
master->bus_num = dws->bus_num;
|
|
master->num_chipselect = dws->num_cs;
|
|
master->setup = dw_spi_setup;
|
|
master->cleanup = dw_spi_cleanup;
|
|
master->set_cs = dw_spi_set_cs;
|
|
master->transfer_one = dw_spi_transfer_one;
|
|
master->handle_err = dw_spi_handle_err;
|
|
master->max_speed_hz = dws->max_freq;
|
|
master->dev.of_node = dev->of_node;
|
|
master->flags = SPI_MASTER_GPIO_SS;
|
|
|
|
if (dws->set_cs)
|
|
master->set_cs = dws->set_cs;
|
|
|
|
/* Basic HW init */
|
|
spi_hw_init(dev, dws);
|
|
|
|
if (dws->dma_ops && dws->dma_ops->dma_init) {
|
|
ret = dws->dma_ops->dma_init(dws);
|
|
if (ret) {
|
|
dev_warn(dev, "DMA init failed\n");
|
|
dws->dma_inited = 0;
|
|
} else {
|
|
master->can_dma = dws->dma_ops->can_dma;
|
|
}
|
|
}
|
|
|
|
ret = devm_spi_register_controller(dev, master);
|
|
if (ret) {
|
|
dev_err(&master->dev, "problem registering spi master\n");
|
|
goto err_dma_exit;
|
|
}
|
|
|
|
dw_spi_debugfs_init(dws);
|
|
return 0;
|
|
|
|
err_dma_exit:
|
|
if (dws->dma_ops && dws->dma_ops->dma_exit)
|
|
dws->dma_ops->dma_exit(dws);
|
|
spi_enable_chip(dws, 0);
|
|
free_irq(dws->irq, master);
|
|
err_free_master:
|
|
spi_controller_put(master);
|
|
return ret;
|
|
}
|
|
EXPORT_SYMBOL_GPL(dw_spi_add_host);
|
|
|
|
void dw_spi_remove_host(struct dw_spi *dws)
|
|
{
|
|
dw_spi_debugfs_remove(dws);
|
|
|
|
if (dws->dma_ops && dws->dma_ops->dma_exit)
|
|
dws->dma_ops->dma_exit(dws);
|
|
|
|
spi_shutdown_chip(dws);
|
|
|
|
free_irq(dws->irq, dws->master);
|
|
}
|
|
EXPORT_SYMBOL_GPL(dw_spi_remove_host);
|
|
|
|
int dw_spi_suspend_host(struct dw_spi *dws)
|
|
{
|
|
int ret;
|
|
|
|
ret = spi_controller_suspend(dws->master);
|
|
if (ret)
|
|
return ret;
|
|
|
|
spi_shutdown_chip(dws);
|
|
return 0;
|
|
}
|
|
EXPORT_SYMBOL_GPL(dw_spi_suspend_host);
|
|
|
|
int dw_spi_resume_host(struct dw_spi *dws)
|
|
{
|
|
int ret;
|
|
|
|
spi_hw_init(&dws->master->dev, dws);
|
|
ret = spi_controller_resume(dws->master);
|
|
if (ret)
|
|
dev_err(&dws->master->dev, "fail to start queue (%d)\n", ret);
|
|
return ret;
|
|
}
|
|
EXPORT_SYMBOL_GPL(dw_spi_resume_host);
|
|
|
|
MODULE_AUTHOR("Feng Tang <feng.tang@intel.com>");
|
|
MODULE_DESCRIPTION("Driver for DesignWare SPI controller core");
|
|
MODULE_LICENSE("GPL v2");
|