319 строки
7.4 KiB
C
319 строки
7.4 KiB
C
/*
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* arch/arm/mm/cache-feroceon-l2.c - Feroceon L2 cache controller support
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*
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* Copyright (C) 2008 Marvell Semiconductor
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*
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* References:
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* - Unified Layer 2 Cache for Feroceon CPU Cores,
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* Document ID MV-S104858-00, Rev. A, October 23 2007.
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*/
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#include <linux/init.h>
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#include <asm/cacheflush.h>
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#include <asm/plat-orion/cache-feroceon-l2.h>
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/*
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* Low-level cache maintenance operations.
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*
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* As well as the regular 'clean/invalidate/flush L2 cache line by
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* MVA' instructions, the Feroceon L2 cache controller also features
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* 'clean/invalidate L2 range by MVA' operations.
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*
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* Cache range operations are initiated by writing the start and
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* end addresses to successive cp15 registers, and process every
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* cache line whose first byte address lies in the inclusive range
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* [start:end].
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*
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* The cache range operations stall the CPU pipeline until completion.
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*
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* The range operations require two successive cp15 writes, in
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* between which we don't want to be preempted.
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*/
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static inline void l2_clean_pa(unsigned long addr)
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{
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__asm__("mcr p15, 1, %0, c15, c9, 3" : : "r" (addr));
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}
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static inline void l2_clean_mva_range(unsigned long start, unsigned long end)
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{
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unsigned long flags;
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/*
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* Make sure 'start' and 'end' reference the same page, as
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* L2 is PIPT and range operations only do a TLB lookup on
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* the start address.
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*/
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BUG_ON((start ^ end) & ~(PAGE_SIZE - 1));
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raw_local_irq_save(flags);
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__asm__("mcr p15, 1, %0, c15, c9, 4" : : "r" (start));
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__asm__("mcr p15, 1, %0, c15, c9, 5" : : "r" (end));
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raw_local_irq_restore(flags);
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}
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static inline void l2_clean_pa_range(unsigned long start, unsigned long end)
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{
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l2_clean_mva_range(__phys_to_virt(start), __phys_to_virt(end));
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}
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static inline void l2_clean_inv_pa(unsigned long addr)
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{
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__asm__("mcr p15, 1, %0, c15, c10, 3" : : "r" (addr));
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}
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static inline void l2_inv_pa(unsigned long addr)
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{
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__asm__("mcr p15, 1, %0, c15, c11, 3" : : "r" (addr));
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}
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static inline void l2_inv_mva_range(unsigned long start, unsigned long end)
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{
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unsigned long flags;
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/*
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* Make sure 'start' and 'end' reference the same page, as
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* L2 is PIPT and range operations only do a TLB lookup on
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* the start address.
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*/
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BUG_ON((start ^ end) & ~(PAGE_SIZE - 1));
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raw_local_irq_save(flags);
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__asm__("mcr p15, 1, %0, c15, c11, 4" : : "r" (start));
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__asm__("mcr p15, 1, %0, c15, c11, 5" : : "r" (end));
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raw_local_irq_restore(flags);
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}
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static inline void l2_inv_pa_range(unsigned long start, unsigned long end)
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{
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l2_inv_mva_range(__phys_to_virt(start), __phys_to_virt(end));
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}
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/*
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* Linux primitives.
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*
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* Note that the end addresses passed to Linux primitives are
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* noninclusive, while the hardware cache range operations use
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* inclusive start and end addresses.
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*/
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#define CACHE_LINE_SIZE 32
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#define MAX_RANGE_SIZE 1024
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static int l2_wt_override;
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static unsigned long calc_range_end(unsigned long start, unsigned long end)
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{
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unsigned long range_end;
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BUG_ON(start & (CACHE_LINE_SIZE - 1));
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BUG_ON(end & (CACHE_LINE_SIZE - 1));
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/*
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* Try to process all cache lines between 'start' and 'end'.
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*/
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range_end = end;
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/*
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* Limit the number of cache lines processed at once,
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* since cache range operations stall the CPU pipeline
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* until completion.
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*/
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if (range_end > start + MAX_RANGE_SIZE)
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range_end = start + MAX_RANGE_SIZE;
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/*
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* Cache range operations can't straddle a page boundary.
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*/
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if (range_end > (start | (PAGE_SIZE - 1)) + 1)
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range_end = (start | (PAGE_SIZE - 1)) + 1;
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return range_end;
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}
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static void feroceon_l2_inv_range(unsigned long start, unsigned long end)
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{
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/*
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* Clean and invalidate partial first cache line.
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*/
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if (start & (CACHE_LINE_SIZE - 1)) {
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l2_clean_inv_pa(start & ~(CACHE_LINE_SIZE - 1));
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start = (start | (CACHE_LINE_SIZE - 1)) + 1;
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}
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/*
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* Clean and invalidate partial last cache line.
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*/
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if (end & (CACHE_LINE_SIZE - 1)) {
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l2_clean_inv_pa(end & ~(CACHE_LINE_SIZE - 1));
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end &= ~(CACHE_LINE_SIZE - 1);
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}
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/*
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* Invalidate all full cache lines between 'start' and 'end'.
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*/
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while (start != end) {
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unsigned long range_end = calc_range_end(start, end);
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l2_inv_pa_range(start, range_end - CACHE_LINE_SIZE);
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start = range_end;
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}
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dsb();
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}
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static void feroceon_l2_clean_range(unsigned long start, unsigned long end)
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{
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/*
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* If L2 is forced to WT, the L2 will always be clean and we
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* don't need to do anything here.
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*/
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if (!l2_wt_override) {
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start &= ~(CACHE_LINE_SIZE - 1);
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end = (end + CACHE_LINE_SIZE - 1) & ~(CACHE_LINE_SIZE - 1);
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while (start != end) {
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unsigned long range_end = calc_range_end(start, end);
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l2_clean_pa_range(start, range_end - CACHE_LINE_SIZE);
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start = range_end;
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}
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}
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dsb();
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}
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static void feroceon_l2_flush_range(unsigned long start, unsigned long end)
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{
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start &= ~(CACHE_LINE_SIZE - 1);
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end = (end + CACHE_LINE_SIZE - 1) & ~(CACHE_LINE_SIZE - 1);
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while (start != end) {
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unsigned long range_end = calc_range_end(start, end);
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if (!l2_wt_override)
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l2_clean_pa_range(start, range_end - CACHE_LINE_SIZE);
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l2_inv_pa_range(start, range_end - CACHE_LINE_SIZE);
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start = range_end;
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}
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dsb();
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}
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/*
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* Routines to disable and re-enable the D-cache and I-cache at run
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* time. These are necessary because the L2 cache can only be enabled
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* or disabled while the L1 Dcache and Icache are both disabled.
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*/
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static void __init invalidate_and_disable_dcache(void)
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{
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u32 cr;
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cr = get_cr();
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if (cr & CR_C) {
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unsigned long flags;
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raw_local_irq_save(flags);
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flush_cache_all();
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set_cr(cr & ~CR_C);
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raw_local_irq_restore(flags);
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}
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}
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static void __init enable_dcache(void)
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{
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u32 cr;
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cr = get_cr();
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if (!(cr & CR_C))
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set_cr(cr | CR_C);
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}
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static void __init __invalidate_icache(void)
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{
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int dummy;
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__asm__ __volatile__("mcr p15, 0, %0, c7, c5, 0\n" : "=r" (dummy));
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}
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static void __init invalidate_and_disable_icache(void)
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{
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u32 cr;
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cr = get_cr();
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if (cr & CR_I) {
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set_cr(cr & ~CR_I);
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__invalidate_icache();
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}
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}
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static void __init enable_icache(void)
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{
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u32 cr;
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cr = get_cr();
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if (!(cr & CR_I))
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set_cr(cr | CR_I);
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}
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static inline u32 read_extra_features(void)
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{
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u32 u;
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__asm__("mrc p15, 1, %0, c15, c1, 0" : "=r" (u));
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return u;
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}
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static inline void write_extra_features(u32 u)
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{
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__asm__("mcr p15, 1, %0, c15, c1, 0" : : "r" (u));
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}
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static void __init disable_l2_prefetch(void)
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{
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u32 u;
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/*
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* Read the CPU Extra Features register and verify that the
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* Disable L2 Prefetch bit is set.
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*/
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u = read_extra_features();
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if (!(u & 0x01000000)) {
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printk(KERN_INFO "Feroceon L2: Disabling L2 prefetch.\n");
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write_extra_features(u | 0x01000000);
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}
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}
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static void __init enable_l2(void)
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{
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u32 u;
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u = read_extra_features();
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if (!(u & 0x00400000)) {
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printk(KERN_INFO "Feroceon L2: Enabling L2\n");
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invalidate_and_disable_dcache();
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invalidate_and_disable_icache();
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write_extra_features(u | 0x00400000);
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enable_icache();
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enable_dcache();
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}
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}
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void __init feroceon_l2_init(int __l2_wt_override)
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{
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l2_wt_override = __l2_wt_override;
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disable_l2_prefetch();
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outer_cache.inv_range = feroceon_l2_inv_range;
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outer_cache.clean_range = feroceon_l2_clean_range;
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outer_cache.flush_range = feroceon_l2_flush_range;
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enable_l2();
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printk(KERN_INFO "Feroceon L2: Cache support initialised%s.\n",
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l2_wt_override ? ", in WT override mode" : "");
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}
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