413 строки
12 KiB
C
413 строки
12 KiB
C
/*
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* Freescale STMP37XX/STMP378X Real Time Clock driver
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*
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* Copyright (c) 2007 Sigmatel, Inc.
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* Peter Hartley, <peter.hartley@sigmatel.com>
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*
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* Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
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* Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
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* Copyright 2011 Wolfram Sang, Pengutronix e.K.
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*/
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/*
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* The code contained herein is licensed under the GNU General Public
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* License. You may obtain a copy of the GNU General Public License
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* Version 2 or later at the following locations:
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*
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* http://www.opensource.org/licenses/gpl-license.html
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* http://www.gnu.org/copyleft/gpl.html
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*/
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/io.h>
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#include <linux/init.h>
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#include <linux/platform_device.h>
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#include <linux/interrupt.h>
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#include <linux/delay.h>
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#include <linux/rtc.h>
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#include <linux/slab.h>
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#include <linux/of_device.h>
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#include <linux/of.h>
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#include <linux/stmp_device.h>
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#include <linux/stmp3xxx_rtc_wdt.h>
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#define STMP3XXX_RTC_CTRL 0x0
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#define STMP3XXX_RTC_CTRL_ALARM_IRQ_EN 0x00000001
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#define STMP3XXX_RTC_CTRL_ONEMSEC_IRQ_EN 0x00000002
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#define STMP3XXX_RTC_CTRL_ALARM_IRQ 0x00000004
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#define STMP3XXX_RTC_CTRL_WATCHDOGEN 0x00000010
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#define STMP3XXX_RTC_STAT 0x10
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#define STMP3XXX_RTC_STAT_STALE_SHIFT 16
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#define STMP3XXX_RTC_STAT_RTC_PRESENT 0x80000000
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#define STMP3XXX_RTC_STAT_XTAL32000_PRESENT 0x10000000
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#define STMP3XXX_RTC_STAT_XTAL32768_PRESENT 0x08000000
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#define STMP3XXX_RTC_SECONDS 0x30
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#define STMP3XXX_RTC_ALARM 0x40
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#define STMP3XXX_RTC_WATCHDOG 0x50
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#define STMP3XXX_RTC_PERSISTENT0 0x60
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#define STMP3XXX_RTC_PERSISTENT0_CLOCKSOURCE (1 << 0)
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#define STMP3XXX_RTC_PERSISTENT0_ALARM_WAKE_EN (1 << 1)
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#define STMP3XXX_RTC_PERSISTENT0_ALARM_EN (1 << 2)
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#define STMP3XXX_RTC_PERSISTENT0_XTAL24MHZ_PWRUP (1 << 4)
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#define STMP3XXX_RTC_PERSISTENT0_XTAL32KHZ_PWRUP (1 << 5)
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#define STMP3XXX_RTC_PERSISTENT0_XTAL32_FREQ (1 << 6)
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#define STMP3XXX_RTC_PERSISTENT0_ALARM_WAKE (1 << 7)
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#define STMP3XXX_RTC_PERSISTENT1 0x70
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/* missing bitmask in headers */
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#define STMP3XXX_RTC_PERSISTENT1_FORCE_UPDATER 0x80000000
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struct stmp3xxx_rtc_data {
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struct rtc_device *rtc;
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void __iomem *io;
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int irq_alarm;
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};
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#if IS_ENABLED(CONFIG_STMP3XXX_RTC_WATCHDOG)
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/**
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* stmp3xxx_wdt_set_timeout - configure the watchdog inside the STMP3xxx RTC
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* @dev: the parent device of the watchdog (= the RTC)
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* @timeout: the desired value for the timeout register of the watchdog.
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* 0 disables the watchdog
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*
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* The watchdog needs one register and two bits which are in the RTC domain.
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* To handle the resource conflict, the RTC driver will create another
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* platform_device for the watchdog driver as a child of the RTC device.
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* The watchdog driver is passed the below accessor function via platform_data
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* to configure the watchdog. Locking is not needed because accessing SET/CLR
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* registers is atomic.
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*/
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static void stmp3xxx_wdt_set_timeout(struct device *dev, u32 timeout)
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{
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struct stmp3xxx_rtc_data *rtc_data = dev_get_drvdata(dev);
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if (timeout) {
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writel(timeout, rtc_data->io + STMP3XXX_RTC_WATCHDOG);
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writel(STMP3XXX_RTC_CTRL_WATCHDOGEN,
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rtc_data->io + STMP3XXX_RTC_CTRL + STMP_OFFSET_REG_SET);
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writel(STMP3XXX_RTC_PERSISTENT1_FORCE_UPDATER,
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rtc_data->io + STMP3XXX_RTC_PERSISTENT1 + STMP_OFFSET_REG_SET);
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} else {
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writel(STMP3XXX_RTC_CTRL_WATCHDOGEN,
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rtc_data->io + STMP3XXX_RTC_CTRL + STMP_OFFSET_REG_CLR);
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writel(STMP3XXX_RTC_PERSISTENT1_FORCE_UPDATER,
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rtc_data->io + STMP3XXX_RTC_PERSISTENT1 + STMP_OFFSET_REG_CLR);
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}
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}
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static struct stmp3xxx_wdt_pdata wdt_pdata = {
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.wdt_set_timeout = stmp3xxx_wdt_set_timeout,
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};
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static void stmp3xxx_wdt_register(struct platform_device *rtc_pdev)
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{
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int rc = -1;
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struct platform_device *wdt_pdev =
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platform_device_alloc("stmp3xxx_rtc_wdt", rtc_pdev->id);
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if (wdt_pdev) {
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wdt_pdev->dev.parent = &rtc_pdev->dev;
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wdt_pdev->dev.platform_data = &wdt_pdata;
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rc = platform_device_add(wdt_pdev);
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}
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if (rc)
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dev_err(&rtc_pdev->dev,
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"failed to register stmp3xxx_rtc_wdt\n");
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}
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#else
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static void stmp3xxx_wdt_register(struct platform_device *rtc_pdev)
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{
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}
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#endif /* CONFIG_STMP3XXX_RTC_WATCHDOG */
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static int stmp3xxx_wait_time(struct stmp3xxx_rtc_data *rtc_data)
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{
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int timeout = 5000; /* 3ms according to i.MX28 Ref Manual */
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/*
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* The i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
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* states:
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* | The order in which registers are updated is
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* | Persistent 0, 1, 2, 3, 4, 5, Alarm, Seconds.
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* | (This list is in bitfield order, from LSB to MSB, as they would
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* | appear in the STALE_REGS and NEW_REGS bitfields of the HW_RTC_STAT
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* | register. For example, the Seconds register corresponds to
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* | STALE_REGS or NEW_REGS containing 0x80.)
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*/
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do {
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if (!(readl(rtc_data->io + STMP3XXX_RTC_STAT) &
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(0x80 << STMP3XXX_RTC_STAT_STALE_SHIFT)))
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return 0;
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udelay(1);
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} while (--timeout > 0);
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return (readl(rtc_data->io + STMP3XXX_RTC_STAT) &
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(0x80 << STMP3XXX_RTC_STAT_STALE_SHIFT)) ? -ETIME : 0;
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}
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/* Time read/write */
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static int stmp3xxx_rtc_gettime(struct device *dev, struct rtc_time *rtc_tm)
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{
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int ret;
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struct stmp3xxx_rtc_data *rtc_data = dev_get_drvdata(dev);
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ret = stmp3xxx_wait_time(rtc_data);
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if (ret)
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return ret;
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rtc_time_to_tm(readl(rtc_data->io + STMP3XXX_RTC_SECONDS), rtc_tm);
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return 0;
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}
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static int stmp3xxx_rtc_set_mmss(struct device *dev, unsigned long t)
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{
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struct stmp3xxx_rtc_data *rtc_data = dev_get_drvdata(dev);
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writel(t, rtc_data->io + STMP3XXX_RTC_SECONDS);
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return stmp3xxx_wait_time(rtc_data);
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}
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/* interrupt(s) handler */
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static irqreturn_t stmp3xxx_rtc_interrupt(int irq, void *dev_id)
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{
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struct stmp3xxx_rtc_data *rtc_data = dev_get_drvdata(dev_id);
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u32 status = readl(rtc_data->io + STMP3XXX_RTC_CTRL);
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if (status & STMP3XXX_RTC_CTRL_ALARM_IRQ) {
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writel(STMP3XXX_RTC_CTRL_ALARM_IRQ,
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rtc_data->io + STMP3XXX_RTC_CTRL + STMP_OFFSET_REG_CLR);
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rtc_update_irq(rtc_data->rtc, 1, RTC_AF | RTC_IRQF);
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return IRQ_HANDLED;
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}
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return IRQ_NONE;
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}
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static int stmp3xxx_alarm_irq_enable(struct device *dev, unsigned int enabled)
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{
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struct stmp3xxx_rtc_data *rtc_data = dev_get_drvdata(dev);
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if (enabled) {
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writel(STMP3XXX_RTC_PERSISTENT0_ALARM_EN |
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STMP3XXX_RTC_PERSISTENT0_ALARM_WAKE_EN,
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rtc_data->io + STMP3XXX_RTC_PERSISTENT0 +
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STMP_OFFSET_REG_SET);
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writel(STMP3XXX_RTC_CTRL_ALARM_IRQ_EN,
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rtc_data->io + STMP3XXX_RTC_CTRL + STMP_OFFSET_REG_SET);
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} else {
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writel(STMP3XXX_RTC_PERSISTENT0_ALARM_EN |
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STMP3XXX_RTC_PERSISTENT0_ALARM_WAKE_EN,
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rtc_data->io + STMP3XXX_RTC_PERSISTENT0 +
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STMP_OFFSET_REG_CLR);
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writel(STMP3XXX_RTC_CTRL_ALARM_IRQ_EN,
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rtc_data->io + STMP3XXX_RTC_CTRL + STMP_OFFSET_REG_CLR);
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}
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return 0;
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}
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static int stmp3xxx_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alm)
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{
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struct stmp3xxx_rtc_data *rtc_data = dev_get_drvdata(dev);
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rtc_time_to_tm(readl(rtc_data->io + STMP3XXX_RTC_ALARM), &alm->time);
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return 0;
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}
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static int stmp3xxx_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alm)
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{
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unsigned long t;
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struct stmp3xxx_rtc_data *rtc_data = dev_get_drvdata(dev);
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rtc_tm_to_time(&alm->time, &t);
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writel(t, rtc_data->io + STMP3XXX_RTC_ALARM);
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stmp3xxx_alarm_irq_enable(dev, alm->enabled);
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return 0;
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}
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static const struct rtc_class_ops stmp3xxx_rtc_ops = {
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.alarm_irq_enable =
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stmp3xxx_alarm_irq_enable,
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.read_time = stmp3xxx_rtc_gettime,
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.set_mmss = stmp3xxx_rtc_set_mmss,
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.read_alarm = stmp3xxx_rtc_read_alarm,
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.set_alarm = stmp3xxx_rtc_set_alarm,
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};
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static int stmp3xxx_rtc_remove(struct platform_device *pdev)
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{
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struct stmp3xxx_rtc_data *rtc_data = platform_get_drvdata(pdev);
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if (!rtc_data)
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return 0;
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writel(STMP3XXX_RTC_CTRL_ALARM_IRQ_EN,
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rtc_data->io + STMP3XXX_RTC_CTRL + STMP_OFFSET_REG_CLR);
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return 0;
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}
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static int stmp3xxx_rtc_probe(struct platform_device *pdev)
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{
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struct stmp3xxx_rtc_data *rtc_data;
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struct resource *r;
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u32 rtc_stat;
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u32 pers0_set, pers0_clr;
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u32 crystalfreq = 0;
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int err;
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rtc_data = devm_kzalloc(&pdev->dev, sizeof(*rtc_data), GFP_KERNEL);
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if (!rtc_data)
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return -ENOMEM;
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r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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if (!r) {
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dev_err(&pdev->dev, "failed to get resource\n");
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return -ENXIO;
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}
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rtc_data->io = devm_ioremap(&pdev->dev, r->start, resource_size(r));
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if (!rtc_data->io) {
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dev_err(&pdev->dev, "ioremap failed\n");
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return -EIO;
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}
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rtc_data->irq_alarm = platform_get_irq(pdev, 0);
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rtc_stat = readl(rtc_data->io + STMP3XXX_RTC_STAT);
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if (!(rtc_stat & STMP3XXX_RTC_STAT_RTC_PRESENT)) {
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dev_err(&pdev->dev, "no device onboard\n");
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return -ENODEV;
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}
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platform_set_drvdata(pdev, rtc_data);
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err = stmp_reset_block(rtc_data->io);
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if (err) {
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dev_err(&pdev->dev, "stmp_reset_block failed: %d\n", err);
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return err;
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}
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/*
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* Obviously the rtc needs a clock input to be able to run.
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* This clock can be provided by an external 32k crystal. If that one is
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* missing XTAL must not be disabled in suspend which consumes a
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* lot of power. Normally the presence and exact frequency (supported
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* are 32000 Hz and 32768 Hz) is detectable from fuses, but as reality
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* proves these fuses are not blown correctly on all machines, so the
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* frequency can be overridden in the device tree.
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*/
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if (rtc_stat & STMP3XXX_RTC_STAT_XTAL32000_PRESENT)
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crystalfreq = 32000;
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else if (rtc_stat & STMP3XXX_RTC_STAT_XTAL32768_PRESENT)
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crystalfreq = 32768;
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of_property_read_u32(pdev->dev.of_node, "stmp,crystal-freq",
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&crystalfreq);
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switch (crystalfreq) {
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case 32000:
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/* keep 32kHz crystal running in low-power mode */
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pers0_set = STMP3XXX_RTC_PERSISTENT0_XTAL32_FREQ |
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STMP3XXX_RTC_PERSISTENT0_XTAL32KHZ_PWRUP |
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STMP3XXX_RTC_PERSISTENT0_CLOCKSOURCE;
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pers0_clr = STMP3XXX_RTC_PERSISTENT0_XTAL24MHZ_PWRUP;
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break;
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case 32768:
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/* keep 32.768kHz crystal running in low-power mode */
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pers0_set = STMP3XXX_RTC_PERSISTENT0_XTAL32KHZ_PWRUP |
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STMP3XXX_RTC_PERSISTENT0_CLOCKSOURCE;
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pers0_clr = STMP3XXX_RTC_PERSISTENT0_XTAL24MHZ_PWRUP |
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STMP3XXX_RTC_PERSISTENT0_XTAL32_FREQ;
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break;
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default:
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dev_warn(&pdev->dev,
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"invalid crystal-freq specified in device-tree. Assuming no crystal\n");
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/* fall-through */
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case 0:
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/* keep XTAL on in low-power mode */
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pers0_set = STMP3XXX_RTC_PERSISTENT0_XTAL24MHZ_PWRUP;
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pers0_clr = STMP3XXX_RTC_PERSISTENT0_XTAL32KHZ_PWRUP |
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STMP3XXX_RTC_PERSISTENT0_CLOCKSOURCE;
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}
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writel(pers0_set, rtc_data->io + STMP3XXX_RTC_PERSISTENT0 +
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STMP_OFFSET_REG_SET);
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writel(STMP3XXX_RTC_PERSISTENT0_ALARM_EN |
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STMP3XXX_RTC_PERSISTENT0_ALARM_WAKE_EN |
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STMP3XXX_RTC_PERSISTENT0_ALARM_WAKE | pers0_clr,
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rtc_data->io + STMP3XXX_RTC_PERSISTENT0 + STMP_OFFSET_REG_CLR);
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writel(STMP3XXX_RTC_CTRL_ONEMSEC_IRQ_EN |
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STMP3XXX_RTC_CTRL_ALARM_IRQ_EN,
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rtc_data->io + STMP3XXX_RTC_CTRL + STMP_OFFSET_REG_CLR);
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rtc_data->rtc = devm_rtc_device_register(&pdev->dev, pdev->name,
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&stmp3xxx_rtc_ops, THIS_MODULE);
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if (IS_ERR(rtc_data->rtc))
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return PTR_ERR(rtc_data->rtc);
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err = devm_request_irq(&pdev->dev, rtc_data->irq_alarm,
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stmp3xxx_rtc_interrupt, 0, "RTC alarm", &pdev->dev);
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if (err) {
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dev_err(&pdev->dev, "Cannot claim IRQ%d\n",
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rtc_data->irq_alarm);
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return err;
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}
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stmp3xxx_wdt_register(pdev);
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return 0;
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}
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#ifdef CONFIG_PM_SLEEP
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static int stmp3xxx_rtc_suspend(struct device *dev)
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{
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return 0;
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}
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static int stmp3xxx_rtc_resume(struct device *dev)
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{
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struct stmp3xxx_rtc_data *rtc_data = dev_get_drvdata(dev);
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stmp_reset_block(rtc_data->io);
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writel(STMP3XXX_RTC_PERSISTENT0_ALARM_EN |
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STMP3XXX_RTC_PERSISTENT0_ALARM_WAKE_EN |
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STMP3XXX_RTC_PERSISTENT0_ALARM_WAKE,
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rtc_data->io + STMP3XXX_RTC_PERSISTENT0 + STMP_OFFSET_REG_CLR);
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return 0;
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}
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#endif
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static SIMPLE_DEV_PM_OPS(stmp3xxx_rtc_pm_ops, stmp3xxx_rtc_suspend,
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stmp3xxx_rtc_resume);
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static const struct of_device_id rtc_dt_ids[] = {
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{ .compatible = "fsl,stmp3xxx-rtc", },
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{ /* sentinel */ }
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};
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MODULE_DEVICE_TABLE(of, rtc_dt_ids);
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static struct platform_driver stmp3xxx_rtcdrv = {
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.probe = stmp3xxx_rtc_probe,
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.remove = stmp3xxx_rtc_remove,
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.driver = {
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.name = "stmp3xxx-rtc",
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.pm = &stmp3xxx_rtc_pm_ops,
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.of_match_table = rtc_dt_ids,
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},
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};
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module_platform_driver(stmp3xxx_rtcdrv);
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MODULE_DESCRIPTION("STMP3xxx RTC Driver");
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MODULE_AUTHOR("dmitry pervushin <dpervushin@embeddedalley.com> and "
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"Wolfram Sang <w.sang@pengutronix.de>");
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MODULE_LICENSE("GPL");
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