946 строки
25 KiB
C
946 строки
25 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Universal Host Controller Interface driver for USB.
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*
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* Maintainer: Alan Stern <stern@rowland.harvard.edu>
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*
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* (C) Copyright 1999 Linus Torvalds
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* (C) Copyright 1999-2002 Johannes Erdfelt, johannes@erdfelt.com
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* (C) Copyright 1999 Randy Dunlap
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* (C) Copyright 1999 Georg Acher, acher@in.tum.de
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* (C) Copyright 1999 Deti Fliegl, deti@fliegl.de
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* (C) Copyright 1999 Thomas Sailer, sailer@ife.ee.ethz.ch
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* (C) Copyright 1999 Roman Weissgaerber, weissg@vienna.at
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* (C) Copyright 2000 Yggdrasil Computing, Inc. (port of new PCI interface
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* support from usb-ohci.c by Adam Richter, adam@yggdrasil.com).
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* (C) Copyright 1999 Gregory P. Smith (from usb-ohci.c)
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* (C) Copyright 2004-2007 Alan Stern, stern@rowland.harvard.edu
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*
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* Intel documents this fairly well, and as far as I know there
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* are no royalties or anything like that, but even so there are
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* people who decided that they want to do the same thing in a
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* completely different way.
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*
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*/
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#include <linux/module.h>
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#include <linux/pci.h>
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/delay.h>
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#include <linux/ioport.h>
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#include <linux/slab.h>
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#include <linux/errno.h>
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#include <linux/unistd.h>
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#include <linux/interrupt.h>
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#include <linux/spinlock.h>
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#include <linux/debugfs.h>
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#include <linux/pm.h>
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#include <linux/dmapool.h>
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#include <linux/dma-mapping.h>
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#include <linux/usb.h>
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#include <linux/usb/hcd.h>
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#include <linux/bitops.h>
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#include <linux/dmi.h>
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#include <linux/uaccess.h>
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#include <asm/io.h>
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#include <asm/irq.h>
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#include "uhci-hcd.h"
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/*
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* Version Information
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*/
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#define DRIVER_AUTHOR \
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"Linus 'Frodo Rabbit' Torvalds, Johannes Erdfelt, " \
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"Randy Dunlap, Georg Acher, Deti Fliegl, Thomas Sailer, " \
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"Roman Weissgaerber, Alan Stern"
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#define DRIVER_DESC "USB Universal Host Controller Interface driver"
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/* for flakey hardware, ignore overcurrent indicators */
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static bool ignore_oc;
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module_param(ignore_oc, bool, S_IRUGO);
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MODULE_PARM_DESC(ignore_oc, "ignore hardware overcurrent indications");
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/*
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* debug = 0, no debugging messages
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* debug = 1, dump failed URBs except for stalls
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* debug = 2, dump all failed URBs (including stalls)
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* show all queues in /sys/kernel/debug/uhci/[pci_addr]
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* debug = 3, show all TDs in URBs when dumping
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*/
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#ifdef CONFIG_DYNAMIC_DEBUG
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static int debug = 1;
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module_param(debug, int, S_IRUGO | S_IWUSR);
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MODULE_PARM_DESC(debug, "Debug level");
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static char *errbuf;
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#else
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#define debug 0
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#define errbuf NULL
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#endif
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#define ERRBUF_LEN (32 * 1024)
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static struct kmem_cache *uhci_up_cachep; /* urb_priv */
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static void suspend_rh(struct uhci_hcd *uhci, enum uhci_rh_state new_state);
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static void wakeup_rh(struct uhci_hcd *uhci);
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static void uhci_get_current_frame_number(struct uhci_hcd *uhci);
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/*
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* Calculate the link pointer DMA value for the first Skeleton QH in a frame.
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*/
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static __hc32 uhci_frame_skel_link(struct uhci_hcd *uhci, int frame)
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{
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int skelnum;
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/*
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* The interrupt queues will be interleaved as evenly as possible.
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* There's not much to be done about period-1 interrupts; they have
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* to occur in every frame. But we can schedule period-2 interrupts
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* in odd-numbered frames, period-4 interrupts in frames congruent
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* to 2 (mod 4), and so on. This way each frame only has two
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* interrupt QHs, which will help spread out bandwidth utilization.
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*
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* ffs (Find First bit Set) does exactly what we need:
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* 1,3,5,... => ffs = 0 => use period-2 QH = skelqh[8],
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* 2,6,10,... => ffs = 1 => use period-4 QH = skelqh[7], etc.
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* ffs >= 7 => not on any high-period queue, so use
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* period-1 QH = skelqh[9].
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* Add in UHCI_NUMFRAMES to insure at least one bit is set.
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*/
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skelnum = 8 - (int) __ffs(frame | UHCI_NUMFRAMES);
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if (skelnum <= 1)
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skelnum = 9;
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return LINK_TO_QH(uhci, uhci->skelqh[skelnum]);
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}
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#include "uhci-debug.c"
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#include "uhci-q.c"
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#include "uhci-hub.c"
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/*
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* Finish up a host controller reset and update the recorded state.
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*/
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static void finish_reset(struct uhci_hcd *uhci)
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{
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int port;
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/* HCRESET doesn't affect the Suspend, Reset, and Resume Detect
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* bits in the port status and control registers.
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* We have to clear them by hand.
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*/
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for (port = 0; port < uhci->rh_numports; ++port)
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uhci_writew(uhci, 0, USBPORTSC1 + (port * 2));
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uhci->port_c_suspend = uhci->resuming_ports = 0;
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uhci->rh_state = UHCI_RH_RESET;
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uhci->is_stopped = UHCI_IS_STOPPED;
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clear_bit(HCD_FLAG_POLL_RH, &uhci_to_hcd(uhci)->flags);
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}
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/*
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* Last rites for a defunct/nonfunctional controller
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* or one we don't want to use any more.
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*/
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static void uhci_hc_died(struct uhci_hcd *uhci)
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{
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uhci_get_current_frame_number(uhci);
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uhci->reset_hc(uhci);
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finish_reset(uhci);
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uhci->dead = 1;
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/* The current frame may already be partway finished */
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++uhci->frame_number;
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}
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/*
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* Initialize a controller that was newly discovered or has lost power
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* or otherwise been reset while it was suspended. In none of these cases
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* can we be sure of its previous state.
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*/
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static void check_and_reset_hc(struct uhci_hcd *uhci)
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{
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if (uhci->check_and_reset_hc(uhci))
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finish_reset(uhci);
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}
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#if defined(CONFIG_USB_UHCI_SUPPORT_NON_PCI_HC)
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/*
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* The two functions below are generic reset functions that are used on systems
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* that do not have keyboard and mouse legacy support. We assume that we are
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* running on such a system if CONFIG_USB_UHCI_SUPPORT_NON_PCI_HC is defined.
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*/
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/*
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* Make sure the controller is completely inactive, unable to
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* generate interrupts or do DMA.
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*/
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static void uhci_generic_reset_hc(struct uhci_hcd *uhci)
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{
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/* Reset the HC - this will force us to get a
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* new notification of any already connected
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* ports due to the virtual disconnect that it
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* implies.
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*/
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uhci_writew(uhci, USBCMD_HCRESET, USBCMD);
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mb();
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udelay(5);
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if (uhci_readw(uhci, USBCMD) & USBCMD_HCRESET)
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dev_warn(uhci_dev(uhci), "HCRESET not completed yet!\n");
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/* Just to be safe, disable interrupt requests and
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* make sure the controller is stopped.
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*/
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uhci_writew(uhci, 0, USBINTR);
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uhci_writew(uhci, 0, USBCMD);
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}
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/*
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* Initialize a controller that was newly discovered or has just been
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* resumed. In either case we can't be sure of its previous state.
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*
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* Returns: 1 if the controller was reset, 0 otherwise.
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*/
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static int uhci_generic_check_and_reset_hc(struct uhci_hcd *uhci)
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{
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unsigned int cmd, intr;
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/*
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* When restarting a suspended controller, we expect all the
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* settings to be the same as we left them:
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*
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* Controller is stopped and configured with EGSM set;
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* No interrupts enabled except possibly Resume Detect.
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*
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* If any of these conditions are violated we do a complete reset.
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*/
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cmd = uhci_readw(uhci, USBCMD);
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if ((cmd & USBCMD_RS) || !(cmd & USBCMD_CF) || !(cmd & USBCMD_EGSM)) {
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dev_dbg(uhci_dev(uhci), "%s: cmd = 0x%04x\n",
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__func__, cmd);
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goto reset_needed;
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}
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intr = uhci_readw(uhci, USBINTR);
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if (intr & (~USBINTR_RESUME)) {
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dev_dbg(uhci_dev(uhci), "%s: intr = 0x%04x\n",
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__func__, intr);
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goto reset_needed;
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}
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return 0;
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reset_needed:
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dev_dbg(uhci_dev(uhci), "Performing full reset\n");
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uhci_generic_reset_hc(uhci);
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return 1;
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}
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#endif /* CONFIG_USB_UHCI_SUPPORT_NON_PCI_HC */
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/*
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* Store the basic register settings needed by the controller.
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*/
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static void configure_hc(struct uhci_hcd *uhci)
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{
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/* Set the frame length to the default: 1 ms exactly */
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uhci_writeb(uhci, USBSOF_DEFAULT, USBSOF);
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/* Store the frame list base address */
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uhci_writel(uhci, uhci->frame_dma_handle, USBFLBASEADD);
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/* Set the current frame number */
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uhci_writew(uhci, uhci->frame_number & UHCI_MAX_SOF_NUMBER,
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USBFRNUM);
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/* perform any arch/bus specific configuration */
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if (uhci->configure_hc)
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uhci->configure_hc(uhci);
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}
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static int resume_detect_interrupts_are_broken(struct uhci_hcd *uhci)
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{
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/*
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* If we have to ignore overcurrent events then almost by definition
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* we can't depend on resume-detect interrupts.
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*
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* Those interrupts also don't seem to work on ASpeed SoCs.
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*/
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if (ignore_oc || uhci_is_aspeed(uhci))
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return 1;
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return uhci->resume_detect_interrupts_are_broken ?
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uhci->resume_detect_interrupts_are_broken(uhci) : 0;
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}
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static int global_suspend_mode_is_broken(struct uhci_hcd *uhci)
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{
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return uhci->global_suspend_mode_is_broken ?
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uhci->global_suspend_mode_is_broken(uhci) : 0;
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}
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static void suspend_rh(struct uhci_hcd *uhci, enum uhci_rh_state new_state)
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__releases(uhci->lock)
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__acquires(uhci->lock)
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{
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int auto_stop;
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int int_enable, egsm_enable, wakeup_enable;
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struct usb_device *rhdev = uhci_to_hcd(uhci)->self.root_hub;
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auto_stop = (new_state == UHCI_RH_AUTO_STOPPED);
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dev_dbg(&rhdev->dev, "%s%s\n", __func__,
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(auto_stop ? " (auto-stop)" : ""));
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/* Start off by assuming Resume-Detect interrupts and EGSM work
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* and that remote wakeups should be enabled.
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*/
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egsm_enable = USBCMD_EGSM;
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int_enable = USBINTR_RESUME;
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wakeup_enable = 1;
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/*
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* In auto-stop mode, we must be able to detect new connections.
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* The user can force us to poll by disabling remote wakeup;
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* otherwise we will use the EGSM/RD mechanism.
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*/
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if (auto_stop) {
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if (!device_may_wakeup(&rhdev->dev))
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egsm_enable = int_enable = 0;
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}
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#ifdef CONFIG_PM
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/*
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* In bus-suspend mode, we use the wakeup setting specified
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* for the root hub.
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*/
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else {
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if (!rhdev->do_remote_wakeup)
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wakeup_enable = 0;
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}
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#endif
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/*
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* UHCI doesn't distinguish between wakeup requests from downstream
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* devices and local connect/disconnect events. There's no way to
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* enable one without the other; both are controlled by EGSM. Thus
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* if wakeups are disallowed then EGSM must be turned off -- in which
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* case remote wakeup requests from downstream during system sleep
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* will be lost.
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*
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* In addition, if EGSM is broken then we can't use it. Likewise,
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* if Resume-Detect interrupts are broken then we can't use them.
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*
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* Finally, neither EGSM nor RD is useful by itself. Without EGSM,
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* the RD status bit will never get set. Without RD, the controller
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* won't generate interrupts to tell the system about wakeup events.
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*/
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if (!wakeup_enable || global_suspend_mode_is_broken(uhci) ||
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resume_detect_interrupts_are_broken(uhci))
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egsm_enable = int_enable = 0;
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uhci->RD_enable = !!int_enable;
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uhci_writew(uhci, int_enable, USBINTR);
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uhci_writew(uhci, egsm_enable | USBCMD_CF, USBCMD);
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mb();
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udelay(5);
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/* If we're auto-stopping then no devices have been attached
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* for a while, so there shouldn't be any active URBs and the
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* controller should stop after a few microseconds. Otherwise
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* we will give the controller one frame to stop.
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*/
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if (!auto_stop && !(uhci_readw(uhci, USBSTS) & USBSTS_HCH)) {
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uhci->rh_state = UHCI_RH_SUSPENDING;
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spin_unlock_irq(&uhci->lock);
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msleep(1);
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spin_lock_irq(&uhci->lock);
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if (uhci->dead)
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return;
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}
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if (!(uhci_readw(uhci, USBSTS) & USBSTS_HCH))
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dev_warn(uhci_dev(uhci), "Controller not stopped yet!\n");
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uhci_get_current_frame_number(uhci);
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uhci->rh_state = new_state;
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uhci->is_stopped = UHCI_IS_STOPPED;
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/*
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* If remote wakeup is enabled but either EGSM or RD interrupts
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* doesn't work, then we won't get an interrupt when a wakeup event
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* occurs. Thus the suspended root hub needs to be polled.
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*/
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if (wakeup_enable && (!int_enable || !egsm_enable))
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set_bit(HCD_FLAG_POLL_RH, &uhci_to_hcd(uhci)->flags);
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else
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clear_bit(HCD_FLAG_POLL_RH, &uhci_to_hcd(uhci)->flags);
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uhci_scan_schedule(uhci);
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uhci_fsbr_off(uhci);
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}
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static void start_rh(struct uhci_hcd *uhci)
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{
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uhci->is_stopped = 0;
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/*
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* Clear stale status bits on Aspeed as we get a stale HCH
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* which causes problems later on
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*/
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if (uhci_is_aspeed(uhci))
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uhci_writew(uhci, uhci_readw(uhci, USBSTS), USBSTS);
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/* Mark it configured and running with a 64-byte max packet.
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* All interrupts are enabled, even though RESUME won't do anything.
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*/
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uhci_writew(uhci, USBCMD_RS | USBCMD_CF | USBCMD_MAXP, USBCMD);
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uhci_writew(uhci, USBINTR_TIMEOUT | USBINTR_RESUME |
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USBINTR_IOC | USBINTR_SP, USBINTR);
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mb();
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uhci->rh_state = UHCI_RH_RUNNING;
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set_bit(HCD_FLAG_POLL_RH, &uhci_to_hcd(uhci)->flags);
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}
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static void wakeup_rh(struct uhci_hcd *uhci)
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__releases(uhci->lock)
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__acquires(uhci->lock)
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{
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dev_dbg(&uhci_to_hcd(uhci)->self.root_hub->dev,
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"%s%s\n", __func__,
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uhci->rh_state == UHCI_RH_AUTO_STOPPED ?
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" (auto-start)" : "");
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/* If we are auto-stopped then no devices are attached so there's
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* no need for wakeup signals. Otherwise we send Global Resume
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* for 20 ms.
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*/
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if (uhci->rh_state == UHCI_RH_SUSPENDED) {
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unsigned egsm;
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/* Keep EGSM on if it was set before */
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egsm = uhci_readw(uhci, USBCMD) & USBCMD_EGSM;
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uhci->rh_state = UHCI_RH_RESUMING;
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uhci_writew(uhci, USBCMD_FGR | USBCMD_CF | egsm, USBCMD);
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spin_unlock_irq(&uhci->lock);
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msleep(20);
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spin_lock_irq(&uhci->lock);
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if (uhci->dead)
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return;
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/* End Global Resume and wait for EOP to be sent */
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uhci_writew(uhci, USBCMD_CF, USBCMD);
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mb();
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udelay(4);
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if (uhci_readw(uhci, USBCMD) & USBCMD_FGR)
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dev_warn(uhci_dev(uhci), "FGR not stopped yet!\n");
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}
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start_rh(uhci);
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/* Restart root hub polling */
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mod_timer(&uhci_to_hcd(uhci)->rh_timer, jiffies);
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}
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static irqreturn_t uhci_irq(struct usb_hcd *hcd)
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{
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struct uhci_hcd *uhci = hcd_to_uhci(hcd);
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unsigned short status;
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/*
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* Read the interrupt status, and write it back to clear the
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* interrupt cause. Contrary to the UHCI specification, the
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* "HC Halted" status bit is persistent: it is RO, not R/WC.
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*/
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status = uhci_readw(uhci, USBSTS);
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if (!(status & ~USBSTS_HCH)) /* shared interrupt, not mine */
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return IRQ_NONE;
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uhci_writew(uhci, status, USBSTS); /* Clear it */
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spin_lock(&uhci->lock);
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if (unlikely(!uhci->is_initialized)) /* not yet configured */
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goto done;
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if (status & ~(USBSTS_USBINT | USBSTS_ERROR | USBSTS_RD)) {
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if (status & USBSTS_HSE)
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dev_err(uhci_dev(uhci),
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"host system error, PCI problems?\n");
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if (status & USBSTS_HCPE)
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dev_err(uhci_dev(uhci),
|
|
"host controller process error, something bad happened!\n");
|
|
if (status & USBSTS_HCH) {
|
|
if (uhci->rh_state >= UHCI_RH_RUNNING) {
|
|
dev_err(uhci_dev(uhci),
|
|
"host controller halted, very bad!\n");
|
|
if (debug > 1 && errbuf) {
|
|
/* Print the schedule for debugging */
|
|
uhci_sprint_schedule(uhci, errbuf,
|
|
ERRBUF_LEN - EXTRA_SPACE);
|
|
lprintk(errbuf);
|
|
}
|
|
uhci_hc_died(uhci);
|
|
usb_hc_died(hcd);
|
|
|
|
/* Force a callback in case there are
|
|
* pending unlinks */
|
|
mod_timer(&hcd->rh_timer, jiffies);
|
|
}
|
|
}
|
|
}
|
|
|
|
if (status & USBSTS_RD) {
|
|
spin_unlock(&uhci->lock);
|
|
usb_hcd_poll_rh_status(hcd);
|
|
} else {
|
|
uhci_scan_schedule(uhci);
|
|
done:
|
|
spin_unlock(&uhci->lock);
|
|
}
|
|
|
|
return IRQ_HANDLED;
|
|
}
|
|
|
|
/*
|
|
* Store the current frame number in uhci->frame_number if the controller
|
|
* is running. Expand from 11 bits (of which we use only 10) to a
|
|
* full-sized integer.
|
|
*
|
|
* Like many other parts of the driver, this code relies on being polled
|
|
* more than once per second as long as the controller is running.
|
|
*/
|
|
static void uhci_get_current_frame_number(struct uhci_hcd *uhci)
|
|
{
|
|
if (!uhci->is_stopped) {
|
|
unsigned delta;
|
|
|
|
delta = (uhci_readw(uhci, USBFRNUM) - uhci->frame_number) &
|
|
(UHCI_NUMFRAMES - 1);
|
|
uhci->frame_number += delta;
|
|
}
|
|
}
|
|
|
|
/*
|
|
* De-allocate all resources
|
|
*/
|
|
static void release_uhci(struct uhci_hcd *uhci)
|
|
{
|
|
int i;
|
|
|
|
|
|
spin_lock_irq(&uhci->lock);
|
|
uhci->is_initialized = 0;
|
|
spin_unlock_irq(&uhci->lock);
|
|
|
|
debugfs_remove(uhci->dentry);
|
|
|
|
for (i = 0; i < UHCI_NUM_SKELQH; i++)
|
|
uhci_free_qh(uhci, uhci->skelqh[i]);
|
|
|
|
uhci_free_td(uhci, uhci->term_td);
|
|
|
|
dma_pool_destroy(uhci->qh_pool);
|
|
|
|
dma_pool_destroy(uhci->td_pool);
|
|
|
|
kfree(uhci->frame_cpu);
|
|
|
|
dma_free_coherent(uhci_dev(uhci),
|
|
UHCI_NUMFRAMES * sizeof(*uhci->frame),
|
|
uhci->frame, uhci->frame_dma_handle);
|
|
}
|
|
|
|
/*
|
|
* Allocate a frame list, and then setup the skeleton
|
|
*
|
|
* The hardware doesn't really know any difference
|
|
* in the queues, but the order does matter for the
|
|
* protocols higher up. The order in which the queues
|
|
* are encountered by the hardware is:
|
|
*
|
|
* - All isochronous events are handled before any
|
|
* of the queues. We don't do that here, because
|
|
* we'll create the actual TD entries on demand.
|
|
* - The first queue is the high-period interrupt queue.
|
|
* - The second queue is the period-1 interrupt and async
|
|
* (low-speed control, full-speed control, then bulk) queue.
|
|
* - The third queue is the terminating bandwidth reclamation queue,
|
|
* which contains no members, loops back to itself, and is present
|
|
* only when FSBR is on and there are no full-speed control or bulk QHs.
|
|
*/
|
|
static int uhci_start(struct usb_hcd *hcd)
|
|
{
|
|
struct uhci_hcd *uhci = hcd_to_uhci(hcd);
|
|
int retval = -EBUSY;
|
|
int i;
|
|
struct dentry __maybe_unused *dentry;
|
|
|
|
hcd->uses_new_polling = 1;
|
|
/* Accept arbitrarily long scatter-gather lists */
|
|
if (!(hcd->driver->flags & HCD_LOCAL_MEM))
|
|
hcd->self.sg_tablesize = ~0;
|
|
|
|
spin_lock_init(&uhci->lock);
|
|
timer_setup(&uhci->fsbr_timer, uhci_fsbr_timeout, 0);
|
|
INIT_LIST_HEAD(&uhci->idle_qh_list);
|
|
init_waitqueue_head(&uhci->waitqh);
|
|
|
|
#ifdef UHCI_DEBUG_OPS
|
|
uhci->dentry = debugfs_create_file(hcd->self.bus_name,
|
|
S_IFREG|S_IRUGO|S_IWUSR,
|
|
uhci_debugfs_root, uhci,
|
|
&uhci_debug_operations);
|
|
#endif
|
|
|
|
uhci->frame = dma_alloc_coherent(uhci_dev(uhci),
|
|
UHCI_NUMFRAMES * sizeof(*uhci->frame),
|
|
&uhci->frame_dma_handle, GFP_KERNEL);
|
|
if (!uhci->frame) {
|
|
dev_err(uhci_dev(uhci),
|
|
"unable to allocate consistent memory for frame list\n");
|
|
goto err_alloc_frame;
|
|
}
|
|
|
|
uhci->frame_cpu = kcalloc(UHCI_NUMFRAMES, sizeof(*uhci->frame_cpu),
|
|
GFP_KERNEL);
|
|
if (!uhci->frame_cpu)
|
|
goto err_alloc_frame_cpu;
|
|
|
|
uhci->td_pool = dma_pool_create("uhci_td", uhci_dev(uhci),
|
|
sizeof(struct uhci_td), 16, 0);
|
|
if (!uhci->td_pool) {
|
|
dev_err(uhci_dev(uhci), "unable to create td dma_pool\n");
|
|
goto err_create_td_pool;
|
|
}
|
|
|
|
uhci->qh_pool = dma_pool_create("uhci_qh", uhci_dev(uhci),
|
|
sizeof(struct uhci_qh), 16, 0);
|
|
if (!uhci->qh_pool) {
|
|
dev_err(uhci_dev(uhci), "unable to create qh dma_pool\n");
|
|
goto err_create_qh_pool;
|
|
}
|
|
|
|
uhci->term_td = uhci_alloc_td(uhci);
|
|
if (!uhci->term_td) {
|
|
dev_err(uhci_dev(uhci), "unable to allocate terminating TD\n");
|
|
goto err_alloc_term_td;
|
|
}
|
|
|
|
for (i = 0; i < UHCI_NUM_SKELQH; i++) {
|
|
uhci->skelqh[i] = uhci_alloc_qh(uhci, NULL, NULL);
|
|
if (!uhci->skelqh[i]) {
|
|
dev_err(uhci_dev(uhci), "unable to allocate QH\n");
|
|
goto err_alloc_skelqh;
|
|
}
|
|
}
|
|
|
|
/*
|
|
* 8 Interrupt queues; link all higher int queues to int1 = async
|
|
*/
|
|
for (i = SKEL_ISO + 1; i < SKEL_ASYNC; ++i)
|
|
uhci->skelqh[i]->link = LINK_TO_QH(uhci, uhci->skel_async_qh);
|
|
uhci->skel_async_qh->link = UHCI_PTR_TERM(uhci);
|
|
uhci->skel_term_qh->link = LINK_TO_QH(uhci, uhci->skel_term_qh);
|
|
|
|
/* This dummy TD is to work around a bug in Intel PIIX controllers */
|
|
uhci_fill_td(uhci, uhci->term_td, 0, uhci_explen(0) |
|
|
(0x7f << TD_TOKEN_DEVADDR_SHIFT) | USB_PID_IN, 0);
|
|
uhci->term_td->link = UHCI_PTR_TERM(uhci);
|
|
uhci->skel_async_qh->element = uhci->skel_term_qh->element =
|
|
LINK_TO_TD(uhci, uhci->term_td);
|
|
|
|
/*
|
|
* Fill the frame list: make all entries point to the proper
|
|
* interrupt queue.
|
|
*/
|
|
for (i = 0; i < UHCI_NUMFRAMES; i++) {
|
|
|
|
/* Only place we don't use the frame list routines */
|
|
uhci->frame[i] = uhci_frame_skel_link(uhci, i);
|
|
}
|
|
|
|
/*
|
|
* Some architectures require a full mb() to enforce completion of
|
|
* the memory writes above before the I/O transfers in configure_hc().
|
|
*/
|
|
mb();
|
|
|
|
spin_lock_irq(&uhci->lock);
|
|
configure_hc(uhci);
|
|
uhci->is_initialized = 1;
|
|
start_rh(uhci);
|
|
spin_unlock_irq(&uhci->lock);
|
|
return 0;
|
|
|
|
/*
|
|
* error exits:
|
|
*/
|
|
err_alloc_skelqh:
|
|
for (i = 0; i < UHCI_NUM_SKELQH; i++) {
|
|
if (uhci->skelqh[i])
|
|
uhci_free_qh(uhci, uhci->skelqh[i]);
|
|
}
|
|
|
|
uhci_free_td(uhci, uhci->term_td);
|
|
|
|
err_alloc_term_td:
|
|
dma_pool_destroy(uhci->qh_pool);
|
|
|
|
err_create_qh_pool:
|
|
dma_pool_destroy(uhci->td_pool);
|
|
|
|
err_create_td_pool:
|
|
kfree(uhci->frame_cpu);
|
|
|
|
err_alloc_frame_cpu:
|
|
dma_free_coherent(uhci_dev(uhci),
|
|
UHCI_NUMFRAMES * sizeof(*uhci->frame),
|
|
uhci->frame, uhci->frame_dma_handle);
|
|
|
|
err_alloc_frame:
|
|
debugfs_remove(uhci->dentry);
|
|
|
|
return retval;
|
|
}
|
|
|
|
static void uhci_stop(struct usb_hcd *hcd)
|
|
{
|
|
struct uhci_hcd *uhci = hcd_to_uhci(hcd);
|
|
|
|
spin_lock_irq(&uhci->lock);
|
|
if (HCD_HW_ACCESSIBLE(hcd) && !uhci->dead)
|
|
uhci_hc_died(uhci);
|
|
uhci_scan_schedule(uhci);
|
|
spin_unlock_irq(&uhci->lock);
|
|
synchronize_irq(hcd->irq);
|
|
|
|
del_timer_sync(&uhci->fsbr_timer);
|
|
release_uhci(uhci);
|
|
}
|
|
|
|
#ifdef CONFIG_PM
|
|
static int uhci_rh_suspend(struct usb_hcd *hcd)
|
|
{
|
|
struct uhci_hcd *uhci = hcd_to_uhci(hcd);
|
|
int rc = 0;
|
|
|
|
spin_lock_irq(&uhci->lock);
|
|
if (!HCD_HW_ACCESSIBLE(hcd))
|
|
rc = -ESHUTDOWN;
|
|
else if (uhci->dead)
|
|
; /* Dead controllers tell no tales */
|
|
|
|
/* Once the controller is stopped, port resumes that are already
|
|
* in progress won't complete. Hence if remote wakeup is enabled
|
|
* for the root hub and any ports are in the middle of a resume or
|
|
* remote wakeup, we must fail the suspend.
|
|
*/
|
|
else if (hcd->self.root_hub->do_remote_wakeup &&
|
|
uhci->resuming_ports) {
|
|
dev_dbg(uhci_dev(uhci),
|
|
"suspend failed because a port is resuming\n");
|
|
rc = -EBUSY;
|
|
} else
|
|
suspend_rh(uhci, UHCI_RH_SUSPENDED);
|
|
spin_unlock_irq(&uhci->lock);
|
|
return rc;
|
|
}
|
|
|
|
static int uhci_rh_resume(struct usb_hcd *hcd)
|
|
{
|
|
struct uhci_hcd *uhci = hcd_to_uhci(hcd);
|
|
int rc = 0;
|
|
|
|
spin_lock_irq(&uhci->lock);
|
|
if (!HCD_HW_ACCESSIBLE(hcd))
|
|
rc = -ESHUTDOWN;
|
|
else if (!uhci->dead)
|
|
wakeup_rh(uhci);
|
|
spin_unlock_irq(&uhci->lock);
|
|
return rc;
|
|
}
|
|
|
|
#endif
|
|
|
|
/* Wait until a particular device/endpoint's QH is idle, and free it */
|
|
static void uhci_hcd_endpoint_disable(struct usb_hcd *hcd,
|
|
struct usb_host_endpoint *hep)
|
|
{
|
|
struct uhci_hcd *uhci = hcd_to_uhci(hcd);
|
|
struct uhci_qh *qh;
|
|
|
|
spin_lock_irq(&uhci->lock);
|
|
qh = (struct uhci_qh *) hep->hcpriv;
|
|
if (qh == NULL)
|
|
goto done;
|
|
|
|
while (qh->state != QH_STATE_IDLE) {
|
|
++uhci->num_waiting;
|
|
spin_unlock_irq(&uhci->lock);
|
|
wait_event_interruptible(uhci->waitqh,
|
|
qh->state == QH_STATE_IDLE);
|
|
spin_lock_irq(&uhci->lock);
|
|
--uhci->num_waiting;
|
|
}
|
|
|
|
uhci_free_qh(uhci, qh);
|
|
done:
|
|
spin_unlock_irq(&uhci->lock);
|
|
}
|
|
|
|
static int uhci_hcd_get_frame_number(struct usb_hcd *hcd)
|
|
{
|
|
struct uhci_hcd *uhci = hcd_to_uhci(hcd);
|
|
unsigned frame_number;
|
|
unsigned delta;
|
|
|
|
/* Minimize latency by avoiding the spinlock */
|
|
frame_number = uhci->frame_number;
|
|
barrier();
|
|
delta = (uhci_readw(uhci, USBFRNUM) - frame_number) &
|
|
(UHCI_NUMFRAMES - 1);
|
|
return frame_number + delta;
|
|
}
|
|
|
|
/* Determines number of ports on controller */
|
|
static int uhci_count_ports(struct usb_hcd *hcd)
|
|
{
|
|
struct uhci_hcd *uhci = hcd_to_uhci(hcd);
|
|
unsigned io_size = (unsigned) hcd->rsrc_len;
|
|
int port;
|
|
|
|
/* The UHCI spec says devices must have 2 ports, and goes on to say
|
|
* they may have more but gives no way to determine how many there
|
|
* are. However according to the UHCI spec, Bit 7 of the port
|
|
* status and control register is always set to 1. So we try to
|
|
* use this to our advantage. Another common failure mode when
|
|
* a nonexistent register is addressed is to return all ones, so
|
|
* we test for that also.
|
|
*/
|
|
for (port = 0; port < (io_size - USBPORTSC1) / 2; port++) {
|
|
unsigned int portstatus;
|
|
|
|
portstatus = uhci_readw(uhci, USBPORTSC1 + (port * 2));
|
|
if (!(portstatus & 0x0080) || portstatus == 0xffff)
|
|
break;
|
|
}
|
|
if (debug)
|
|
dev_info(uhci_dev(uhci), "detected %d ports\n", port);
|
|
|
|
/* Anything greater than 7 is weird so we'll ignore it. */
|
|
if (port > UHCI_RH_MAXCHILD) {
|
|
dev_info(uhci_dev(uhci),
|
|
"port count misdetected? forcing to 2 ports\n");
|
|
port = 2;
|
|
}
|
|
|
|
return port;
|
|
}
|
|
|
|
static const char hcd_name[] = "uhci_hcd";
|
|
|
|
#ifdef CONFIG_USB_PCI
|
|
#include "uhci-pci.c"
|
|
#define PCI_DRIVER uhci_pci_driver
|
|
#endif
|
|
|
|
#ifdef CONFIG_SPARC_LEON
|
|
#include "uhci-grlib.c"
|
|
#define PLATFORM_DRIVER uhci_grlib_driver
|
|
#endif
|
|
|
|
#ifdef CONFIG_USB_UHCI_PLATFORM
|
|
#include "uhci-platform.c"
|
|
#define PLATFORM_DRIVER uhci_platform_driver
|
|
#endif
|
|
|
|
#if !defined(PCI_DRIVER) && !defined(PLATFORM_DRIVER)
|
|
#error "missing bus glue for uhci-hcd"
|
|
#endif
|
|
|
|
static int __init uhci_hcd_init(void)
|
|
{
|
|
int retval = -ENOMEM;
|
|
|
|
if (usb_disabled())
|
|
return -ENODEV;
|
|
|
|
printk(KERN_INFO "uhci_hcd: " DRIVER_DESC "%s\n",
|
|
ignore_oc ? ", overcurrent ignored" : "");
|
|
set_bit(USB_UHCI_LOADED, &usb_hcds_loaded);
|
|
|
|
#ifdef CONFIG_DYNAMIC_DEBUG
|
|
errbuf = kmalloc(ERRBUF_LEN, GFP_KERNEL);
|
|
if (!errbuf)
|
|
goto errbuf_failed;
|
|
uhci_debugfs_root = debugfs_create_dir("uhci", usb_debug_root);
|
|
#endif
|
|
|
|
uhci_up_cachep = kmem_cache_create("uhci_urb_priv",
|
|
sizeof(struct urb_priv), 0, 0, NULL);
|
|
if (!uhci_up_cachep)
|
|
goto up_failed;
|
|
|
|
#ifdef PLATFORM_DRIVER
|
|
retval = platform_driver_register(&PLATFORM_DRIVER);
|
|
if (retval < 0)
|
|
goto clean0;
|
|
#endif
|
|
|
|
#ifdef PCI_DRIVER
|
|
retval = pci_register_driver(&PCI_DRIVER);
|
|
if (retval < 0)
|
|
goto clean1;
|
|
#endif
|
|
|
|
return 0;
|
|
|
|
#ifdef PCI_DRIVER
|
|
clean1:
|
|
#endif
|
|
#ifdef PLATFORM_DRIVER
|
|
platform_driver_unregister(&PLATFORM_DRIVER);
|
|
clean0:
|
|
#endif
|
|
kmem_cache_destroy(uhci_up_cachep);
|
|
|
|
up_failed:
|
|
#if defined(DEBUG) || defined(CONFIG_DYNAMIC_DEBUG)
|
|
debugfs_remove(uhci_debugfs_root);
|
|
|
|
kfree(errbuf);
|
|
|
|
errbuf_failed:
|
|
#endif
|
|
|
|
clear_bit(USB_UHCI_LOADED, &usb_hcds_loaded);
|
|
return retval;
|
|
}
|
|
|
|
static void __exit uhci_hcd_cleanup(void)
|
|
{
|
|
#ifdef PLATFORM_DRIVER
|
|
platform_driver_unregister(&PLATFORM_DRIVER);
|
|
#endif
|
|
#ifdef PCI_DRIVER
|
|
pci_unregister_driver(&PCI_DRIVER);
|
|
#endif
|
|
kmem_cache_destroy(uhci_up_cachep);
|
|
debugfs_remove(uhci_debugfs_root);
|
|
#ifdef CONFIG_DYNAMIC_DEBUG
|
|
kfree(errbuf);
|
|
#endif
|
|
clear_bit(USB_UHCI_LOADED, &usb_hcds_loaded);
|
|
}
|
|
|
|
module_init(uhci_hcd_init);
|
|
module_exit(uhci_hcd_cleanup);
|
|
|
|
MODULE_AUTHOR(DRIVER_AUTHOR);
|
|
MODULE_DESCRIPTION(DRIVER_DESC);
|
|
MODULE_LICENSE("GPL");
|