770 строки
19 KiB
C
770 строки
19 KiB
C
/*
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* Rockchip Generic power domain support.
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*
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* Copyright (c) 2015 ROCKCHIP, Co. Ltd.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/io.h>
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#include <linux/err.h>
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#include <linux/pm_clock.h>
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#include <linux/pm_domain.h>
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#include <linux/of_address.h>
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#include <linux/of_platform.h>
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#include <linux/clk.h>
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#include <linux/regmap.h>
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#include <linux/mfd/syscon.h>
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#include <dt-bindings/power/rk3288-power.h>
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#include <dt-bindings/power/rk3368-power.h>
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#include <dt-bindings/power/rk3399-power.h>
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struct rockchip_domain_info {
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int pwr_mask;
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int status_mask;
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int req_mask;
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int idle_mask;
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int ack_mask;
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bool active_wakeup;
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};
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struct rockchip_pmu_info {
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u32 pwr_offset;
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u32 status_offset;
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u32 req_offset;
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u32 idle_offset;
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u32 ack_offset;
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u32 core_pwrcnt_offset;
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u32 gpu_pwrcnt_offset;
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unsigned int core_power_transition_time;
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unsigned int gpu_power_transition_time;
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int num_domains;
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const struct rockchip_domain_info *domain_info;
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};
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#define MAX_QOS_REGS_NUM 5
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#define QOS_PRIORITY 0x08
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#define QOS_MODE 0x0c
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#define QOS_BANDWIDTH 0x10
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#define QOS_SATURATION 0x14
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#define QOS_EXTCONTROL 0x18
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struct rockchip_pm_domain {
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struct generic_pm_domain genpd;
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const struct rockchip_domain_info *info;
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struct rockchip_pmu *pmu;
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int num_qos;
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struct regmap **qos_regmap;
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u32 *qos_save_regs[MAX_QOS_REGS_NUM];
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int num_clks;
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struct clk *clks[];
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};
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struct rockchip_pmu {
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struct device *dev;
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struct regmap *regmap;
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const struct rockchip_pmu_info *info;
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struct mutex mutex; /* mutex lock for pmu */
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struct genpd_onecell_data genpd_data;
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struct generic_pm_domain *domains[];
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};
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#define to_rockchip_pd(gpd) container_of(gpd, struct rockchip_pm_domain, genpd)
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#define DOMAIN(pwr, status, req, idle, ack, wakeup) \
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{ \
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.pwr_mask = (pwr >= 0) ? BIT(pwr) : 0, \
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.status_mask = (status >= 0) ? BIT(status) : 0, \
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.req_mask = (req >= 0) ? BIT(req) : 0, \
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.idle_mask = (idle >= 0) ? BIT(idle) : 0, \
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.ack_mask = (ack >= 0) ? BIT(ack) : 0, \
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.active_wakeup = wakeup, \
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}
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#define DOMAIN_RK3288(pwr, status, req, wakeup) \
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DOMAIN(pwr, status, req, req, (req) + 16, wakeup)
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#define DOMAIN_RK3368(pwr, status, req, wakeup) \
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DOMAIN(pwr, status, req, (req) + 16, req, wakeup)
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#define DOMAIN_RK3399(pwr, status, req, wakeup) \
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DOMAIN(pwr, status, req, req, req, wakeup)
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static bool rockchip_pmu_domain_is_idle(struct rockchip_pm_domain *pd)
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{
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struct rockchip_pmu *pmu = pd->pmu;
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const struct rockchip_domain_info *pd_info = pd->info;
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unsigned int val;
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regmap_read(pmu->regmap, pmu->info->idle_offset, &val);
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return (val & pd_info->idle_mask) == pd_info->idle_mask;
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}
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static int rockchip_pmu_set_idle_request(struct rockchip_pm_domain *pd,
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bool idle)
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{
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const struct rockchip_domain_info *pd_info = pd->info;
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struct rockchip_pmu *pmu = pd->pmu;
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unsigned int val;
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if (pd_info->req_mask == 0)
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return 0;
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regmap_update_bits(pmu->regmap, pmu->info->req_offset,
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pd_info->req_mask, idle ? -1U : 0);
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dsb(sy);
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do {
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regmap_read(pmu->regmap, pmu->info->ack_offset, &val);
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} while ((val & pd_info->ack_mask) != (idle ? pd_info->ack_mask : 0));
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while (rockchip_pmu_domain_is_idle(pd) != idle)
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cpu_relax();
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return 0;
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}
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static int rockchip_pmu_save_qos(struct rockchip_pm_domain *pd)
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{
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int i;
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for (i = 0; i < pd->num_qos; i++) {
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regmap_read(pd->qos_regmap[i],
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QOS_PRIORITY,
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&pd->qos_save_regs[0][i]);
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regmap_read(pd->qos_regmap[i],
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QOS_MODE,
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&pd->qos_save_regs[1][i]);
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regmap_read(pd->qos_regmap[i],
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QOS_BANDWIDTH,
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&pd->qos_save_regs[2][i]);
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regmap_read(pd->qos_regmap[i],
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QOS_SATURATION,
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&pd->qos_save_regs[3][i]);
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regmap_read(pd->qos_regmap[i],
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QOS_EXTCONTROL,
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&pd->qos_save_regs[4][i]);
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}
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return 0;
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}
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static int rockchip_pmu_restore_qos(struct rockchip_pm_domain *pd)
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{
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int i;
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for (i = 0; i < pd->num_qos; i++) {
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regmap_write(pd->qos_regmap[i],
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QOS_PRIORITY,
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pd->qos_save_regs[0][i]);
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regmap_write(pd->qos_regmap[i],
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QOS_MODE,
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pd->qos_save_regs[1][i]);
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regmap_write(pd->qos_regmap[i],
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QOS_BANDWIDTH,
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pd->qos_save_regs[2][i]);
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regmap_write(pd->qos_regmap[i],
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QOS_SATURATION,
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pd->qos_save_regs[3][i]);
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regmap_write(pd->qos_regmap[i],
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QOS_EXTCONTROL,
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pd->qos_save_regs[4][i]);
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}
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return 0;
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}
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static bool rockchip_pmu_domain_is_on(struct rockchip_pm_domain *pd)
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{
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struct rockchip_pmu *pmu = pd->pmu;
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unsigned int val;
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/* check idle status for idle-only domains */
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if (pd->info->status_mask == 0)
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return !rockchip_pmu_domain_is_idle(pd);
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regmap_read(pmu->regmap, pmu->info->status_offset, &val);
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/* 1'b0: power on, 1'b1: power off */
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return !(val & pd->info->status_mask);
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}
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static void rockchip_do_pmu_set_power_domain(struct rockchip_pm_domain *pd,
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bool on)
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{
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struct rockchip_pmu *pmu = pd->pmu;
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if (pd->info->pwr_mask == 0)
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return;
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regmap_update_bits(pmu->regmap, pmu->info->pwr_offset,
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pd->info->pwr_mask, on ? 0 : -1U);
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dsb(sy);
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while (rockchip_pmu_domain_is_on(pd) != on)
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cpu_relax();
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}
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static int rockchip_pd_power(struct rockchip_pm_domain *pd, bool power_on)
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{
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int i;
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mutex_lock(&pd->pmu->mutex);
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if (rockchip_pmu_domain_is_on(pd) != power_on) {
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for (i = 0; i < pd->num_clks; i++)
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clk_enable(pd->clks[i]);
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if (!power_on) {
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rockchip_pmu_save_qos(pd);
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/* if powering down, idle request to NIU first */
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rockchip_pmu_set_idle_request(pd, true);
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}
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rockchip_do_pmu_set_power_domain(pd, power_on);
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if (power_on) {
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/* if powering up, leave idle mode */
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rockchip_pmu_set_idle_request(pd, false);
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rockchip_pmu_restore_qos(pd);
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}
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for (i = pd->num_clks - 1; i >= 0; i--)
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clk_disable(pd->clks[i]);
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}
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mutex_unlock(&pd->pmu->mutex);
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return 0;
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}
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static int rockchip_pd_power_on(struct generic_pm_domain *domain)
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{
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struct rockchip_pm_domain *pd = to_rockchip_pd(domain);
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return rockchip_pd_power(pd, true);
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}
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static int rockchip_pd_power_off(struct generic_pm_domain *domain)
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{
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struct rockchip_pm_domain *pd = to_rockchip_pd(domain);
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return rockchip_pd_power(pd, false);
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}
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static int rockchip_pd_attach_dev(struct generic_pm_domain *genpd,
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struct device *dev)
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{
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struct clk *clk;
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int i;
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int error;
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dev_dbg(dev, "attaching to power domain '%s'\n", genpd->name);
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error = pm_clk_create(dev);
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if (error) {
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dev_err(dev, "pm_clk_create failed %d\n", error);
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return error;
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}
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i = 0;
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while ((clk = of_clk_get(dev->of_node, i++)) && !IS_ERR(clk)) {
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dev_dbg(dev, "adding clock '%pC' to list of PM clocks\n", clk);
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error = pm_clk_add_clk(dev, clk);
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if (error) {
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dev_err(dev, "pm_clk_add_clk failed %d\n", error);
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clk_put(clk);
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pm_clk_destroy(dev);
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return error;
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}
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}
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return 0;
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}
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static void rockchip_pd_detach_dev(struct generic_pm_domain *genpd,
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struct device *dev)
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{
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dev_dbg(dev, "detaching from power domain '%s'\n", genpd->name);
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pm_clk_destroy(dev);
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}
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static bool rockchip_active_wakeup(struct device *dev)
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{
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struct generic_pm_domain *genpd;
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struct rockchip_pm_domain *pd;
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genpd = pd_to_genpd(dev->pm_domain);
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pd = container_of(genpd, struct rockchip_pm_domain, genpd);
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return pd->info->active_wakeup;
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}
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static int rockchip_pm_add_one_domain(struct rockchip_pmu *pmu,
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struct device_node *node)
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{
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const struct rockchip_domain_info *pd_info;
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struct rockchip_pm_domain *pd;
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struct device_node *qos_node;
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struct clk *clk;
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int clk_cnt;
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int i, j;
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u32 id;
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int error;
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error = of_property_read_u32(node, "reg", &id);
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if (error) {
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dev_err(pmu->dev,
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"%s: failed to retrieve domain id (reg): %d\n",
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node->name, error);
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return -EINVAL;
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}
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if (id >= pmu->info->num_domains) {
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dev_err(pmu->dev, "%s: invalid domain id %d\n",
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node->name, id);
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return -EINVAL;
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}
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pd_info = &pmu->info->domain_info[id];
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if (!pd_info) {
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dev_err(pmu->dev, "%s: undefined domain id %d\n",
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node->name, id);
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return -EINVAL;
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}
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clk_cnt = of_count_phandle_with_args(node, "clocks", "#clock-cells");
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pd = devm_kzalloc(pmu->dev,
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sizeof(*pd) + clk_cnt * sizeof(pd->clks[0]),
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GFP_KERNEL);
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if (!pd)
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return -ENOMEM;
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pd->info = pd_info;
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pd->pmu = pmu;
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for (i = 0; i < clk_cnt; i++) {
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clk = of_clk_get(node, i);
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if (IS_ERR(clk)) {
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error = PTR_ERR(clk);
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dev_err(pmu->dev,
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"%s: failed to get clk at index %d: %d\n",
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node->name, i, error);
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goto err_out;
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}
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error = clk_prepare(clk);
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if (error) {
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dev_err(pmu->dev,
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"%s: failed to prepare clk %pC (index %d): %d\n",
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node->name, clk, i, error);
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clk_put(clk);
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goto err_out;
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}
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pd->clks[pd->num_clks++] = clk;
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dev_dbg(pmu->dev, "added clock '%pC' to domain '%s'\n",
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clk, node->name);
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}
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pd->num_qos = of_count_phandle_with_args(node, "pm_qos",
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NULL);
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if (pd->num_qos > 0) {
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pd->qos_regmap = devm_kcalloc(pmu->dev, pd->num_qos,
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sizeof(*pd->qos_regmap),
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GFP_KERNEL);
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if (!pd->qos_regmap) {
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error = -ENOMEM;
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goto err_out;
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}
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for (j = 0; j < MAX_QOS_REGS_NUM; j++) {
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pd->qos_save_regs[j] = devm_kcalloc(pmu->dev,
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pd->num_qos,
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sizeof(u32),
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GFP_KERNEL);
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if (!pd->qos_save_regs[j]) {
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error = -ENOMEM;
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goto err_out;
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}
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}
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for (j = 0; j < pd->num_qos; j++) {
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qos_node = of_parse_phandle(node, "pm_qos", j);
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if (!qos_node) {
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error = -ENODEV;
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goto err_out;
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}
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pd->qos_regmap[j] = syscon_node_to_regmap(qos_node);
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if (IS_ERR(pd->qos_regmap[j])) {
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error = -ENODEV;
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of_node_put(qos_node);
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goto err_out;
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}
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of_node_put(qos_node);
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}
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}
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error = rockchip_pd_power(pd, true);
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if (error) {
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dev_err(pmu->dev,
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"failed to power on domain '%s': %d\n",
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node->name, error);
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goto err_out;
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}
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pd->genpd.name = node->name;
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pd->genpd.power_off = rockchip_pd_power_off;
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pd->genpd.power_on = rockchip_pd_power_on;
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pd->genpd.attach_dev = rockchip_pd_attach_dev;
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pd->genpd.detach_dev = rockchip_pd_detach_dev;
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pd->genpd.dev_ops.active_wakeup = rockchip_active_wakeup;
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pd->genpd.flags = GENPD_FLAG_PM_CLK;
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pm_genpd_init(&pd->genpd, NULL, false);
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pmu->genpd_data.domains[id] = &pd->genpd;
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return 0;
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err_out:
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while (--i >= 0) {
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clk_unprepare(pd->clks[i]);
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clk_put(pd->clks[i]);
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}
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return error;
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}
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static void rockchip_pm_remove_one_domain(struct rockchip_pm_domain *pd)
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{
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int i;
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for (i = 0; i < pd->num_clks; i++) {
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clk_unprepare(pd->clks[i]);
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clk_put(pd->clks[i]);
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}
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/* protect the zeroing of pm->num_clks */
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mutex_lock(&pd->pmu->mutex);
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pd->num_clks = 0;
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mutex_unlock(&pd->pmu->mutex);
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/* devm will free our memory */
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}
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static void rockchip_pm_domain_cleanup(struct rockchip_pmu *pmu)
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{
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struct generic_pm_domain *genpd;
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struct rockchip_pm_domain *pd;
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int i;
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for (i = 0; i < pmu->genpd_data.num_domains; i++) {
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genpd = pmu->genpd_data.domains[i];
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if (genpd) {
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pd = to_rockchip_pd(genpd);
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rockchip_pm_remove_one_domain(pd);
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}
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}
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/* devm will free our memory */
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}
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static void rockchip_configure_pd_cnt(struct rockchip_pmu *pmu,
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u32 domain_reg_offset,
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unsigned int count)
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{
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/* First configure domain power down transition count ... */
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regmap_write(pmu->regmap, domain_reg_offset, count);
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/* ... and then power up count. */
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regmap_write(pmu->regmap, domain_reg_offset + 4, count);
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}
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static int rockchip_pm_add_subdomain(struct rockchip_pmu *pmu,
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struct device_node *parent)
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{
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struct device_node *np;
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struct generic_pm_domain *child_domain, *parent_domain;
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int error;
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for_each_child_of_node(parent, np) {
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u32 idx;
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error = of_property_read_u32(parent, "reg", &idx);
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if (error) {
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dev_err(pmu->dev,
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"%s: failed to retrieve domain id (reg): %d\n",
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parent->name, error);
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goto err_out;
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}
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parent_domain = pmu->genpd_data.domains[idx];
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error = rockchip_pm_add_one_domain(pmu, np);
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if (error) {
|
|
dev_err(pmu->dev, "failed to handle node %s: %d\n",
|
|
np->name, error);
|
|
goto err_out;
|
|
}
|
|
|
|
error = of_property_read_u32(np, "reg", &idx);
|
|
if (error) {
|
|
dev_err(pmu->dev,
|
|
"%s: failed to retrieve domain id (reg): %d\n",
|
|
np->name, error);
|
|
goto err_out;
|
|
}
|
|
child_domain = pmu->genpd_data.domains[idx];
|
|
|
|
error = pm_genpd_add_subdomain(parent_domain, child_domain);
|
|
if (error) {
|
|
dev_err(pmu->dev, "%s failed to add subdomain %s: %d\n",
|
|
parent_domain->name, child_domain->name, error);
|
|
goto err_out;
|
|
} else {
|
|
dev_dbg(pmu->dev, "%s add subdomain: %s\n",
|
|
parent_domain->name, child_domain->name);
|
|
}
|
|
|
|
rockchip_pm_add_subdomain(pmu, np);
|
|
}
|
|
|
|
return 0;
|
|
|
|
err_out:
|
|
of_node_put(np);
|
|
return error;
|
|
}
|
|
|
|
static int rockchip_pm_domain_probe(struct platform_device *pdev)
|
|
{
|
|
struct device *dev = &pdev->dev;
|
|
struct device_node *np = dev->of_node;
|
|
struct device_node *node;
|
|
struct device *parent;
|
|
struct rockchip_pmu *pmu;
|
|
const struct of_device_id *match;
|
|
const struct rockchip_pmu_info *pmu_info;
|
|
int error;
|
|
|
|
if (!np) {
|
|
dev_err(dev, "device tree node not found\n");
|
|
return -ENODEV;
|
|
}
|
|
|
|
match = of_match_device(dev->driver->of_match_table, dev);
|
|
if (!match || !match->data) {
|
|
dev_err(dev, "missing pmu data\n");
|
|
return -EINVAL;
|
|
}
|
|
|
|
pmu_info = match->data;
|
|
|
|
pmu = devm_kzalloc(dev,
|
|
sizeof(*pmu) +
|
|
pmu_info->num_domains * sizeof(pmu->domains[0]),
|
|
GFP_KERNEL);
|
|
if (!pmu)
|
|
return -ENOMEM;
|
|
|
|
pmu->dev = &pdev->dev;
|
|
mutex_init(&pmu->mutex);
|
|
|
|
pmu->info = pmu_info;
|
|
|
|
pmu->genpd_data.domains = pmu->domains;
|
|
pmu->genpd_data.num_domains = pmu_info->num_domains;
|
|
|
|
parent = dev->parent;
|
|
if (!parent) {
|
|
dev_err(dev, "no parent for syscon devices\n");
|
|
return -ENODEV;
|
|
}
|
|
|
|
pmu->regmap = syscon_node_to_regmap(parent->of_node);
|
|
if (IS_ERR(pmu->regmap)) {
|
|
dev_err(dev, "no regmap available\n");
|
|
return PTR_ERR(pmu->regmap);
|
|
}
|
|
|
|
/*
|
|
* Configure power up and down transition delays for CORE
|
|
* and GPU domains.
|
|
*/
|
|
rockchip_configure_pd_cnt(pmu, pmu_info->core_pwrcnt_offset,
|
|
pmu_info->core_power_transition_time);
|
|
rockchip_configure_pd_cnt(pmu, pmu_info->gpu_pwrcnt_offset,
|
|
pmu_info->gpu_power_transition_time);
|
|
|
|
error = -ENODEV;
|
|
|
|
for_each_available_child_of_node(np, node) {
|
|
error = rockchip_pm_add_one_domain(pmu, node);
|
|
if (error) {
|
|
dev_err(dev, "failed to handle node %s: %d\n",
|
|
node->name, error);
|
|
of_node_put(node);
|
|
goto err_out;
|
|
}
|
|
|
|
error = rockchip_pm_add_subdomain(pmu, node);
|
|
if (error < 0) {
|
|
dev_err(dev, "failed to handle subdomain node %s: %d\n",
|
|
node->name, error);
|
|
of_node_put(node);
|
|
goto err_out;
|
|
}
|
|
}
|
|
|
|
if (error) {
|
|
dev_dbg(dev, "no power domains defined\n");
|
|
goto err_out;
|
|
}
|
|
|
|
of_genpd_add_provider_onecell(np, &pmu->genpd_data);
|
|
|
|
return 0;
|
|
|
|
err_out:
|
|
rockchip_pm_domain_cleanup(pmu);
|
|
return error;
|
|
}
|
|
|
|
static const struct rockchip_domain_info rk3288_pm_domains[] = {
|
|
[RK3288_PD_VIO] = DOMAIN_RK3288(7, 7, 4, false),
|
|
[RK3288_PD_HEVC] = DOMAIN_RK3288(14, 10, 9, false),
|
|
[RK3288_PD_VIDEO] = DOMAIN_RK3288(8, 8, 3, false),
|
|
[RK3288_PD_GPU] = DOMAIN_RK3288(9, 9, 2, false),
|
|
};
|
|
|
|
static const struct rockchip_domain_info rk3368_pm_domains[] = {
|
|
[RK3368_PD_PERI] = DOMAIN_RK3368(13, 12, 6, true),
|
|
[RK3368_PD_VIO] = DOMAIN_RK3368(15, 14, 8, false),
|
|
[RK3368_PD_VIDEO] = DOMAIN_RK3368(14, 13, 7, false),
|
|
[RK3368_PD_GPU_0] = DOMAIN_RK3368(16, 15, 2, false),
|
|
[RK3368_PD_GPU_1] = DOMAIN_RK3368(17, 16, 2, false),
|
|
};
|
|
|
|
static const struct rockchip_domain_info rk3399_pm_domains[] = {
|
|
[RK3399_PD_TCPD0] = DOMAIN_RK3399(8, 8, -1, false),
|
|
[RK3399_PD_TCPD1] = DOMAIN_RK3399(9, 9, -1, false),
|
|
[RK3399_PD_CCI] = DOMAIN_RK3399(10, 10, -1, true),
|
|
[RK3399_PD_CCI0] = DOMAIN_RK3399(-1, -1, 15, true),
|
|
[RK3399_PD_CCI1] = DOMAIN_RK3399(-1, -1, 16, true),
|
|
[RK3399_PD_PERILP] = DOMAIN_RK3399(11, 11, 1, true),
|
|
[RK3399_PD_PERIHP] = DOMAIN_RK3399(12, 12, 2, true),
|
|
[RK3399_PD_CENTER] = DOMAIN_RK3399(13, 13, 14, true),
|
|
[RK3399_PD_VIO] = DOMAIN_RK3399(14, 14, 17, false),
|
|
[RK3399_PD_GPU] = DOMAIN_RK3399(15, 15, 0, false),
|
|
[RK3399_PD_VCODEC] = DOMAIN_RK3399(16, 16, 3, false),
|
|
[RK3399_PD_VDU] = DOMAIN_RK3399(17, 17, 4, false),
|
|
[RK3399_PD_RGA] = DOMAIN_RK3399(18, 18, 5, false),
|
|
[RK3399_PD_IEP] = DOMAIN_RK3399(19, 19, 6, false),
|
|
[RK3399_PD_VO] = DOMAIN_RK3399(20, 20, -1, false),
|
|
[RK3399_PD_VOPB] = DOMAIN_RK3399(-1, -1, 7, false),
|
|
[RK3399_PD_VOPL] = DOMAIN_RK3399(-1, -1, 8, false),
|
|
[RK3399_PD_ISP0] = DOMAIN_RK3399(22, 22, 9, false),
|
|
[RK3399_PD_ISP1] = DOMAIN_RK3399(23, 23, 10, false),
|
|
[RK3399_PD_HDCP] = DOMAIN_RK3399(24, 24, 11, false),
|
|
[RK3399_PD_GMAC] = DOMAIN_RK3399(25, 25, 23, true),
|
|
[RK3399_PD_EMMC] = DOMAIN_RK3399(26, 26, 24, true),
|
|
[RK3399_PD_USB3] = DOMAIN_RK3399(27, 27, 12, true),
|
|
[RK3399_PD_EDP] = DOMAIN_RK3399(28, 28, 22, false),
|
|
[RK3399_PD_GIC] = DOMAIN_RK3399(29, 29, 27, true),
|
|
[RK3399_PD_SD] = DOMAIN_RK3399(30, 30, 28, true),
|
|
[RK3399_PD_SDIOAUDIO] = DOMAIN_RK3399(31, 31, 29, true),
|
|
};
|
|
|
|
static const struct rockchip_pmu_info rk3288_pmu = {
|
|
.pwr_offset = 0x08,
|
|
.status_offset = 0x0c,
|
|
.req_offset = 0x10,
|
|
.idle_offset = 0x14,
|
|
.ack_offset = 0x14,
|
|
|
|
.core_pwrcnt_offset = 0x34,
|
|
.gpu_pwrcnt_offset = 0x3c,
|
|
|
|
.core_power_transition_time = 24, /* 1us */
|
|
.gpu_power_transition_time = 24, /* 1us */
|
|
|
|
.num_domains = ARRAY_SIZE(rk3288_pm_domains),
|
|
.domain_info = rk3288_pm_domains,
|
|
};
|
|
|
|
static const struct rockchip_pmu_info rk3368_pmu = {
|
|
.pwr_offset = 0x0c,
|
|
.status_offset = 0x10,
|
|
.req_offset = 0x3c,
|
|
.idle_offset = 0x40,
|
|
.ack_offset = 0x40,
|
|
|
|
.core_pwrcnt_offset = 0x48,
|
|
.gpu_pwrcnt_offset = 0x50,
|
|
|
|
.core_power_transition_time = 24,
|
|
.gpu_power_transition_time = 24,
|
|
|
|
.num_domains = ARRAY_SIZE(rk3368_pm_domains),
|
|
.domain_info = rk3368_pm_domains,
|
|
};
|
|
|
|
static const struct rockchip_pmu_info rk3399_pmu = {
|
|
.pwr_offset = 0x14,
|
|
.status_offset = 0x18,
|
|
.req_offset = 0x60,
|
|
.idle_offset = 0x64,
|
|
.ack_offset = 0x68,
|
|
|
|
.core_pwrcnt_offset = 0x9c,
|
|
.gpu_pwrcnt_offset = 0xa4,
|
|
|
|
.core_power_transition_time = 24,
|
|
.gpu_power_transition_time = 24,
|
|
|
|
.num_domains = ARRAY_SIZE(rk3399_pm_domains),
|
|
.domain_info = rk3399_pm_domains,
|
|
};
|
|
|
|
static const struct of_device_id rockchip_pm_domain_dt_match[] = {
|
|
{
|
|
.compatible = "rockchip,rk3288-power-controller",
|
|
.data = (void *)&rk3288_pmu,
|
|
},
|
|
{
|
|
.compatible = "rockchip,rk3368-power-controller",
|
|
.data = (void *)&rk3368_pmu,
|
|
},
|
|
{
|
|
.compatible = "rockchip,rk3399-power-controller",
|
|
.data = (void *)&rk3399_pmu,
|
|
},
|
|
{ /* sentinel */ },
|
|
};
|
|
|
|
static struct platform_driver rockchip_pm_domain_driver = {
|
|
.probe = rockchip_pm_domain_probe,
|
|
.driver = {
|
|
.name = "rockchip-pm-domain",
|
|
.of_match_table = rockchip_pm_domain_dt_match,
|
|
/*
|
|
* We can't forcibly eject devices form power domain,
|
|
* so we can't really remove power domains once they
|
|
* were added.
|
|
*/
|
|
.suppress_bind_attrs = true,
|
|
},
|
|
};
|
|
|
|
static int __init rockchip_pm_domain_drv_register(void)
|
|
{
|
|
return platform_driver_register(&rockchip_pm_domain_driver);
|
|
}
|
|
postcore_initcall(rockchip_pm_domain_drv_register);
|