263 строки
7.8 KiB
C
263 строки
7.8 KiB
C
/* SPDX-License-Identifier: GPL-2.0-or-later */
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/*
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* cx25840.h - definition for cx25840/1/2/3 inputs
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*
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* Copyright (C) 2006 Hans Verkuil (hverkuil@xs4all.nl)
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*/
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#ifndef _CX25840_H_
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#define _CX25840_H_
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/*
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* Note that the cx25840 driver requires that the bridge driver calls the
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* v4l2_subdev's load_fw operation in order to load the driver's firmware.
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* This will load the firmware on the first invocation (further ones are NOP).
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* Without this the audio standard detection will fail and you will
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* only get mono.
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* Alternatively, you can call the reset operation (this can be done
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* multiple times if needed, each invocation will fully reinitialize
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* the device).
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*
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* Since loading the firmware is often problematic when the driver is
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* compiled into the kernel I recommend postponing calling this function
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* until the first open of the video device. Another reason for
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* postponing it is that loading this firmware takes a long time (seconds)
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* due to the slow i2c bus speed. So it will speed up the boot process if
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* you can avoid loading the fw as long as the video device isn't used.
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*/
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enum cx25840_video_input {
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/* Composite video inputs In1-In8 */
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CX25840_COMPOSITE1 = 1,
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CX25840_COMPOSITE2,
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CX25840_COMPOSITE3,
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CX25840_COMPOSITE4,
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CX25840_COMPOSITE5,
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CX25840_COMPOSITE6,
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CX25840_COMPOSITE7,
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CX25840_COMPOSITE8,
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/*
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* S-Video inputs consist of one luma input (In1-In8) ORed with one
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* chroma input (In5-In8)
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*/
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CX25840_SVIDEO_LUMA1 = 0x10,
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CX25840_SVIDEO_LUMA2 = 0x20,
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CX25840_SVIDEO_LUMA3 = 0x30,
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CX25840_SVIDEO_LUMA4 = 0x40,
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CX25840_SVIDEO_LUMA5 = 0x50,
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CX25840_SVIDEO_LUMA6 = 0x60,
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CX25840_SVIDEO_LUMA7 = 0x70,
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CX25840_SVIDEO_LUMA8 = 0x80,
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CX25840_SVIDEO_CHROMA4 = 0x400,
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CX25840_SVIDEO_CHROMA5 = 0x500,
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CX25840_SVIDEO_CHROMA6 = 0x600,
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CX25840_SVIDEO_CHROMA7 = 0x700,
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CX25840_SVIDEO_CHROMA8 = 0x800,
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/* S-Video aliases for common luma/chroma combinations */
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CX25840_SVIDEO1 = 0x510,
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CX25840_SVIDEO2 = 0x620,
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CX25840_SVIDEO3 = 0x730,
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CX25840_SVIDEO4 = 0x840,
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/* Allow frames to specify specific input configurations */
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CX25840_VIN1_CH1 = 0x80000000,
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CX25840_VIN2_CH1 = 0x80000001,
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CX25840_VIN3_CH1 = 0x80000002,
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CX25840_VIN4_CH1 = 0x80000003,
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CX25840_VIN5_CH1 = 0x80000004,
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CX25840_VIN6_CH1 = 0x80000005,
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CX25840_VIN7_CH1 = 0x80000006,
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CX25840_VIN8_CH1 = 0x80000007,
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CX25840_VIN4_CH2 = 0x80000000,
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CX25840_VIN5_CH2 = 0x80000010,
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CX25840_VIN6_CH2 = 0x80000020,
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CX25840_NONE_CH2 = 0x80000030,
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CX25840_VIN7_CH3 = 0x80000000,
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CX25840_VIN8_CH3 = 0x80000040,
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CX25840_NONE0_CH3 = 0x80000080,
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CX25840_NONE1_CH3 = 0x800000c0,
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CX25840_SVIDEO_ON = 0x80000100,
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CX25840_COMPONENT_ON = 0x80000200,
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CX25840_DIF_ON = 0x80000400,
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};
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/*
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* The defines below are used to set the chip video output settings
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* in the generic mode that can be enabled by calling the subdevice
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* init core op.
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*
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* The requested settings can be passed to the init core op as
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* @val parameter and to the s_routing video op as @config parameter.
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*
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* For details please refer to the section 3.7 Video Output Formatting and
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* to Video Out Control 1 to 4 registers in the section 5.6 Video Decoder Core
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* of the chip datasheet.
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*/
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#define CX25840_VCONFIG_FMT_SHIFT 0
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#define CX25840_VCONFIG_FMT_MASK GENMASK(2, 0)
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#define CX25840_VCONFIG_FMT_BT601 BIT(0)
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#define CX25840_VCONFIG_FMT_BT656 BIT(1)
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#define CX25840_VCONFIG_FMT_VIP11 GENMASK(1, 0)
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#define CX25840_VCONFIG_FMT_VIP2 BIT(2)
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#define CX25840_VCONFIG_RES_SHIFT 3
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#define CX25840_VCONFIG_RES_MASK GENMASK(4, 3)
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#define CX25840_VCONFIG_RES_8BIT BIT(3)
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#define CX25840_VCONFIG_RES_10BIT BIT(4)
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#define CX25840_VCONFIG_VBIRAW_SHIFT 5
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#define CX25840_VCONFIG_VBIRAW_MASK GENMASK(6, 5)
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#define CX25840_VCONFIG_VBIRAW_DISABLED BIT(5)
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#define CX25840_VCONFIG_VBIRAW_ENABLED BIT(6)
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#define CX25840_VCONFIG_ANCDATA_SHIFT 7
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#define CX25840_VCONFIG_ANCDATA_MASK GENMASK(8, 7)
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#define CX25840_VCONFIG_ANCDATA_DISABLED BIT(7)
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#define CX25840_VCONFIG_ANCDATA_ENABLED BIT(8)
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#define CX25840_VCONFIG_TASKBIT_SHIFT 9
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#define CX25840_VCONFIG_TASKBIT_MASK GENMASK(10, 9)
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#define CX25840_VCONFIG_TASKBIT_ZERO BIT(9)
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#define CX25840_VCONFIG_TASKBIT_ONE BIT(10)
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#define CX25840_VCONFIG_ACTIVE_SHIFT 11
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#define CX25840_VCONFIG_ACTIVE_MASK GENMASK(12, 11)
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#define CX25840_VCONFIG_ACTIVE_COMPOSITE BIT(11)
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#define CX25840_VCONFIG_ACTIVE_HORIZONTAL BIT(12)
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#define CX25840_VCONFIG_VALID_SHIFT 13
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#define CX25840_VCONFIG_VALID_MASK GENMASK(14, 13)
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#define CX25840_VCONFIG_VALID_NORMAL BIT(13)
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#define CX25840_VCONFIG_VALID_ANDACTIVE BIT(14)
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#define CX25840_VCONFIG_HRESETW_SHIFT 15
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#define CX25840_VCONFIG_HRESETW_MASK GENMASK(16, 15)
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#define CX25840_VCONFIG_HRESETW_NORMAL BIT(15)
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#define CX25840_VCONFIG_HRESETW_PIXCLK BIT(16)
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#define CX25840_VCONFIG_CLKGATE_SHIFT 17
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#define CX25840_VCONFIG_CLKGATE_MASK GENMASK(18, 17)
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#define CX25840_VCONFIG_CLKGATE_NONE BIT(17)
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#define CX25840_VCONFIG_CLKGATE_VALID BIT(18)
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#define CX25840_VCONFIG_CLKGATE_VALIDACTIVE GENMASK(18, 17)
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#define CX25840_VCONFIG_DCMODE_SHIFT 19
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#define CX25840_VCONFIG_DCMODE_MASK GENMASK(20, 19)
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#define CX25840_VCONFIG_DCMODE_DWORDS BIT(19)
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#define CX25840_VCONFIG_DCMODE_BYTES BIT(20)
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#define CX25840_VCONFIG_IDID0S_SHIFT 21
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#define CX25840_VCONFIG_IDID0S_MASK GENMASK(22, 21)
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#define CX25840_VCONFIG_IDID0S_NORMAL BIT(21)
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#define CX25840_VCONFIG_IDID0S_LINECNT BIT(22)
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#define CX25840_VCONFIG_VIPCLAMP_SHIFT 23
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#define CX25840_VCONFIG_VIPCLAMP_MASK GENMASK(24, 23)
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#define CX25840_VCONFIG_VIPCLAMP_ENABLED BIT(23)
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#define CX25840_VCONFIG_VIPCLAMP_DISABLED BIT(24)
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enum cx25840_audio_input {
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/* Audio inputs: serial or In4-In8 */
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CX25840_AUDIO_SERIAL,
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CX25840_AUDIO4 = 4,
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CX25840_AUDIO5,
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CX25840_AUDIO6,
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CX25840_AUDIO7,
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CX25840_AUDIO8,
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};
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enum cx25840_io_pin {
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CX25840_PIN_DVALID_PRGM0 = 0,
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CX25840_PIN_FIELD_PRGM1,
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CX25840_PIN_HRESET_PRGM2,
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CX25840_PIN_VRESET_HCTL_PRGM3,
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CX25840_PIN_IRQ_N_PRGM4,
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CX25840_PIN_IR_TX_PRGM6,
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CX25840_PIN_IR_RX_PRGM5,
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CX25840_PIN_GPIO0_PRGM8,
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CX25840_PIN_GPIO1_PRGM9,
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CX25840_PIN_SA_SDIN, /* Alternate GP Input only */
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CX25840_PIN_SA_SDOUT, /* Alternate GP Input only */
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CX25840_PIN_PLL_CLK_PRGM7,
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CX25840_PIN_CHIP_SEL_VIPCLK, /* Output only */
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};
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enum cx25840_io_pad {
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/* Output pads, these must match the actual chip register values */
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CX25840_PAD_DEFAULT = 0,
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CX25840_PAD_ACTIVE,
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CX25840_PAD_VACTIVE,
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CX25840_PAD_CBFLAG,
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CX25840_PAD_VID_DATA_EXT0,
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CX25840_PAD_VID_DATA_EXT1,
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CX25840_PAD_GPO0,
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CX25840_PAD_GPO1,
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CX25840_PAD_GPO2,
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CX25840_PAD_GPO3,
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CX25840_PAD_IRQ_N,
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CX25840_PAD_AC_SYNC,
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CX25840_PAD_AC_SDOUT,
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CX25840_PAD_PLL_CLK,
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CX25840_PAD_VRESET,
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CX25840_PAD_RESERVED,
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/* Pads for PLL_CLK output only */
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CX25840_PAD_XTI_X5_DLL,
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CX25840_PAD_AUX_PLL,
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CX25840_PAD_VID_PLL,
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CX25840_PAD_XTI,
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/* Input Pads */
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CX25840_PAD_GPI0,
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CX25840_PAD_GPI1,
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CX25840_PAD_GPI2,
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CX25840_PAD_GPI3,
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};
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enum cx25840_io_pin_strength {
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CX25840_PIN_DRIVE_MEDIUM = 0,
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CX25840_PIN_DRIVE_SLOW,
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CX25840_PIN_DRIVE_FAST,
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};
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enum cx23885_io_pin {
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CX23885_PIN_IR_RX_GPIO19,
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CX23885_PIN_IR_TX_GPIO20,
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CX23885_PIN_I2S_SDAT_GPIO21,
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CX23885_PIN_I2S_WCLK_GPIO22,
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CX23885_PIN_I2S_BCLK_GPIO23,
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CX23885_PIN_IRQ_N_GPIO16,
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};
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enum cx23885_io_pad {
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CX23885_PAD_IR_RX,
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CX23885_PAD_GPIO19,
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CX23885_PAD_IR_TX,
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CX23885_PAD_GPIO20,
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CX23885_PAD_I2S_SDAT,
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CX23885_PAD_GPIO21,
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CX23885_PAD_I2S_WCLK,
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CX23885_PAD_GPIO22,
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CX23885_PAD_I2S_BCLK,
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CX23885_PAD_GPIO23,
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CX23885_PAD_IRQ_N,
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CX23885_PAD_GPIO16,
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};
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/*
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* pvr150_workaround activates a workaround for a hardware bug that is
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* present in Hauppauge PVR-150 (and possibly PVR-500) cards that have
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* certain NTSC tuners (tveeprom tuner model numbers 85, 99 and 112). The
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* audio autodetect fails on some channels for these models and the workaround
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* is to select the audio standard explicitly. Many thanks to Hauppauge for
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* providing this information.
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*
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* This platform data only needs to be supplied by the ivtv driver.
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*/
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struct cx25840_platform_data {
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int pvr150_workaround;
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};
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#endif
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