574 строки
15 KiB
C
574 строки
15 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (C) Overkiz SAS 2012
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*
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* Author: Boris BREZILLON <b.brezillon@overkiz.com>
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*/
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#include <linux/module.h>
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#include <linux/init.h>
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#include <linux/clocksource.h>
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#include <linux/clockchips.h>
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#include <linux/interrupt.h>
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#include <linux/irq.h>
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#include <linux/clk.h>
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#include <linux/err.h>
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#include <linux/ioport.h>
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#include <linux/io.h>
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#include <linux/mfd/syscon.h>
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#include <linux/platform_device.h>
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#include <linux/pwm.h>
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#include <linux/of_device.h>
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#include <linux/of_irq.h>
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#include <linux/regmap.h>
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#include <linux/slab.h>
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#include <soc/at91/atmel_tcb.h>
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#define NPWM 2
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#define ATMEL_TC_ACMR_MASK (ATMEL_TC_ACPA | ATMEL_TC_ACPC | \
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ATMEL_TC_AEEVT | ATMEL_TC_ASWTRG)
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#define ATMEL_TC_BCMR_MASK (ATMEL_TC_BCPB | ATMEL_TC_BCPC | \
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ATMEL_TC_BEEVT | ATMEL_TC_BSWTRG)
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struct atmel_tcb_pwm_device {
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enum pwm_polarity polarity; /* PWM polarity */
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unsigned div; /* PWM clock divider */
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unsigned duty; /* PWM duty expressed in clk cycles */
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unsigned period; /* PWM period expressed in clk cycles */
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};
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struct atmel_tcb_channel {
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u32 enabled;
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u32 cmr;
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u32 ra;
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u32 rb;
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u32 rc;
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};
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struct atmel_tcb_pwm_chip {
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struct pwm_chip chip;
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spinlock_t lock;
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u8 channel;
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u8 width;
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struct regmap *regmap;
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struct clk *clk;
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struct clk *gclk;
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struct clk *slow_clk;
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struct atmel_tcb_pwm_device *pwms[NPWM];
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struct atmel_tcb_channel bkup;
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};
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const u8 atmel_tcb_divisors[] = { 2, 8, 32, 128, 0, };
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static inline struct atmel_tcb_pwm_chip *to_tcb_chip(struct pwm_chip *chip)
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{
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return container_of(chip, struct atmel_tcb_pwm_chip, chip);
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}
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static int atmel_tcb_pwm_set_polarity(struct pwm_chip *chip,
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struct pwm_device *pwm,
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enum pwm_polarity polarity)
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{
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struct atmel_tcb_pwm_device *tcbpwm = pwm_get_chip_data(pwm);
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tcbpwm->polarity = polarity;
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return 0;
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}
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static int atmel_tcb_pwm_request(struct pwm_chip *chip,
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struct pwm_device *pwm)
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{
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struct atmel_tcb_pwm_chip *tcbpwmc = to_tcb_chip(chip);
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struct atmel_tcb_pwm_device *tcbpwm;
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unsigned cmr;
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int ret;
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tcbpwm = devm_kzalloc(chip->dev, sizeof(*tcbpwm), GFP_KERNEL);
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if (!tcbpwm)
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return -ENOMEM;
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ret = clk_prepare_enable(tcbpwmc->clk);
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if (ret) {
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devm_kfree(chip->dev, tcbpwm);
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return ret;
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}
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pwm_set_chip_data(pwm, tcbpwm);
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tcbpwm->polarity = PWM_POLARITY_NORMAL;
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tcbpwm->duty = 0;
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tcbpwm->period = 0;
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tcbpwm->div = 0;
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spin_lock(&tcbpwmc->lock);
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regmap_read(tcbpwmc->regmap, ATMEL_TC_REG(tcbpwmc->channel, CMR), &cmr);
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/*
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* Get init config from Timer Counter registers if
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* Timer Counter is already configured as a PWM generator.
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*/
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if (cmr & ATMEL_TC_WAVE) {
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if (pwm->hwpwm == 0)
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regmap_read(tcbpwmc->regmap,
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ATMEL_TC_REG(tcbpwmc->channel, RA),
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&tcbpwm->duty);
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else
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regmap_read(tcbpwmc->regmap,
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ATMEL_TC_REG(tcbpwmc->channel, RB),
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&tcbpwm->duty);
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tcbpwm->div = cmr & ATMEL_TC_TCCLKS;
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regmap_read(tcbpwmc->regmap, ATMEL_TC_REG(tcbpwmc->channel, RC),
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&tcbpwm->period);
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cmr &= (ATMEL_TC_TCCLKS | ATMEL_TC_ACMR_MASK |
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ATMEL_TC_BCMR_MASK);
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} else
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cmr = 0;
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cmr |= ATMEL_TC_WAVE | ATMEL_TC_WAVESEL_UP_AUTO | ATMEL_TC_EEVT_XC0;
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regmap_write(tcbpwmc->regmap, ATMEL_TC_REG(tcbpwmc->channel, CMR), cmr);
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spin_unlock(&tcbpwmc->lock);
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tcbpwmc->pwms[pwm->hwpwm] = tcbpwm;
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return 0;
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}
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static void atmel_tcb_pwm_free(struct pwm_chip *chip, struct pwm_device *pwm)
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{
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struct atmel_tcb_pwm_chip *tcbpwmc = to_tcb_chip(chip);
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struct atmel_tcb_pwm_device *tcbpwm = pwm_get_chip_data(pwm);
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clk_disable_unprepare(tcbpwmc->clk);
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tcbpwmc->pwms[pwm->hwpwm] = NULL;
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devm_kfree(chip->dev, tcbpwm);
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}
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static void atmel_tcb_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm)
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{
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struct atmel_tcb_pwm_chip *tcbpwmc = to_tcb_chip(chip);
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struct atmel_tcb_pwm_device *tcbpwm = pwm_get_chip_data(pwm);
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unsigned cmr;
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enum pwm_polarity polarity = tcbpwm->polarity;
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/*
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* If duty is 0 the timer will be stopped and we have to
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* configure the output correctly on software trigger:
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* - set output to high if PWM_POLARITY_INVERSED
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* - set output to low if PWM_POLARITY_NORMAL
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*
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* This is why we're reverting polarity in this case.
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*/
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if (tcbpwm->duty == 0)
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polarity = !polarity;
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spin_lock(&tcbpwmc->lock);
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regmap_read(tcbpwmc->regmap, ATMEL_TC_REG(tcbpwmc->channel, CMR), &cmr);
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/* flush old setting and set the new one */
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if (pwm->hwpwm == 0) {
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cmr &= ~ATMEL_TC_ACMR_MASK;
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if (polarity == PWM_POLARITY_INVERSED)
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cmr |= ATMEL_TC_ASWTRG_CLEAR;
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else
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cmr |= ATMEL_TC_ASWTRG_SET;
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} else {
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cmr &= ~ATMEL_TC_BCMR_MASK;
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if (polarity == PWM_POLARITY_INVERSED)
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cmr |= ATMEL_TC_BSWTRG_CLEAR;
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else
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cmr |= ATMEL_TC_BSWTRG_SET;
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}
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regmap_write(tcbpwmc->regmap, ATMEL_TC_REG(tcbpwmc->channel, CMR), cmr);
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/*
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* Use software trigger to apply the new setting.
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* If both PWM devices in this group are disabled we stop the clock.
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*/
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if (!(cmr & (ATMEL_TC_ACPC | ATMEL_TC_BCPC))) {
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regmap_write(tcbpwmc->regmap,
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ATMEL_TC_REG(tcbpwmc->channel, CCR),
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ATMEL_TC_SWTRG | ATMEL_TC_CLKDIS);
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tcbpwmc->bkup.enabled = 1;
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} else {
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regmap_write(tcbpwmc->regmap,
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ATMEL_TC_REG(tcbpwmc->channel, CCR),
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ATMEL_TC_SWTRG);
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tcbpwmc->bkup.enabled = 0;
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}
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spin_unlock(&tcbpwmc->lock);
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}
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static int atmel_tcb_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm)
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{
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struct atmel_tcb_pwm_chip *tcbpwmc = to_tcb_chip(chip);
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struct atmel_tcb_pwm_device *tcbpwm = pwm_get_chip_data(pwm);
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u32 cmr;
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enum pwm_polarity polarity = tcbpwm->polarity;
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/*
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* If duty is 0 the timer will be stopped and we have to
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* configure the output correctly on software trigger:
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* - set output to high if PWM_POLARITY_INVERSED
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* - set output to low if PWM_POLARITY_NORMAL
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*
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* This is why we're reverting polarity in this case.
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*/
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if (tcbpwm->duty == 0)
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polarity = !polarity;
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spin_lock(&tcbpwmc->lock);
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regmap_read(tcbpwmc->regmap, ATMEL_TC_REG(tcbpwmc->channel, CMR), &cmr);
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/* flush old setting and set the new one */
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cmr &= ~ATMEL_TC_TCCLKS;
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if (pwm->hwpwm == 0) {
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cmr &= ~ATMEL_TC_ACMR_MASK;
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/* Set CMR flags according to given polarity */
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if (polarity == PWM_POLARITY_INVERSED)
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cmr |= ATMEL_TC_ASWTRG_CLEAR;
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else
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cmr |= ATMEL_TC_ASWTRG_SET;
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} else {
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cmr &= ~ATMEL_TC_BCMR_MASK;
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if (polarity == PWM_POLARITY_INVERSED)
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cmr |= ATMEL_TC_BSWTRG_CLEAR;
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else
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cmr |= ATMEL_TC_BSWTRG_SET;
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}
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/*
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* If duty is 0 or equal to period there's no need to register
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* a specific action on RA/RB and RC compare.
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* The output will be configured on software trigger and keep
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* this config till next config call.
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*/
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if (tcbpwm->duty != tcbpwm->period && tcbpwm->duty > 0) {
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if (pwm->hwpwm == 0) {
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if (polarity == PWM_POLARITY_INVERSED)
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cmr |= ATMEL_TC_ACPA_SET | ATMEL_TC_ACPC_CLEAR;
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else
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cmr |= ATMEL_TC_ACPA_CLEAR | ATMEL_TC_ACPC_SET;
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} else {
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if (polarity == PWM_POLARITY_INVERSED)
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cmr |= ATMEL_TC_BCPB_SET | ATMEL_TC_BCPC_CLEAR;
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else
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cmr |= ATMEL_TC_BCPB_CLEAR | ATMEL_TC_BCPC_SET;
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}
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}
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cmr |= (tcbpwm->div & ATMEL_TC_TCCLKS);
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regmap_write(tcbpwmc->regmap, ATMEL_TC_REG(tcbpwmc->channel, CMR), cmr);
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if (pwm->hwpwm == 0)
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regmap_write(tcbpwmc->regmap,
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ATMEL_TC_REG(tcbpwmc->channel, RA),
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tcbpwm->duty);
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else
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regmap_write(tcbpwmc->regmap,
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ATMEL_TC_REG(tcbpwmc->channel, RB),
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tcbpwm->duty);
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regmap_write(tcbpwmc->regmap, ATMEL_TC_REG(tcbpwmc->channel, RC),
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tcbpwm->period);
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/* Use software trigger to apply the new setting */
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regmap_write(tcbpwmc->regmap, ATMEL_TC_REG(tcbpwmc->channel, CCR),
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ATMEL_TC_SWTRG | ATMEL_TC_CLKEN);
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tcbpwmc->bkup.enabled = 1;
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spin_unlock(&tcbpwmc->lock);
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return 0;
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}
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static int atmel_tcb_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
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int duty_ns, int period_ns)
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{
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struct atmel_tcb_pwm_chip *tcbpwmc = to_tcb_chip(chip);
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struct atmel_tcb_pwm_device *tcbpwm = pwm_get_chip_data(pwm);
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struct atmel_tcb_pwm_device *atcbpwm = NULL;
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int i = 0;
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int slowclk = 0;
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unsigned period;
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unsigned duty;
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unsigned rate = clk_get_rate(tcbpwmc->clk);
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unsigned long long min;
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unsigned long long max;
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/*
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* Find best clk divisor:
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* the smallest divisor which can fulfill the period_ns requirements.
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* If there is a gclk, the first divisor is actuallly the gclk selector
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*/
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if (tcbpwmc->gclk)
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i = 1;
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for (; i < ARRAY_SIZE(atmel_tcb_divisors); ++i) {
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if (atmel_tcb_divisors[i] == 0) {
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slowclk = i;
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continue;
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}
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min = div_u64((u64)NSEC_PER_SEC * atmel_tcb_divisors[i], rate);
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max = min << tcbpwmc->width;
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if (max >= period_ns)
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break;
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}
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/*
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* If none of the divisor are small enough to represent period_ns
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* take slow clock (32KHz).
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*/
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if (i == ARRAY_SIZE(atmel_tcb_divisors)) {
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i = slowclk;
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rate = clk_get_rate(tcbpwmc->slow_clk);
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min = div_u64(NSEC_PER_SEC, rate);
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max = min << tcbpwmc->width;
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/* If period is too big return ERANGE error */
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if (max < period_ns)
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return -ERANGE;
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}
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duty = div_u64(duty_ns, min);
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period = div_u64(period_ns, min);
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if (pwm->hwpwm == 0)
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atcbpwm = tcbpwmc->pwms[1];
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else
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atcbpwm = tcbpwmc->pwms[0];
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/*
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* PWM devices provided by the TCB driver are grouped by 2.
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* PWM devices in a given group must be configured with the
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* same period_ns.
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*
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* We're checking the period value of the second PWM device
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* in this group before applying the new config.
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*/
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if ((atcbpwm && atcbpwm->duty > 0 &&
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atcbpwm->duty != atcbpwm->period) &&
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(atcbpwm->div != i || atcbpwm->period != period)) {
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dev_err(chip->dev,
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"failed to configure period_ns: PWM group already configured with a different value\n");
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return -EINVAL;
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}
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tcbpwm->period = period;
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tcbpwm->div = i;
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tcbpwm->duty = duty;
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return 0;
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}
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static int atmel_tcb_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
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const struct pwm_state *state)
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{
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int duty_cycle, period;
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int ret;
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/* This function only sets a flag in driver data */
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atmel_tcb_pwm_set_polarity(chip, pwm, state->polarity);
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if (!state->enabled) {
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atmel_tcb_pwm_disable(chip, pwm);
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return 0;
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}
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period = state->period < INT_MAX ? state->period : INT_MAX;
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duty_cycle = state->duty_cycle < INT_MAX ? state->duty_cycle : INT_MAX;
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ret = atmel_tcb_pwm_config(chip, pwm, duty_cycle, period);
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if (ret)
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return ret;
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return atmel_tcb_pwm_enable(chip, pwm);
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}
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static const struct pwm_ops atmel_tcb_pwm_ops = {
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.request = atmel_tcb_pwm_request,
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.free = atmel_tcb_pwm_free,
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.apply = atmel_tcb_pwm_apply,
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.owner = THIS_MODULE,
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};
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static struct atmel_tcb_config tcb_rm9200_config = {
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.counter_width = 16,
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};
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static struct atmel_tcb_config tcb_sam9x5_config = {
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.counter_width = 32,
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};
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static struct atmel_tcb_config tcb_sama5d2_config = {
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.counter_width = 32,
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.has_gclk = 1,
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};
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static const struct of_device_id atmel_tcb_of_match[] = {
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{ .compatible = "atmel,at91rm9200-tcb", .data = &tcb_rm9200_config, },
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{ .compatible = "atmel,at91sam9x5-tcb", .data = &tcb_sam9x5_config, },
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{ .compatible = "atmel,sama5d2-tcb", .data = &tcb_sama5d2_config, },
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{ /* sentinel */ }
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};
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static int atmel_tcb_pwm_probe(struct platform_device *pdev)
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{
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const struct of_device_id *match;
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struct atmel_tcb_pwm_chip *tcbpwm;
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const struct atmel_tcb_config *config;
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struct device_node *np = pdev->dev.of_node;
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struct regmap *regmap;
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struct clk *clk, *gclk = NULL;
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struct clk *slow_clk;
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char clk_name[] = "t0_clk";
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int err;
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int channel;
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err = of_property_read_u32(np, "reg", &channel);
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if (err < 0) {
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dev_err(&pdev->dev,
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"failed to get Timer Counter Block channel from device tree (error: %d)\n",
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err);
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return err;
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}
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regmap = syscon_node_to_regmap(np->parent);
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if (IS_ERR(regmap))
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return PTR_ERR(regmap);
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slow_clk = of_clk_get_by_name(np->parent, "slow_clk");
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if (IS_ERR(slow_clk))
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return PTR_ERR(slow_clk);
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clk_name[1] += channel;
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clk = of_clk_get_by_name(np->parent, clk_name);
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if (IS_ERR(clk))
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clk = of_clk_get_by_name(np->parent, "t0_clk");
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if (IS_ERR(clk))
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return PTR_ERR(clk);
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match = of_match_node(atmel_tcb_of_match, np->parent);
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config = match->data;
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if (config->has_gclk) {
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gclk = of_clk_get_by_name(np->parent, "gclk");
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if (IS_ERR(gclk))
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return PTR_ERR(gclk);
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}
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tcbpwm = devm_kzalloc(&pdev->dev, sizeof(*tcbpwm), GFP_KERNEL);
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if (tcbpwm == NULL) {
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err = -ENOMEM;
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goto err_slow_clk;
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}
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tcbpwm->chip.dev = &pdev->dev;
|
|
tcbpwm->chip.ops = &atmel_tcb_pwm_ops;
|
|
tcbpwm->chip.npwm = NPWM;
|
|
tcbpwm->channel = channel;
|
|
tcbpwm->regmap = regmap;
|
|
tcbpwm->clk = clk;
|
|
tcbpwm->gclk = gclk;
|
|
tcbpwm->slow_clk = slow_clk;
|
|
tcbpwm->width = config->counter_width;
|
|
|
|
err = clk_prepare_enable(slow_clk);
|
|
if (err)
|
|
goto err_slow_clk;
|
|
|
|
spin_lock_init(&tcbpwm->lock);
|
|
|
|
err = pwmchip_add(&tcbpwm->chip);
|
|
if (err < 0)
|
|
goto err_disable_clk;
|
|
|
|
platform_set_drvdata(pdev, tcbpwm);
|
|
|
|
return 0;
|
|
|
|
err_disable_clk:
|
|
clk_disable_unprepare(tcbpwm->slow_clk);
|
|
|
|
err_slow_clk:
|
|
clk_put(slow_clk);
|
|
|
|
return err;
|
|
}
|
|
|
|
static int atmel_tcb_pwm_remove(struct platform_device *pdev)
|
|
{
|
|
struct atmel_tcb_pwm_chip *tcbpwm = platform_get_drvdata(pdev);
|
|
|
|
pwmchip_remove(&tcbpwm->chip);
|
|
|
|
clk_disable_unprepare(tcbpwm->slow_clk);
|
|
clk_put(tcbpwm->slow_clk);
|
|
clk_put(tcbpwm->clk);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const struct of_device_id atmel_tcb_pwm_dt_ids[] = {
|
|
{ .compatible = "atmel,tcb-pwm", },
|
|
{ /* sentinel */ }
|
|
};
|
|
MODULE_DEVICE_TABLE(of, atmel_tcb_pwm_dt_ids);
|
|
|
|
#ifdef CONFIG_PM_SLEEP
|
|
static int atmel_tcb_pwm_suspend(struct device *dev)
|
|
{
|
|
struct atmel_tcb_pwm_chip *tcbpwm = dev_get_drvdata(dev);
|
|
struct atmel_tcb_channel *chan = &tcbpwm->bkup;
|
|
unsigned int channel = tcbpwm->channel;
|
|
|
|
regmap_read(tcbpwm->regmap, ATMEL_TC_REG(channel, CMR), &chan->cmr);
|
|
regmap_read(tcbpwm->regmap, ATMEL_TC_REG(channel, RA), &chan->ra);
|
|
regmap_read(tcbpwm->regmap, ATMEL_TC_REG(channel, RB), &chan->rb);
|
|
regmap_read(tcbpwm->regmap, ATMEL_TC_REG(channel, RC), &chan->rc);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int atmel_tcb_pwm_resume(struct device *dev)
|
|
{
|
|
struct atmel_tcb_pwm_chip *tcbpwm = dev_get_drvdata(dev);
|
|
struct atmel_tcb_channel *chan = &tcbpwm->bkup;
|
|
unsigned int channel = tcbpwm->channel;
|
|
|
|
regmap_write(tcbpwm->regmap, ATMEL_TC_REG(channel, CMR), chan->cmr);
|
|
regmap_write(tcbpwm->regmap, ATMEL_TC_REG(channel, RA), chan->ra);
|
|
regmap_write(tcbpwm->regmap, ATMEL_TC_REG(channel, RB), chan->rb);
|
|
regmap_write(tcbpwm->regmap, ATMEL_TC_REG(channel, RC), chan->rc);
|
|
|
|
if (chan->enabled)
|
|
regmap_write(tcbpwm->regmap,
|
|
ATMEL_TC_CLKEN | ATMEL_TC_SWTRG,
|
|
ATMEL_TC_REG(channel, CCR));
|
|
|
|
return 0;
|
|
}
|
|
#endif
|
|
|
|
static SIMPLE_DEV_PM_OPS(atmel_tcb_pwm_pm_ops, atmel_tcb_pwm_suspend,
|
|
atmel_tcb_pwm_resume);
|
|
|
|
static struct platform_driver atmel_tcb_pwm_driver = {
|
|
.driver = {
|
|
.name = "atmel-tcb-pwm",
|
|
.of_match_table = atmel_tcb_pwm_dt_ids,
|
|
.pm = &atmel_tcb_pwm_pm_ops,
|
|
},
|
|
.probe = atmel_tcb_pwm_probe,
|
|
.remove = atmel_tcb_pwm_remove,
|
|
};
|
|
module_platform_driver(atmel_tcb_pwm_driver);
|
|
|
|
MODULE_AUTHOR("Boris BREZILLON <b.brezillon@overkiz.com>");
|
|
MODULE_DESCRIPTION("Atmel Timer Counter Pulse Width Modulation Driver");
|
|
MODULE_LICENSE("GPL v2");
|