291 строка
8.4 KiB
C
291 строка
8.4 KiB
C
/*
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* Copyright (c) 2009 Daniel Mack <daniel@caiaq.de>
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* Copyright (C) 2010 Freescale Semiconductor, Inc.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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* for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software Foundation,
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* Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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*/
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#include <linux/platform_device.h>
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#include <linux/io.h>
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#include <mach/hardware.h>
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#include <mach/mxc_ehci.h>
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#define USBCTRL_OTGBASE_OFFSET 0x600
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#define MX31_OTG_SIC_SHIFT 29
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#define MX31_OTG_SIC_MASK (0x3 << MX31_OTG_SIC_SHIFT)
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#define MX31_OTG_PM_BIT (1 << 24)
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#define MX31_H2_SIC_SHIFT 21
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#define MX31_H2_SIC_MASK (0x3 << MX31_H2_SIC_SHIFT)
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#define MX31_H2_PM_BIT (1 << 16)
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#define MX31_H2_DT_BIT (1 << 5)
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#define MX31_H1_SIC_SHIFT 13
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#define MX31_H1_SIC_MASK (0x3 << MX31_H1_SIC_SHIFT)
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#define MX31_H1_PM_BIT (1 << 8)
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#define MX31_H1_DT_BIT (1 << 4)
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#define MX35_OTG_SIC_SHIFT 29
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#define MX35_OTG_SIC_MASK (0x3 << MX35_OTG_SIC_SHIFT)
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#define MX35_OTG_PM_BIT (1 << 24)
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#define MX35_H1_SIC_SHIFT 21
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#define MX35_H1_SIC_MASK (0x3 << MX35_H1_SIC_SHIFT)
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#define MX35_H1_PM_BIT (1 << 8)
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#define MX35_H1_IPPUE_UP_BIT (1 << 7)
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#define MX35_H1_IPPUE_DOWN_BIT (1 << 6)
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#define MX35_H1_TLL_BIT (1 << 5)
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#define MX35_H1_USBTE_BIT (1 << 4)
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#define MXC_OTG_OFFSET 0
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#define MXC_H1_OFFSET 0x200
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/* USB_CTRL */
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#define MXC_OTG_UCTRL_OWIE_BIT (1 << 27) /* OTG wakeup intr enable */
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#define MXC_OTG_UCTRL_OPM_BIT (1 << 24) /* OTG power mask */
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#define MXC_H1_UCTRL_H1UIE_BIT (1 << 12) /* Host1 ULPI interrupt enable */
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#define MXC_H1_UCTRL_H1WIE_BIT (1 << 11) /* HOST1 wakeup intr enable */
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#define MXC_H1_UCTRL_H1PM_BIT (1 << 8) /* HOST1 power mask */
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/* USB_PHY_CTRL_FUNC */
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#define MXC_OTG_PHYCTRL_OC_DIS_BIT (1 << 8) /* OTG Disable Overcurrent Event */
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#define MXC_H1_OC_DIS_BIT (1 << 5) /* UH1 Disable Overcurrent Event */
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#define MXC_USBCMD_OFFSET 0x140
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/* USBCMD */
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#define MXC_UCMD_ITC_NO_THRESHOLD_MASK (~(0xff << 16)) /* Interrupt Threshold Control */
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int mxc_initialize_usb_hw(int port, unsigned int flags)
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{
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unsigned int v;
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#ifdef CONFIG_ARCH_MX3
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if (cpu_is_mx31()) {
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v = readl(MX31_IO_ADDRESS(MX31_OTG_BASE_ADDR +
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USBCTRL_OTGBASE_OFFSET));
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switch (port) {
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case 0: /* OTG port */
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v &= ~(MX31_OTG_SIC_MASK | MX31_OTG_PM_BIT);
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v |= (flags & MXC_EHCI_INTERFACE_MASK)
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<< MX31_OTG_SIC_SHIFT;
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if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
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v |= MX31_OTG_PM_BIT;
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break;
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case 1: /* H1 port */
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v &= ~(MX31_H1_SIC_MASK | MX31_H1_PM_BIT | MX31_H1_DT_BIT);
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v |= (flags & MXC_EHCI_INTERFACE_MASK)
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<< MX31_H1_SIC_SHIFT;
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if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
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v |= MX31_H1_PM_BIT;
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if (!(flags & MXC_EHCI_TTL_ENABLED))
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v |= MX31_H1_DT_BIT;
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break;
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case 2: /* H2 port */
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v &= ~(MX31_H2_SIC_MASK | MX31_H2_PM_BIT | MX31_H2_DT_BIT);
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v |= (flags & MXC_EHCI_INTERFACE_MASK)
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<< MX31_H2_SIC_SHIFT;
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if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
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v |= MX31_H2_PM_BIT;
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if (!(flags & MXC_EHCI_TTL_ENABLED))
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v |= MX31_H2_DT_BIT;
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break;
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default:
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return -EINVAL;
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}
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writel(v, MX31_IO_ADDRESS(MX31_OTG_BASE_ADDR +
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USBCTRL_OTGBASE_OFFSET));
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return 0;
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}
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if (cpu_is_mx35()) {
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v = readl(MX35_IO_ADDRESS(MX35_OTG_BASE_ADDR +
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USBCTRL_OTGBASE_OFFSET));
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switch (port) {
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case 0: /* OTG port */
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v &= ~(MX35_OTG_SIC_MASK | MX35_OTG_PM_BIT);
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v |= (flags & MXC_EHCI_INTERFACE_MASK)
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<< MX35_OTG_SIC_SHIFT;
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if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
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v |= MX35_OTG_PM_BIT;
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break;
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case 1: /* H1 port */
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v &= ~(MX35_H1_SIC_MASK | MX35_H1_PM_BIT | MX35_H1_TLL_BIT |
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MX35_H1_USBTE_BIT | MX35_H1_IPPUE_DOWN_BIT | MX35_H1_IPPUE_UP_BIT);
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v |= (flags & MXC_EHCI_INTERFACE_MASK)
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<< MX35_H1_SIC_SHIFT;
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if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
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v |= MX35_H1_PM_BIT;
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if (!(flags & MXC_EHCI_TTL_ENABLED))
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v |= MX35_H1_TLL_BIT;
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if (flags & MXC_EHCI_INTERNAL_PHY)
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v |= MX35_H1_USBTE_BIT;
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if (flags & MXC_EHCI_IPPUE_DOWN)
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v |= MX35_H1_IPPUE_DOWN_BIT;
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if (flags & MXC_EHCI_IPPUE_UP)
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v |= MX35_H1_IPPUE_UP_BIT;
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break;
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default:
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return -EINVAL;
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}
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writel(v, MX35_IO_ADDRESS(MX35_OTG_BASE_ADDR +
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USBCTRL_OTGBASE_OFFSET));
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return 0;
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}
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#endif /* CONFIG_ARCH_MX3 */
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#ifdef CONFIG_MACH_MX27
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if (cpu_is_mx27()) {
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/* On i.MX27 we can use the i.MX31 USBCTRL bits, they
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* are identical
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*/
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v = readl(MX27_IO_ADDRESS(MX27_OTG_BASE_ADDR +
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USBCTRL_OTGBASE_OFFSET));
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switch (port) {
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case 0: /* OTG port */
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v &= ~(MX31_OTG_SIC_MASK | MX31_OTG_PM_BIT);
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v |= (flags & MXC_EHCI_INTERFACE_MASK)
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<< MX31_OTG_SIC_SHIFT;
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if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
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v |= MX31_OTG_PM_BIT;
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break;
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case 1: /* H1 port */
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v &= ~(MX31_H1_SIC_MASK | MX31_H1_PM_BIT | MX31_H1_DT_BIT);
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v |= (flags & MXC_EHCI_INTERFACE_MASK)
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<< MX31_H1_SIC_SHIFT;
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if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
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v |= MX31_H1_PM_BIT;
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if (!(flags & MXC_EHCI_TTL_ENABLED))
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v |= MX31_H1_DT_BIT;
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break;
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case 2: /* H2 port */
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v &= ~(MX31_H2_SIC_MASK | MX31_H2_PM_BIT | MX31_H2_DT_BIT);
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v |= (flags & MXC_EHCI_INTERFACE_MASK)
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<< MX31_H2_SIC_SHIFT;
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if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
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v |= MX31_H2_PM_BIT;
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if (!(flags & MXC_EHCI_TTL_ENABLED))
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v |= MX31_H2_DT_BIT;
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break;
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default:
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return -EINVAL;
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}
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writel(v, MX27_IO_ADDRESS(MX27_OTG_BASE_ADDR +
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USBCTRL_OTGBASE_OFFSET));
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return 0;
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}
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#endif /* CONFIG_MACH_MX27 */
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#ifdef CONFIG_ARCH_MX51
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if (cpu_is_mx51()) {
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void __iomem *usb_base;
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u32 usbotg_base;
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u32 usbother_base;
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int ret = 0;
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usb_base = ioremap(MX51_OTG_BASE_ADDR, SZ_4K);
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switch (port) {
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case 0: /* OTG port */
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usbotg_base = usb_base + MXC_OTG_OFFSET;
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break;
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case 1: /* Host 1 port */
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usbotg_base = usb_base + MXC_H1_OFFSET;
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break;
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default:
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printk(KERN_ERR"%s no such port %d\n", __func__, port);
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ret = -ENOENT;
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goto error;
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}
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usbother_base = usb_base + MX5_USBOTHER_REGS_OFFSET;
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switch (port) {
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case 0: /*OTG port */
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if (flags & MXC_EHCI_INTERNAL_PHY) {
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v = __raw_readl(usbother_base + MXC_USB_PHY_CTR_FUNC_OFFSET);
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if (flags & MXC_EHCI_POWER_PINS_ENABLED)
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v |= (MXC_OTG_PHYCTRL_OC_DIS_BIT | MXC_OTG_UCTRL_OPM_BIT); /* OC/USBPWR is not used */
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else
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v &= ~(MXC_OTG_PHYCTRL_OC_DIS_BIT | MXC_OTG_UCTRL_OPM_BIT); /* OC/USBPWR is used */
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__raw_writel(v, usbother_base + MXC_USB_PHY_CTR_FUNC_OFFSET);
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v = __raw_readl(usbother_base + MXC_USBCTRL_OFFSET);
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if (flags & MXC_EHCI_WAKEUP_ENABLED)
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v |= MXC_OTG_UCTRL_OWIE_BIT;/* OTG wakeup enable */
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else
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v &= ~MXC_OTG_UCTRL_OWIE_BIT;/* OTG wakeup disable */
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__raw_writel(v, usbother_base + MXC_USBCTRL_OFFSET);
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}
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break;
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case 1: /* Host 1 */
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/*Host ULPI */
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v = __raw_readl(usbother_base + MXC_USBCTRL_OFFSET);
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if (flags & MXC_EHCI_WAKEUP_ENABLED)
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v &= ~(MXC_H1_UCTRL_H1WIE_BIT | MXC_H1_UCTRL_H1UIE_BIT);/* HOST1 wakeup/ULPI intr disable */
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else
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v &= ~(MXC_H1_UCTRL_H1WIE_BIT | MXC_H1_UCTRL_H1UIE_BIT);/* HOST1 wakeup/ULPI intr disable */
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if (flags & MXC_EHCI_POWER_PINS_ENABLED)
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v &= ~MXC_H1_UCTRL_H1PM_BIT; /* HOST1 power mask used*/
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else
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v |= MXC_H1_UCTRL_H1PM_BIT; /* HOST1 power mask used*/
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__raw_writel(v, usbother_base + MXC_USBCTRL_OFFSET);
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v = __raw_readl(usbother_base + MXC_USB_PHY_CTR_FUNC_OFFSET);
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if (flags & MXC_EHCI_POWER_PINS_ENABLED)
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v &= ~MXC_H1_OC_DIS_BIT; /* OC is used */
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else
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v |= MXC_H1_OC_DIS_BIT; /* OC is not used */
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__raw_writel(v, usbother_base + MXC_USB_PHY_CTR_FUNC_OFFSET);
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v = __raw_readl(usbotg_base + MXC_USBCMD_OFFSET);
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if (flags & MXC_EHCI_ITC_NO_THRESHOLD)
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/* Interrupt Threshold Control:Immediate (no threshold) */
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v &= MXC_UCMD_ITC_NO_THRESHOLD_MASK;
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__raw_writel(v, usbotg_base + MXC_USBCMD_OFFSET);
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break;
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}
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error:
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iounmap(usb_base);
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return ret;
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}
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#endif
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printk(KERN_WARNING
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"%s() unable to setup USBCONTROL for this CPU\n", __func__);
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return -EINVAL;
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}
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EXPORT_SYMBOL(mxc_initialize_usb_hw);
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