Ville Syrjälä 46c06a30df drm/i915: Kill pipestat[] cache ... Caching the PIPESTAT enable bits has been deemed pointless. Just read them from the register itself. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Jani Nikula <jani.nikula@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>		2013-02-21 14:01:12 +01:00
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drm	drm/i915: Kill pipestat[] cache	2013-02-21 14:01:12 +01:00
stub	…
vga	fbcon: fix locking harder	2013-02-08 12:02:43 +10:00
Makefile	…