91 строка
2.2 KiB
C
91 строка
2.2 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* AMD ALSA SoC PDM Driver
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*
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* Copyright 2020 Advanced Micro Devices, Inc.
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*/
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#include "rn_chip_offset_byte.h"
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#define ACP_DEVS 3
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#define ACP_PHY_BASE_ADDRESS 0x1240000
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#define ACP_REG_START 0x1240000
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#define ACP_REG_END 0x1250200
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#define ACP_DEVICE_ID 0x15E2
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#define ACP_POWER_ON 0x00
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#define ACP_POWER_ON_IN_PROGRESS 0x01
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#define ACP_POWER_OFF 0x02
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#define ACP_POWER_OFF_IN_PROGRESS 0x03
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#define ACP_SOFT_RESET_SOFTRESET_AUDDONE_MASK 0x00010001
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#define ACP_PGFSM_CNTL_POWER_ON_MASK 0x01
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#define ACP_PGFSM_CNTL_POWER_OFF_MASK 0x00
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#define ACP_PGFSM_STATUS_MASK 0x03
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#define ACP_POWERED_ON 0x00
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#define ACP_POWER_ON_IN_PROGRESS 0x01
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#define ACP_POWERED_OFF 0x02
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#define ACP_POWER_OFF_IN_PROGRESS 0x03
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#define ACP_ERROR_MASK 0x20000000
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#define ACP_EXT_INTR_STAT_CLEAR_MASK 0xFFFFFFFF
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#define PDM_DMA_STAT 0x10
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#define PDM_DMA_INTR_MASK 0x10000
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#define ACP_ERROR_STAT 29
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#define PDM_DECIMATION_FACTOR 0x2
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#define ACP_PDM_CLK_FREQ_MASK 0x07
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#define ACP_WOV_MISC_CTRL_MASK 0x10
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#define ACP_PDM_ENABLE 0x01
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#define ACP_PDM_DISABLE 0x00
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#define ACP_PDM_DMA_EN_STATUS 0x02
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#define TWO_CH 0x02
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#define DELAY_US 5
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#define ACP_COUNTER 20000
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/* time in ms for runtime suspend delay */
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#define ACP_SUSPEND_DELAY_MS 2000
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#define ACP_SRAM_PTE_OFFSET 0x02050000
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#define PAGE_SIZE_4K_ENABLE 0x2
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#define MEM_WINDOW_START 0x4000000
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#define CAPTURE_MIN_NUM_PERIODS 4
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#define CAPTURE_MAX_NUM_PERIODS 4
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#define CAPTURE_MAX_PERIOD_SIZE 8192
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#define CAPTURE_MIN_PERIOD_SIZE 4096
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#define MAX_BUFFER (CAPTURE_MAX_PERIOD_SIZE * CAPTURE_MAX_NUM_PERIODS)
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#define MIN_BUFFER MAX_BUFFER
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#define ACP_DMIC_AUTO -1
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struct pdm_dev_data {
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u32 pdm_irq;
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void __iomem *acp_base;
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struct snd_pcm_substream *capture_stream;
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};
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struct pdm_stream_instance {
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u16 num_pages;
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u16 channels;
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dma_addr_t dma_addr;
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u64 bytescount;
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void __iomem *acp_base;
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};
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union acp_pdm_dma_count {
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struct {
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u32 low;
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u32 high;
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} bcount;
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u64 bytescount;
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};
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static inline u32 rn_readl(void __iomem *base_addr)
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{
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return readl(base_addr - ACP_PHY_BASE_ADDRESS);
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}
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static inline void rn_writel(u32 val, void __iomem *base_addr)
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{
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writel(val, base_addr - ACP_PHY_BASE_ADDRESS);
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}
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