Kefeng Wang 48084c3595 riscv: perf: RISCV_BASE_PMU should be independent ... Selecting PERF_EVENTS without selecting RISCV_BASE_PMU results in a build error. Signed-off-by: Kefeng Wang <wangkefeng.wang@huawei.com> [Palmer: commit text] Fixes: 178e9fc47aae("perf: riscv: preliminary RISC-V support") Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>		2020-05-12 16:21:46 -07:00
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boot	RISC-V Patches for the 5.7 Merge Window, Part 1	2020-04-09 10:51:30 -07:00
configs	RISC-V Patches for the 5.7 Merge Window, Part 1	2020-04-09 10:51:30 -07:00
include	riscv: perf: RISCV_BASE_PMU should be independent	2020-05-12 16:21:46 -07:00
kernel	riscv: perf: RISCV_BASE_PMU should be independent	2020-05-12 16:21:46 -07:00
lib	RISC-V Patches for the 5.7 Merge Window, Part 1	2020-04-09 10:51:30 -07:00
mm	RISC-V: Remove unused code from STRICT_KERNEL_RWX	2020-05-05 17:02:14 -07:00
net	riscv, bpf: Fix offset range checking for auipc+jalr on RV64	2020-04-08 00:53:41 +02:00
Kbuild	riscv: add arch/riscv/Kbuild	2019-08-30 17:34:00 -07:00
Kconfig	riscv: select ARCH_HAS_STRICT_KERNEL_RWX only if MMU	2020-04-24 11:40:40 -07:00
Kconfig.debug	RISC-V: Remove EARLY_PRINTK support	2018-12-17 10:23:46 -08:00
Kconfig.socs	RISC-V Patches for the 5.7 Merge Window, Part 1	2020-04-09 10:51:30 -07:00
Makefile	RISC-V Patches for the 5.7 Merge Window, Part 1	2020-04-09 10:51:30 -07:00