460 строки
15 KiB
C
460 строки
15 KiB
C
/*
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* linux/drivers/mmc/host/mmci.h - ARM PrimeCell MMCI PL180/1 driver
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*
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* Copyright (C) 2003 Deep Blue Solutions, Ltd, All Rights Reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#define MMCIPOWER 0x000
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#define MCI_PWR_OFF 0x00
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#define MCI_PWR_UP 0x02
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#define MCI_PWR_ON 0x03
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#define MCI_OD (1 << 6)
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#define MCI_ROD (1 << 7)
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/*
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* The ST Micro version does not have ROD and reuse the voltage registers for
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* direction settings.
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*/
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#define MCI_ST_DATA2DIREN (1 << 2)
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#define MCI_ST_CMDDIREN (1 << 3)
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#define MCI_ST_DATA0DIREN (1 << 4)
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#define MCI_ST_DATA31DIREN (1 << 5)
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#define MCI_ST_FBCLKEN (1 << 7)
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#define MCI_ST_DATA74DIREN (1 << 8)
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/*
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* The STM32 sdmmc does not have PWR_UP/OD/ROD
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* and uses the power register for
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*/
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#define MCI_STM32_PWR_CYC 0x02
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#define MCI_STM32_VSWITCH BIT(2)
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#define MCI_STM32_VSWITCHEN BIT(3)
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#define MCI_STM32_DIRPOL BIT(4)
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#define MMCICLOCK 0x004
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#define MCI_CLK_ENABLE (1 << 8)
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#define MCI_CLK_PWRSAVE (1 << 9)
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#define MCI_CLK_BYPASS (1 << 10)
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#define MCI_4BIT_BUS (1 << 11)
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/*
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* 8bit wide buses, hardware flow contronl, negative edges and clock inversion
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* supported in ST Micro U300 and Ux500 versions
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*/
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#define MCI_ST_8BIT_BUS (1 << 12)
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#define MCI_ST_U300_HWFCEN (1 << 13)
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#define MCI_ST_UX500_NEG_EDGE (1 << 13)
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#define MCI_ST_UX500_HWFCEN (1 << 14)
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#define MCI_ST_UX500_CLK_INV (1 << 15)
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/* Modified PL180 on Versatile Express platform */
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#define MCI_ARM_HWFCEN (1 << 12)
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/* Modified on Qualcomm Integrations */
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#define MCI_QCOM_CLK_WIDEBUS_8 (BIT(10) | BIT(11))
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#define MCI_QCOM_CLK_FLOWENA BIT(12)
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#define MCI_QCOM_CLK_INVERTOUT BIT(13)
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/* select in latch data and command in */
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#define MCI_QCOM_CLK_SELECT_IN_FBCLK BIT(15)
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#define MCI_QCOM_CLK_SELECT_IN_DDR_MODE (BIT(14) | BIT(15))
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/* Modified on STM32 sdmmc */
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#define MCI_STM32_CLK_CLKDIV_MSK GENMASK(9, 0)
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#define MCI_STM32_CLK_WIDEBUS_4 BIT(14)
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#define MCI_STM32_CLK_WIDEBUS_8 BIT(15)
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#define MCI_STM32_CLK_NEGEDGE BIT(16)
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#define MCI_STM32_CLK_HWFCEN BIT(17)
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#define MCI_STM32_CLK_DDR BIT(18)
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#define MCI_STM32_CLK_BUSSPEED BIT(19)
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#define MCI_STM32_CLK_SEL_MSK GENMASK(21, 20)
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#define MCI_STM32_CLK_SELCK (0 << 20)
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#define MCI_STM32_CLK_SELCKIN (1 << 20)
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#define MCI_STM32_CLK_SELFBCK (2 << 20)
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#define MMCIARGUMENT 0x008
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/* The command register controls the Command Path State Machine (CPSM) */
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#define MMCICOMMAND 0x00c
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#define MCI_CPSM_RESPONSE BIT(6)
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#define MCI_CPSM_LONGRSP BIT(7)
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#define MCI_CPSM_INTERRUPT BIT(8)
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#define MCI_CPSM_PENDING BIT(9)
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#define MCI_CPSM_ENABLE BIT(10)
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/* Command register flag extenstions in the ST Micro versions */
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#define MCI_CPSM_ST_SDIO_SUSP BIT(11)
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#define MCI_CPSM_ST_ENCMD_COMPL BIT(12)
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#define MCI_CPSM_ST_NIEN BIT(13)
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#define MCI_CPSM_ST_CE_ATACMD BIT(14)
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/* Command register flag extensions in the Qualcomm versions */
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#define MCI_CPSM_QCOM_PROGENA BIT(11)
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#define MCI_CPSM_QCOM_DATCMD BIT(12)
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#define MCI_CPSM_QCOM_MCIABORT BIT(13)
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#define MCI_CPSM_QCOM_CCSENABLE BIT(14)
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#define MCI_CPSM_QCOM_CCSDISABLE BIT(15)
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#define MCI_CPSM_QCOM_AUTO_CMD19 BIT(16)
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#define MCI_CPSM_QCOM_AUTO_CMD21 BIT(21)
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/* Command register in STM32 sdmmc versions */
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#define MCI_CPSM_STM32_CMDTRANS BIT(6)
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#define MCI_CPSM_STM32_CMDSTOP BIT(7)
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#define MCI_CPSM_STM32_WAITRESP_MASK GENMASK(9, 8)
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#define MCI_CPSM_STM32_NORSP (0 << 8)
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#define MCI_CPSM_STM32_SRSP_CRC (1 << 8)
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#define MCI_CPSM_STM32_SRSP (2 << 8)
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#define MCI_CPSM_STM32_LRSP_CRC (3 << 8)
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#define MCI_CPSM_STM32_ENABLE BIT(12)
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#define MMCIRESPCMD 0x010
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#define MMCIRESPONSE0 0x014
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#define MMCIRESPONSE1 0x018
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#define MMCIRESPONSE2 0x01c
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#define MMCIRESPONSE3 0x020
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#define MMCIDATATIMER 0x024
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#define MMCIDATALENGTH 0x028
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/* The data control register controls the Data Path State Machine (DPSM) */
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#define MMCIDATACTRL 0x02c
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#define MCI_DPSM_ENABLE BIT(0)
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#define MCI_DPSM_DIRECTION BIT(1)
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#define MCI_DPSM_MODE BIT(2)
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#define MCI_DPSM_DMAENABLE BIT(3)
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#define MCI_DPSM_BLOCKSIZE BIT(4)
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/* Control register extensions in the ST Micro U300 and Ux500 versions */
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#define MCI_DPSM_ST_RWSTART BIT(8)
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#define MCI_DPSM_ST_RWSTOP BIT(9)
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#define MCI_DPSM_ST_RWMOD BIT(10)
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#define MCI_DPSM_ST_SDIOEN BIT(11)
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/* Control register extensions in the ST Micro Ux500 versions */
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#define MCI_DPSM_ST_DMAREQCTL BIT(12)
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#define MCI_DPSM_ST_DBOOTMODEEN BIT(13)
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#define MCI_DPSM_ST_BUSYMODE BIT(14)
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#define MCI_DPSM_ST_DDRMODE BIT(15)
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/* Control register extensions in the Qualcomm versions */
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#define MCI_DPSM_QCOM_DATA_PEND BIT(17)
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#define MCI_DPSM_QCOM_RX_DATA_PEND BIT(20)
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/* Control register extensions in STM32 versions */
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#define MCI_DPSM_STM32_MODE_BLOCK (0 << 2)
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#define MCI_DPSM_STM32_MODE_SDIO (1 << 2)
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#define MCI_DPSM_STM32_MODE_STREAM (2 << 2)
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#define MCI_DPSM_STM32_MODE_BLOCK_STOP (3 << 2)
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#define MMCIDATACNT 0x030
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#define MMCISTATUS 0x034
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#define MCI_CMDCRCFAIL (1 << 0)
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#define MCI_DATACRCFAIL (1 << 1)
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#define MCI_CMDTIMEOUT (1 << 2)
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#define MCI_DATATIMEOUT (1 << 3)
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#define MCI_TXUNDERRUN (1 << 4)
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#define MCI_RXOVERRUN (1 << 5)
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#define MCI_CMDRESPEND (1 << 6)
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#define MCI_CMDSENT (1 << 7)
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#define MCI_DATAEND (1 << 8)
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#define MCI_STARTBITERR (1 << 9)
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#define MCI_DATABLOCKEND (1 << 10)
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#define MCI_CMDACTIVE (1 << 11)
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#define MCI_TXACTIVE (1 << 12)
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#define MCI_RXACTIVE (1 << 13)
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#define MCI_TXFIFOHALFEMPTY (1 << 14)
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#define MCI_RXFIFOHALFFULL (1 << 15)
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#define MCI_TXFIFOFULL (1 << 16)
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#define MCI_RXFIFOFULL (1 << 17)
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#define MCI_TXFIFOEMPTY (1 << 18)
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#define MCI_RXFIFOEMPTY (1 << 19)
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#define MCI_TXDATAAVLBL (1 << 20)
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#define MCI_RXDATAAVLBL (1 << 21)
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/* Extended status bits for the ST Micro variants */
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#define MCI_ST_SDIOIT (1 << 22)
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#define MCI_ST_CEATAEND (1 << 23)
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#define MCI_ST_CARDBUSY (1 << 24)
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/* Extended status bits for the STM32 variants */
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#define MCI_STM32_BUSYD0 BIT(20)
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#define MMCICLEAR 0x038
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#define MCI_CMDCRCFAILCLR (1 << 0)
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#define MCI_DATACRCFAILCLR (1 << 1)
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#define MCI_CMDTIMEOUTCLR (1 << 2)
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#define MCI_DATATIMEOUTCLR (1 << 3)
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#define MCI_TXUNDERRUNCLR (1 << 4)
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#define MCI_RXOVERRUNCLR (1 << 5)
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#define MCI_CMDRESPENDCLR (1 << 6)
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#define MCI_CMDSENTCLR (1 << 7)
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#define MCI_DATAENDCLR (1 << 8)
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#define MCI_STARTBITERRCLR (1 << 9)
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#define MCI_DATABLOCKENDCLR (1 << 10)
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/* Extended status bits for the ST Micro variants */
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#define MCI_ST_SDIOITC (1 << 22)
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#define MCI_ST_CEATAENDC (1 << 23)
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#define MCI_ST_BUSYENDC (1 << 24)
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#define MMCIMASK0 0x03c
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#define MCI_CMDCRCFAILMASK (1 << 0)
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#define MCI_DATACRCFAILMASK (1 << 1)
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#define MCI_CMDTIMEOUTMASK (1 << 2)
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#define MCI_DATATIMEOUTMASK (1 << 3)
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#define MCI_TXUNDERRUNMASK (1 << 4)
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#define MCI_RXOVERRUNMASK (1 << 5)
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#define MCI_CMDRESPENDMASK (1 << 6)
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#define MCI_CMDSENTMASK (1 << 7)
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#define MCI_DATAENDMASK (1 << 8)
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#define MCI_STARTBITERRMASK (1 << 9)
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#define MCI_DATABLOCKENDMASK (1 << 10)
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#define MCI_CMDACTIVEMASK (1 << 11)
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#define MCI_TXACTIVEMASK (1 << 12)
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#define MCI_RXACTIVEMASK (1 << 13)
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#define MCI_TXFIFOHALFEMPTYMASK (1 << 14)
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#define MCI_RXFIFOHALFFULLMASK (1 << 15)
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#define MCI_TXFIFOFULLMASK (1 << 16)
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#define MCI_RXFIFOFULLMASK (1 << 17)
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#define MCI_TXFIFOEMPTYMASK (1 << 18)
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#define MCI_RXFIFOEMPTYMASK (1 << 19)
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#define MCI_TXDATAAVLBLMASK (1 << 20)
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#define MCI_RXDATAAVLBLMASK (1 << 21)
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/* Extended status bits for the ST Micro variants */
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#define MCI_ST_SDIOITMASK (1 << 22)
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#define MCI_ST_CEATAENDMASK (1 << 23)
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#define MCI_ST_BUSYENDMASK (1 << 24)
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/* Extended status bits for the STM32 variants */
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#define MCI_STM32_BUSYD0ENDMASK BIT(21)
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#define MMCIMASK1 0x040
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#define MMCIFIFOCNT 0x048
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#define MMCIFIFO 0x080 /* to 0x0bc */
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/* STM32 sdmmc registers for IDMA (Internal DMA) */
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#define MMCI_STM32_IDMACTRLR 0x050
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#define MMCI_STM32_IDMAEN BIT(0)
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#define MMCI_STM32_IDMALLIEN BIT(1)
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#define MMCI_STM32_IDMABSIZER 0x054
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#define MMCI_STM32_IDMABNDT_SHIFT 5
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#define MMCI_STM32_IDMABNDT_MASK GENMASK(12, 5)
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#define MMCI_STM32_IDMABASE0R 0x058
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#define MMCI_STM32_IDMALAR 0x64
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#define MMCI_STM32_IDMALA_MASK GENMASK(13, 0)
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#define MMCI_STM32_ABR BIT(29)
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#define MMCI_STM32_ULS BIT(30)
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#define MMCI_STM32_ULA BIT(31)
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#define MMCI_STM32_IDMABAR 0x68
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#define MCI_IRQENABLE \
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(MCI_CMDCRCFAILMASK | MCI_DATACRCFAILMASK | MCI_CMDTIMEOUTMASK | \
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MCI_DATATIMEOUTMASK | MCI_TXUNDERRUNMASK | MCI_RXOVERRUNMASK | \
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MCI_CMDRESPENDMASK | MCI_CMDSENTMASK)
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/* These interrupts are directed to IRQ1 when two IRQ lines are available */
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#define MCI_IRQ_PIO_MASK \
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(MCI_RXFIFOHALFFULLMASK | MCI_RXDATAAVLBLMASK | \
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MCI_TXFIFOHALFEMPTYMASK)
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#define MCI_IRQ_PIO_STM32_MASK \
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(MCI_RXFIFOHALFFULLMASK | MCI_TXFIFOHALFEMPTYMASK)
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#define NR_SG 128
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#define MMCI_PINCTRL_STATE_OPENDRAIN "opendrain"
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struct clk;
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struct dma_chan;
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struct mmci_host;
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/**
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* struct variant_data - MMCI variant-specific quirks
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* @clkreg: default value for MCICLOCK register
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* @clkreg_enable: enable value for MMCICLOCK register
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* @clkreg_8bit_bus_enable: enable value for 8 bit bus
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* @clkreg_neg_edge_enable: enable value for inverted data/cmd output
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* @cmdreg_cpsm_enable: enable value for CPSM
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* @cmdreg_lrsp_crc: enable value for long response with crc
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* @cmdreg_srsp_crc: enable value for short response with crc
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* @cmdreg_srsp: enable value for short response without crc
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* @cmdreg_stop: enable value for stop and abort transmission
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* @datalength_bits: number of bits in the MMCIDATALENGTH register
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* @fifosize: number of bytes that can be written when MMCI_TXFIFOEMPTY
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* is asserted (likewise for RX)
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* @fifohalfsize: number of bytes that can be written when MCI_TXFIFOHALFEMPTY
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* is asserted (likewise for RX)
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* @data_cmd_enable: enable value for data commands.
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* @st_sdio: enable ST specific SDIO logic
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* @st_clkdiv: true if using a ST-specific clock divider algorithm
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* @stm32_clkdiv: true if using a STM32-specific clock divider algorithm
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* @datactrl_mask_ddrmode: ddr mode mask in datactrl register.
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* @datactrl_mask_sdio: SDIO enable mask in datactrl register
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* @datactrl_blksz: block size in power of two
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* @datactrl_first: true if data must be setup before send command
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* @datacnt_useless: true if you could not use datacnt register to read
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* remaining data
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* @pwrreg_powerup: power up value for MMCIPOWER register
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* @f_max: maximum clk frequency supported by the controller.
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* @signal_direction: input/out direction of bus signals can be indicated
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* @pwrreg_clkgate: MMCIPOWER register must be used to gate the clock
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* @busy_detect: true if the variant supports busy detection on DAT0.
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* @busy_dpsm_flag: bitmask enabling busy detection in the DPSM
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* @busy_detect_flag: bitmask identifying the bit in the MMCISTATUS register
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* indicating that the card is busy
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* @busy_detect_mask: bitmask identifying the bit in the MMCIMASK0 to mask for
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* getting busy end detection interrupts
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* @pwrreg_nopower: bits in MMCIPOWER don't controls ext. power supply
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* @explicit_mclk_control: enable explicit mclk control in driver.
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* @qcom_fifo: enables qcom specific fifo pio read logic.
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* @qcom_dml: enables qcom specific dma glue for dma transfers.
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* @reversed_irq_handling: handle data irq before cmd irq.
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* @mmcimask1: true if variant have a MMCIMASK1 register.
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* @irq_pio_mask: bitmask used to manage interrupt pio transfert in mmcimask
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* register
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* @start_err: bitmask identifying the STARTBITERR bit inside MMCISTATUS
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* register.
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* @opendrain: bitmask identifying the OPENDRAIN bit inside MMCIPOWER register
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* @dma_lli: true if variant has dma link list feature.
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* @stm32_idmabsize_mask: stm32 sdmmc idma buffer size.
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*/
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struct variant_data {
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unsigned int clkreg;
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unsigned int clkreg_enable;
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unsigned int clkreg_8bit_bus_enable;
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unsigned int clkreg_neg_edge_enable;
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unsigned int cmdreg_cpsm_enable;
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unsigned int cmdreg_lrsp_crc;
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unsigned int cmdreg_srsp_crc;
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unsigned int cmdreg_srsp;
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unsigned int cmdreg_stop;
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unsigned int datalength_bits;
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unsigned int fifosize;
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unsigned int fifohalfsize;
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unsigned int data_cmd_enable;
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unsigned int datactrl_mask_ddrmode;
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unsigned int datactrl_mask_sdio;
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unsigned int datactrl_blocksz;
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u8 datactrl_first:1;
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u8 datacnt_useless:1;
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u8 st_sdio:1;
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u8 st_clkdiv:1;
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u8 stm32_clkdiv:1;
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u32 pwrreg_powerup;
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u32 f_max;
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u8 signal_direction:1;
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u8 pwrreg_clkgate:1;
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u8 busy_detect:1;
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u32 busy_dpsm_flag;
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u32 busy_detect_flag;
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u32 busy_detect_mask;
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u8 pwrreg_nopower:1;
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u8 explicit_mclk_control:1;
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u8 qcom_fifo:1;
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u8 qcom_dml:1;
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u8 reversed_irq_handling:1;
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u8 mmcimask1:1;
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unsigned int irq_pio_mask;
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u32 start_err;
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u32 opendrain;
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u8 dma_lli:1;
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u32 stm32_idmabsize_mask;
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void (*init)(struct mmci_host *host);
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};
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/* mmci variant callbacks */
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struct mmci_host_ops {
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int (*validate_data)(struct mmci_host *host, struct mmc_data *data);
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int (*prep_data)(struct mmci_host *host, struct mmc_data *data,
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bool next);
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void (*unprep_data)(struct mmci_host *host, struct mmc_data *data,
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int err);
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u32 (*get_datactrl_cfg)(struct mmci_host *host);
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void (*get_next_data)(struct mmci_host *host, struct mmc_data *data);
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int (*dma_setup)(struct mmci_host *host);
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void (*dma_release)(struct mmci_host *host);
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int (*dma_start)(struct mmci_host *host, unsigned int *datactrl);
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void (*dma_finalize)(struct mmci_host *host, struct mmc_data *data);
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void (*dma_error)(struct mmci_host *host);
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void (*set_clkreg)(struct mmci_host *host, unsigned int desired);
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void (*set_pwrreg)(struct mmci_host *host, unsigned int pwr);
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};
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struct mmci_host {
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phys_addr_t phybase;
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void __iomem *base;
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struct mmc_request *mrq;
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struct mmc_command *cmd;
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struct mmc_command stop_abort;
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struct mmc_data *data;
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struct mmc_host *mmc;
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struct clk *clk;
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u8 singleirq:1;
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struct reset_control *rst;
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spinlock_t lock;
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unsigned int mclk;
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/* cached value of requested clk in set_ios */
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unsigned int clock_cache;
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unsigned int cclk;
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u32 pwr_reg;
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u32 pwr_reg_add;
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|
u32 clk_reg;
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|
u32 clk_reg_add;
|
|
u32 datactrl_reg;
|
|
u32 busy_status;
|
|
u32 mask1_reg;
|
|
u8 vqmmc_enabled:1;
|
|
struct mmci_platform_data *plat;
|
|
struct mmci_host_ops *ops;
|
|
struct variant_data *variant;
|
|
struct pinctrl *pinctrl;
|
|
struct pinctrl_state *pins_default;
|
|
struct pinctrl_state *pins_opendrain;
|
|
|
|
u8 hw_designer;
|
|
u8 hw_revision:4;
|
|
|
|
struct timer_list timer;
|
|
unsigned int oldstat;
|
|
|
|
/* pio stuff */
|
|
struct sg_mapping_iter sg_miter;
|
|
unsigned int size;
|
|
int (*get_rx_fifocnt)(struct mmci_host *h, u32 status, int remain);
|
|
|
|
u8 use_dma:1;
|
|
u8 dma_in_progress:1;
|
|
void *dma_priv;
|
|
|
|
s32 next_cookie;
|
|
};
|
|
|
|
#define dma_inprogress(host) ((host)->dma_in_progress)
|
|
|
|
void mmci_write_clkreg(struct mmci_host *host, u32 clk);
|
|
void mmci_write_pwrreg(struct mmci_host *host, u32 pwr);
|
|
|
|
static inline u32 mmci_dctrl_blksz(struct mmci_host *host)
|
|
{
|
|
return (ffs(host->data->blksz) - 1) << 4;
|
|
}
|
|
|
|
#ifdef CONFIG_DMA_ENGINE
|
|
int mmci_dmae_prep_data(struct mmci_host *host, struct mmc_data *data,
|
|
bool next);
|
|
void mmci_dmae_unprep_data(struct mmci_host *host, struct mmc_data *data,
|
|
int err);
|
|
void mmci_dmae_get_next_data(struct mmci_host *host, struct mmc_data *data);
|
|
int mmci_dmae_setup(struct mmci_host *host);
|
|
void mmci_dmae_release(struct mmci_host *host);
|
|
int mmci_dmae_start(struct mmci_host *host, unsigned int *datactrl);
|
|
void mmci_dmae_finalize(struct mmci_host *host, struct mmc_data *data);
|
|
void mmci_dmae_error(struct mmci_host *host);
|
|
#endif
|
|
|
|
#ifdef CONFIG_MMC_QCOM_DML
|
|
void qcom_variant_init(struct mmci_host *host);
|
|
#else
|
|
static inline void qcom_variant_init(struct mmci_host *host) {}
|
|
#endif
|
|
|
|
#ifdef CONFIG_MMC_STM32_SDMMC
|
|
void sdmmc_variant_init(struct mmci_host *host);
|
|
#else
|
|
static inline void sdmmc_variant_init(struct mmci_host *host) {}
|
|
#endif
|