657 строки
18 KiB
C
657 строки
18 KiB
C
/*
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* Probe module for 8250/16550-type Exar chips PCI serial ports.
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*
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* Based on drivers/tty/serial/8250/8250_pci.c,
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*
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* Copyright (C) 2017 Sudip Mukherjee, All Rights Reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License.
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*/
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#include <linux/acpi.h>
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#include <linux/dmi.h>
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#include <linux/io.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/pci.h>
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#include <linux/property.h>
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#include <linux/serial_core.h>
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#include <linux/serial_reg.h>
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#include <linux/slab.h>
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#include <linux/string.h>
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#include <linux/tty.h>
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#include <linux/8250_pci.h>
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#include <asm/byteorder.h>
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#include "8250.h"
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#define PCI_DEVICE_ID_COMMTECH_4224PCI335 0x0002
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#define PCI_DEVICE_ID_COMMTECH_4222PCI335 0x0004
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#define PCI_DEVICE_ID_COMMTECH_2324PCI335 0x000a
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#define PCI_DEVICE_ID_COMMTECH_2328PCI335 0x000b
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#define PCI_DEVICE_ID_COMMTECH_4224PCIE 0x0020
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#define PCI_DEVICE_ID_COMMTECH_4228PCIE 0x0021
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#define PCI_DEVICE_ID_COMMTECH_4222PCIE 0x0022
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#define PCI_DEVICE_ID_EXAR_XR17V4358 0x4358
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#define PCI_DEVICE_ID_EXAR_XR17V8358 0x8358
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#define UART_EXAR_8XMODE 0x88 /* 8X sampling rate select */
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#define UART_EXAR_FCTR 0x08 /* Feature Control Register */
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#define UART_FCTR_EXAR_IRDA 0x10 /* IrDa data encode select */
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#define UART_FCTR_EXAR_485 0x20 /* Auto 485 half duplex dir ctl */
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#define UART_FCTR_EXAR_TRGA 0x00 /* FIFO trigger table A */
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#define UART_FCTR_EXAR_TRGB 0x60 /* FIFO trigger table B */
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#define UART_FCTR_EXAR_TRGC 0x80 /* FIFO trigger table C */
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#define UART_FCTR_EXAR_TRGD 0xc0 /* FIFO trigger table D programmable */
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#define UART_EXAR_TXTRG 0x0a /* Tx FIFO trigger level write-only */
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#define UART_EXAR_RXTRG 0x0b /* Rx FIFO trigger level write-only */
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#define UART_EXAR_MPIOINT_7_0 0x8f /* MPIOINT[7:0] */
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#define UART_EXAR_MPIOLVL_7_0 0x90 /* MPIOLVL[7:0] */
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#define UART_EXAR_MPIO3T_7_0 0x91 /* MPIO3T[7:0] */
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#define UART_EXAR_MPIOINV_7_0 0x92 /* MPIOINV[7:0] */
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#define UART_EXAR_MPIOSEL_7_0 0x93 /* MPIOSEL[7:0] */
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#define UART_EXAR_MPIOOD_7_0 0x94 /* MPIOOD[7:0] */
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#define UART_EXAR_MPIOINT_15_8 0x95 /* MPIOINT[15:8] */
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#define UART_EXAR_MPIOLVL_15_8 0x96 /* MPIOLVL[15:8] */
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#define UART_EXAR_MPIO3T_15_8 0x97 /* MPIO3T[15:8] */
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#define UART_EXAR_MPIOINV_15_8 0x98 /* MPIOINV[15:8] */
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#define UART_EXAR_MPIOSEL_15_8 0x99 /* MPIOSEL[15:8] */
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#define UART_EXAR_MPIOOD_15_8 0x9a /* MPIOOD[15:8] */
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#define UART_EXAR_RS485_DLY(x) ((x) << 4)
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/*
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* IOT2040 MPIO wiring semantics:
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*
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* MPIO Port Function
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* ---- ---- --------
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* 0 2 Mode bit 0
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* 1 2 Mode bit 1
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* 2 2 Terminate bus
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* 3 - <reserved>
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* 4 3 Mode bit 0
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* 5 3 Mode bit 1
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* 6 3 Terminate bus
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* 7 - <reserved>
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* 8 2 Enable
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* 9 3 Enable
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* 10 - Red LED
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* 11..15 - <unused>
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*/
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/* IOT2040 MPIOs 0..7 */
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#define IOT2040_UART_MODE_RS232 0x01
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#define IOT2040_UART_MODE_RS485 0x02
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#define IOT2040_UART_MODE_RS422 0x03
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#define IOT2040_UART_TERMINATE_BUS 0x04
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#define IOT2040_UART1_MASK 0x0f
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#define IOT2040_UART2_SHIFT 4
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#define IOT2040_UARTS_DEFAULT_MODE 0x11 /* both RS232 */
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#define IOT2040_UARTS_GPIO_LO_MODE 0x88 /* reserved pins as input */
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/* IOT2040 MPIOs 8..15 */
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#define IOT2040_UARTS_ENABLE 0x03
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#define IOT2040_UARTS_GPIO_HI_MODE 0xF8 /* enable & LED as outputs */
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struct exar8250;
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struct exar8250_platform {
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int (*rs485_config)(struct uart_port *, struct serial_rs485 *);
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int (*register_gpio)(struct pci_dev *, struct uart_8250_port *);
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};
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/**
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* struct exar8250_board - board information
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* @num_ports: number of serial ports
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* @reg_shift: describes UART register mapping in PCI memory
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*/
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struct exar8250_board {
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unsigned int num_ports;
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unsigned int reg_shift;
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bool has_slave;
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int (*setup)(struct exar8250 *, struct pci_dev *,
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struct uart_8250_port *, int);
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void (*exit)(struct pci_dev *pcidev);
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};
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struct exar8250 {
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unsigned int nr;
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struct exar8250_board *board;
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int line[0];
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};
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static int default_setup(struct exar8250 *priv, struct pci_dev *pcidev,
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int idx, unsigned int offset,
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struct uart_8250_port *port)
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{
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const struct exar8250_board *board = priv->board;
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unsigned int bar = 0;
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if (!pcim_iomap_table(pcidev)[bar] && !pcim_iomap(pcidev, bar, 0))
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return -ENOMEM;
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port->port.iotype = UPIO_MEM;
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port->port.mapbase = pci_resource_start(pcidev, bar) + offset;
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port->port.membase = pcim_iomap_table(pcidev)[bar] + offset;
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port->port.regshift = board->reg_shift;
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return 0;
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}
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static int
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pci_fastcom335_setup(struct exar8250 *priv, struct pci_dev *pcidev,
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struct uart_8250_port *port, int idx)
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{
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unsigned int offset = idx * 0x200;
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unsigned int baud = 1843200;
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u8 __iomem *p;
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int err;
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port->port.uartclk = baud * 16;
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err = default_setup(priv, pcidev, idx, offset, port);
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if (err)
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return err;
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p = port->port.membase;
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writeb(0x00, p + UART_EXAR_8XMODE);
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writeb(UART_FCTR_EXAR_TRGD, p + UART_EXAR_FCTR);
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writeb(32, p + UART_EXAR_TXTRG);
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writeb(32, p + UART_EXAR_RXTRG);
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/*
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* Setup Multipurpose Input/Output pins.
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*/
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if (idx == 0) {
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switch (pcidev->device) {
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case PCI_DEVICE_ID_COMMTECH_4222PCI335:
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case PCI_DEVICE_ID_COMMTECH_4224PCI335:
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writeb(0x78, p + UART_EXAR_MPIOLVL_7_0);
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writeb(0x00, p + UART_EXAR_MPIOINV_7_0);
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writeb(0x00, p + UART_EXAR_MPIOSEL_7_0);
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break;
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case PCI_DEVICE_ID_COMMTECH_2324PCI335:
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case PCI_DEVICE_ID_COMMTECH_2328PCI335:
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writeb(0x00, p + UART_EXAR_MPIOLVL_7_0);
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writeb(0xc0, p + UART_EXAR_MPIOINV_7_0);
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writeb(0xc0, p + UART_EXAR_MPIOSEL_7_0);
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break;
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}
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writeb(0x00, p + UART_EXAR_MPIOINT_7_0);
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writeb(0x00, p + UART_EXAR_MPIO3T_7_0);
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writeb(0x00, p + UART_EXAR_MPIOOD_7_0);
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}
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return 0;
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}
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static int
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pci_connect_tech_setup(struct exar8250 *priv, struct pci_dev *pcidev,
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struct uart_8250_port *port, int idx)
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{
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unsigned int offset = idx * 0x200;
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unsigned int baud = 1843200;
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port->port.uartclk = baud * 16;
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return default_setup(priv, pcidev, idx, offset, port);
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}
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static int
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pci_xr17c154_setup(struct exar8250 *priv, struct pci_dev *pcidev,
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struct uart_8250_port *port, int idx)
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{
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unsigned int offset = idx * 0x200;
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unsigned int baud = 921600;
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port->port.uartclk = baud * 16;
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return default_setup(priv, pcidev, idx, offset, port);
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}
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static void setup_gpio(struct pci_dev *pcidev, u8 __iomem *p)
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{
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/*
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* The Commtech adapters required the MPIOs to be driven low. The Exar
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* devices will export them as GPIOs, so we pre-configure them safely
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* as inputs.
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*/
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u8 dir = pcidev->vendor == PCI_VENDOR_ID_EXAR ? 0xff : 0x00;
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writeb(0x00, p + UART_EXAR_MPIOINT_7_0);
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writeb(0x00, p + UART_EXAR_MPIOLVL_7_0);
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writeb(0x00, p + UART_EXAR_MPIO3T_7_0);
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writeb(0x00, p + UART_EXAR_MPIOINV_7_0);
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writeb(dir, p + UART_EXAR_MPIOSEL_7_0);
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writeb(0x00, p + UART_EXAR_MPIOOD_7_0);
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writeb(0x00, p + UART_EXAR_MPIOINT_15_8);
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writeb(0x00, p + UART_EXAR_MPIOLVL_15_8);
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writeb(0x00, p + UART_EXAR_MPIO3T_15_8);
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writeb(0x00, p + UART_EXAR_MPIOINV_15_8);
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writeb(dir, p + UART_EXAR_MPIOSEL_15_8);
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writeb(0x00, p + UART_EXAR_MPIOOD_15_8);
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}
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static void *
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__xr17v35x_register_gpio(struct pci_dev *pcidev,
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const struct property_entry *properties)
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{
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struct platform_device *pdev;
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pdev = platform_device_alloc("gpio_exar", PLATFORM_DEVID_AUTO);
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if (!pdev)
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return NULL;
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pdev->dev.parent = &pcidev->dev;
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ACPI_COMPANION_SET(&pdev->dev, ACPI_COMPANION(&pcidev->dev));
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if (platform_device_add_properties(pdev, properties) < 0 ||
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platform_device_add(pdev) < 0) {
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platform_device_put(pdev);
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return NULL;
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}
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return pdev;
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}
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static const struct property_entry exar_gpio_properties[] = {
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PROPERTY_ENTRY_U32("exar,first-pin", 0),
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PROPERTY_ENTRY_U32("ngpios", 16),
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{ }
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};
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static int xr17v35x_register_gpio(struct pci_dev *pcidev,
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struct uart_8250_port *port)
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{
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if (pcidev->vendor == PCI_VENDOR_ID_EXAR)
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port->port.private_data =
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__xr17v35x_register_gpio(pcidev, exar_gpio_properties);
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return 0;
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}
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static const struct exar8250_platform exar8250_default_platform = {
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.register_gpio = xr17v35x_register_gpio,
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};
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static int iot2040_rs485_config(struct uart_port *port,
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struct serial_rs485 *rs485)
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{
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bool is_rs485 = !!(rs485->flags & SER_RS485_ENABLED);
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u8 __iomem *p = port->membase;
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u8 mask = IOT2040_UART1_MASK;
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u8 mode, value;
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if (is_rs485) {
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if (rs485->flags & SER_RS485_RX_DURING_TX)
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mode = IOT2040_UART_MODE_RS422;
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else
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mode = IOT2040_UART_MODE_RS485;
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if (rs485->flags & SER_RS485_TERMINATE_BUS)
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mode |= IOT2040_UART_TERMINATE_BUS;
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} else {
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mode = IOT2040_UART_MODE_RS232;
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}
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if (port->line == 3) {
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mask <<= IOT2040_UART2_SHIFT;
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mode <<= IOT2040_UART2_SHIFT;
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}
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value = readb(p + UART_EXAR_MPIOLVL_7_0);
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value &= ~mask;
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value |= mode;
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writeb(value, p + UART_EXAR_MPIOLVL_7_0);
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value = readb(p + UART_EXAR_FCTR);
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if (is_rs485)
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value |= UART_FCTR_EXAR_485;
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else
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value &= ~UART_FCTR_EXAR_485;
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writeb(value, p + UART_EXAR_FCTR);
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if (is_rs485)
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writeb(UART_EXAR_RS485_DLY(4), p + UART_MSR);
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port->rs485 = *rs485;
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return 0;
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}
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static const struct property_entry iot2040_gpio_properties[] = {
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PROPERTY_ENTRY_U32("exar,first-pin", 10),
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PROPERTY_ENTRY_U32("ngpios", 1),
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{ }
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};
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static int iot2040_register_gpio(struct pci_dev *pcidev,
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struct uart_8250_port *port)
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{
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u8 __iomem *p = port->port.membase;
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writeb(IOT2040_UARTS_DEFAULT_MODE, p + UART_EXAR_MPIOLVL_7_0);
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writeb(IOT2040_UARTS_GPIO_LO_MODE, p + UART_EXAR_MPIOSEL_7_0);
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writeb(IOT2040_UARTS_ENABLE, p + UART_EXAR_MPIOLVL_15_8);
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writeb(IOT2040_UARTS_GPIO_HI_MODE, p + UART_EXAR_MPIOSEL_15_8);
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port->port.private_data =
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__xr17v35x_register_gpio(pcidev, iot2040_gpio_properties);
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return 0;
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}
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static const struct exar8250_platform iot2040_platform = {
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.rs485_config = iot2040_rs485_config,
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.register_gpio = iot2040_register_gpio,
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};
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static const struct dmi_system_id exar_platforms[] = {
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{
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.matches = {
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DMI_EXACT_MATCH(DMI_BOARD_NAME, "SIMATIC IOT2000"),
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DMI_EXACT_MATCH(DMI_BOARD_ASSET_TAG,
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"6ES7647-0AA00-1YA2"),
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},
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.driver_data = (void *)&iot2040_platform,
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},
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{}
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};
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static int
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pci_xr17v35x_setup(struct exar8250 *priv, struct pci_dev *pcidev,
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struct uart_8250_port *port, int idx)
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{
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const struct exar8250_board *board = priv->board;
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const struct exar8250_platform *platform;
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const struct dmi_system_id *dmi_match;
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unsigned int offset = idx * 0x400;
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unsigned int baud = 7812500;
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u8 __iomem *p;
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int ret;
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dmi_match = dmi_first_match(exar_platforms);
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if (dmi_match)
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platform = dmi_match->driver_data;
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else
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platform = &exar8250_default_platform;
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port->port.uartclk = baud * 16;
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port->port.rs485_config = platform->rs485_config;
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/*
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* Setup the uart clock for the devices on expansion slot to
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* half the clock speed of the main chip (which is 125MHz)
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*/
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if (board->has_slave && idx >= 8)
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port->port.uartclk /= 2;
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ret = default_setup(priv, pcidev, idx, offset, port);
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if (ret)
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return ret;
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p = port->port.membase;
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writeb(0x00, p + UART_EXAR_8XMODE);
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writeb(UART_FCTR_EXAR_TRGD, p + UART_EXAR_FCTR);
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writeb(128, p + UART_EXAR_TXTRG);
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writeb(128, p + UART_EXAR_RXTRG);
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if (idx == 0) {
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/* Setup Multipurpose Input/Output pins. */
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setup_gpio(pcidev, p);
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ret = platform->register_gpio(pcidev, port);
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}
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return ret;
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}
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static void pci_xr17v35x_exit(struct pci_dev *pcidev)
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{
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struct exar8250 *priv = pci_get_drvdata(pcidev);
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struct uart_8250_port *port = serial8250_get_port(priv->line[0]);
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struct platform_device *pdev = port->port.private_data;
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platform_device_unregister(pdev);
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port->port.private_data = NULL;
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}
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static int
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exar_pci_probe(struct pci_dev *pcidev, const struct pci_device_id *ent)
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{
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unsigned int nr_ports, i, bar = 0, maxnr;
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struct exar8250_board *board;
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struct uart_8250_port uart;
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struct exar8250 *priv;
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int rc;
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board = (struct exar8250_board *)ent->driver_data;
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if (!board)
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return -EINVAL;
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rc = pcim_enable_device(pcidev);
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if (rc)
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return rc;
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maxnr = pci_resource_len(pcidev, bar) >> (board->reg_shift + 3);
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nr_ports = board->num_ports ? board->num_ports : pcidev->device & 0x0f;
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priv = devm_kzalloc(&pcidev->dev, sizeof(*priv) +
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sizeof(unsigned int) * nr_ports,
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GFP_KERNEL);
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if (!priv)
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return -ENOMEM;
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priv->board = board;
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pci_set_master(pcidev);
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rc = pci_alloc_irq_vectors(pcidev, 1, 1, PCI_IRQ_ALL_TYPES);
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|
if (rc < 0)
|
|
return rc;
|
|
|
|
memset(&uart, 0, sizeof(uart));
|
|
uart.port.flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF | UPF_SHARE_IRQ
|
|
| UPF_EXAR_EFR;
|
|
uart.port.irq = pci_irq_vector(pcidev, 0);
|
|
uart.port.dev = &pcidev->dev;
|
|
|
|
for (i = 0; i < nr_ports && i < maxnr; i++) {
|
|
rc = board->setup(priv, pcidev, &uart, i);
|
|
if (rc) {
|
|
dev_err(&pcidev->dev, "Failed to setup port %u\n", i);
|
|
break;
|
|
}
|
|
|
|
dev_dbg(&pcidev->dev, "Setup PCI port: port %lx, irq %d, type %d\n",
|
|
uart.port.iobase, uart.port.irq, uart.port.iotype);
|
|
|
|
priv->line[i] = serial8250_register_8250_port(&uart);
|
|
if (priv->line[i] < 0) {
|
|
dev_err(&pcidev->dev,
|
|
"Couldn't register serial port %lx, irq %d, type %d, error %d\n",
|
|
uart.port.iobase, uart.port.irq,
|
|
uart.port.iotype, priv->line[i]);
|
|
break;
|
|
}
|
|
}
|
|
priv->nr = i;
|
|
pci_set_drvdata(pcidev, priv);
|
|
return 0;
|
|
}
|
|
|
|
static void exar_pci_remove(struct pci_dev *pcidev)
|
|
{
|
|
struct exar8250 *priv = pci_get_drvdata(pcidev);
|
|
unsigned int i;
|
|
|
|
for (i = 0; i < priv->nr; i++)
|
|
serial8250_unregister_port(priv->line[i]);
|
|
|
|
if (priv->board->exit)
|
|
priv->board->exit(pcidev);
|
|
}
|
|
|
|
static int __maybe_unused exar_suspend(struct device *dev)
|
|
{
|
|
struct pci_dev *pcidev = to_pci_dev(dev);
|
|
struct exar8250 *priv = pci_get_drvdata(pcidev);
|
|
unsigned int i;
|
|
|
|
for (i = 0; i < priv->nr; i++)
|
|
if (priv->line[i] >= 0)
|
|
serial8250_suspend_port(priv->line[i]);
|
|
|
|
/* Ensure that every init quirk is properly torn down */
|
|
if (priv->board->exit)
|
|
priv->board->exit(pcidev);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int __maybe_unused exar_resume(struct device *dev)
|
|
{
|
|
struct pci_dev *pcidev = to_pci_dev(dev);
|
|
struct exar8250 *priv = pci_get_drvdata(pcidev);
|
|
unsigned int i;
|
|
|
|
for (i = 0; i < priv->nr; i++)
|
|
if (priv->line[i] >= 0)
|
|
serial8250_resume_port(priv->line[i]);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static SIMPLE_DEV_PM_OPS(exar_pci_pm, exar_suspend, exar_resume);
|
|
|
|
static const struct exar8250_board pbn_fastcom335_2 = {
|
|
.num_ports = 2,
|
|
.setup = pci_fastcom335_setup,
|
|
};
|
|
|
|
static const struct exar8250_board pbn_fastcom335_4 = {
|
|
.num_ports = 4,
|
|
.setup = pci_fastcom335_setup,
|
|
};
|
|
|
|
static const struct exar8250_board pbn_fastcom335_8 = {
|
|
.num_ports = 8,
|
|
.setup = pci_fastcom335_setup,
|
|
};
|
|
|
|
static const struct exar8250_board pbn_connect = {
|
|
.setup = pci_connect_tech_setup,
|
|
};
|
|
|
|
static const struct exar8250_board pbn_exar_ibm_saturn = {
|
|
.num_ports = 1,
|
|
.setup = pci_xr17c154_setup,
|
|
};
|
|
|
|
static const struct exar8250_board pbn_exar_XR17C15x = {
|
|
.setup = pci_xr17c154_setup,
|
|
};
|
|
|
|
static const struct exar8250_board pbn_exar_XR17V35x = {
|
|
.setup = pci_xr17v35x_setup,
|
|
.exit = pci_xr17v35x_exit,
|
|
};
|
|
|
|
static const struct exar8250_board pbn_exar_XR17V4358 = {
|
|
.num_ports = 12,
|
|
.has_slave = true,
|
|
.setup = pci_xr17v35x_setup,
|
|
.exit = pci_xr17v35x_exit,
|
|
};
|
|
|
|
static const struct exar8250_board pbn_exar_XR17V8358 = {
|
|
.num_ports = 16,
|
|
.has_slave = true,
|
|
.setup = pci_xr17v35x_setup,
|
|
.exit = pci_xr17v35x_exit,
|
|
};
|
|
|
|
#define CONNECT_DEVICE(devid, sdevid, bd) { \
|
|
PCI_DEVICE_SUB( \
|
|
PCI_VENDOR_ID_EXAR, \
|
|
PCI_DEVICE_ID_EXAR_##devid, \
|
|
PCI_SUBVENDOR_ID_CONNECT_TECH, \
|
|
PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_##sdevid), 0, 0, \
|
|
(kernel_ulong_t)&bd \
|
|
}
|
|
|
|
#define EXAR_DEVICE(vend, devid, bd) { \
|
|
PCI_VDEVICE(vend, PCI_DEVICE_ID_##devid), (kernel_ulong_t)&bd \
|
|
}
|
|
|
|
#define IBM_DEVICE(devid, sdevid, bd) { \
|
|
PCI_DEVICE_SUB( \
|
|
PCI_VENDOR_ID_EXAR, \
|
|
PCI_DEVICE_ID_EXAR_##devid, \
|
|
PCI_VENDOR_ID_IBM, \
|
|
PCI_SUBDEVICE_ID_IBM_##sdevid), 0, 0, \
|
|
(kernel_ulong_t)&bd \
|
|
}
|
|
|
|
static const struct pci_device_id exar_pci_tbl[] = {
|
|
CONNECT_DEVICE(XR17C152, UART_2_232, pbn_connect),
|
|
CONNECT_DEVICE(XR17C154, UART_4_232, pbn_connect),
|
|
CONNECT_DEVICE(XR17C158, UART_8_232, pbn_connect),
|
|
CONNECT_DEVICE(XR17C152, UART_1_1, pbn_connect),
|
|
CONNECT_DEVICE(XR17C154, UART_2_2, pbn_connect),
|
|
CONNECT_DEVICE(XR17C158, UART_4_4, pbn_connect),
|
|
CONNECT_DEVICE(XR17C152, UART_2, pbn_connect),
|
|
CONNECT_DEVICE(XR17C154, UART_4, pbn_connect),
|
|
CONNECT_DEVICE(XR17C158, UART_8, pbn_connect),
|
|
CONNECT_DEVICE(XR17C152, UART_2_485, pbn_connect),
|
|
CONNECT_DEVICE(XR17C154, UART_4_485, pbn_connect),
|
|
CONNECT_DEVICE(XR17C158, UART_8_485, pbn_connect),
|
|
|
|
IBM_DEVICE(XR17C152, SATURN_SERIAL_ONE_PORT, pbn_exar_ibm_saturn),
|
|
|
|
/* Exar Corp. XR17C15[248] Dual/Quad/Octal UART */
|
|
EXAR_DEVICE(EXAR, EXAR_XR17C152, pbn_exar_XR17C15x),
|
|
EXAR_DEVICE(EXAR, EXAR_XR17C154, pbn_exar_XR17C15x),
|
|
EXAR_DEVICE(EXAR, EXAR_XR17C158, pbn_exar_XR17C15x),
|
|
|
|
/* Exar Corp. XR17V[48]35[248] Dual/Quad/Octal/Hexa PCIe UARTs */
|
|
EXAR_DEVICE(EXAR, EXAR_XR17V352, pbn_exar_XR17V35x),
|
|
EXAR_DEVICE(EXAR, EXAR_XR17V354, pbn_exar_XR17V35x),
|
|
EXAR_DEVICE(EXAR, EXAR_XR17V358, pbn_exar_XR17V35x),
|
|
EXAR_DEVICE(EXAR, EXAR_XR17V4358, pbn_exar_XR17V4358),
|
|
EXAR_DEVICE(EXAR, EXAR_XR17V8358, pbn_exar_XR17V8358),
|
|
EXAR_DEVICE(COMMTECH, COMMTECH_4222PCIE, pbn_exar_XR17V35x),
|
|
EXAR_DEVICE(COMMTECH, COMMTECH_4224PCIE, pbn_exar_XR17V35x),
|
|
EXAR_DEVICE(COMMTECH, COMMTECH_4228PCIE, pbn_exar_XR17V35x),
|
|
|
|
EXAR_DEVICE(COMMTECH, COMMTECH_4222PCI335, pbn_fastcom335_2),
|
|
EXAR_DEVICE(COMMTECH, COMMTECH_4224PCI335, pbn_fastcom335_4),
|
|
EXAR_DEVICE(COMMTECH, COMMTECH_2324PCI335, pbn_fastcom335_4),
|
|
EXAR_DEVICE(COMMTECH, COMMTECH_2328PCI335, pbn_fastcom335_8),
|
|
{ 0, }
|
|
};
|
|
MODULE_DEVICE_TABLE(pci, exar_pci_tbl);
|
|
|
|
static struct pci_driver exar_pci_driver = {
|
|
.name = "exar_serial",
|
|
.probe = exar_pci_probe,
|
|
.remove = exar_pci_remove,
|
|
.driver = {
|
|
.pm = &exar_pci_pm,
|
|
},
|
|
.id_table = exar_pci_tbl,
|
|
};
|
|
module_pci_driver(exar_pci_driver);
|
|
|
|
MODULE_LICENSE("GPL");
|
|
MODULE_DESCRIPTION("Exar Serial Driver");
|
|
MODULE_AUTHOR("Sudip Mukherjee <sudip.mukherjee@codethink.co.uk>");
|