245 строки
5.4 KiB
C
245 строки
5.4 KiB
C
/*
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* Versatile Express Core Tile Cortex A9x4 Support
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*/
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#include <linux/init.h>
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#include <linux/gfp.h>
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#include <linux/device.h>
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#include <linux/dma-mapping.h>
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#include <linux/platform_device.h>
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#include <linux/amba/bus.h>
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#include <linux/amba/clcd.h>
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#include <linux/clkdev.h>
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#include <asm/hardware/arm_timer.h>
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#include <asm/hardware/cache-l2x0.h>
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#include <asm/hardware/gic.h>
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#include <asm/pmu.h>
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#include <asm/smp_scu.h>
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#include <asm/smp_twd.h>
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#include <mach/ct-ca9x4.h>
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#include <asm/hardware/timer-sp.h>
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#include <asm/mach/map.h>
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#include <asm/mach/time.h>
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#include "core.h"
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#include <mach/motherboard.h>
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#include <plat/clcd.h>
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static struct map_desc ct_ca9x4_io_desc[] __initdata = {
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{
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.virtual = V2T_PERIPH,
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.pfn = __phys_to_pfn(CT_CA9X4_MPIC),
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.length = SZ_8K,
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.type = MT_DEVICE,
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},
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};
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static void __init ct_ca9x4_map_io(void)
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{
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iotable_init(ct_ca9x4_io_desc, ARRAY_SIZE(ct_ca9x4_io_desc));
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}
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#ifdef CONFIG_HAVE_ARM_TWD
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static DEFINE_TWD_LOCAL_TIMER(twd_local_timer, A9_MPCORE_TWD, IRQ_LOCALTIMER);
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static void __init ca9x4_twd_init(void)
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{
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int err = twd_local_timer_register(&twd_local_timer);
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if (err)
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pr_err("twd_local_timer_register failed %d\n", err);
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}
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#else
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#define ca9x4_twd_init() do {} while(0)
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#endif
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static void __init ct_ca9x4_init_irq(void)
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{
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gic_init(0, 29, ioremap(A9_MPCORE_GIC_DIST, SZ_4K),
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ioremap(A9_MPCORE_GIC_CPU, SZ_256));
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ca9x4_twd_init();
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}
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static void ct_ca9x4_clcd_enable(struct clcd_fb *fb)
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{
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v2m_cfg_write(SYS_CFG_MUXFPGA | SYS_CFG_SITE_DB1, 0);
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v2m_cfg_write(SYS_CFG_DVIMODE | SYS_CFG_SITE_DB1, 2);
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}
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static int ct_ca9x4_clcd_setup(struct clcd_fb *fb)
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{
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unsigned long framesize = 1024 * 768 * 2;
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fb->panel = versatile_clcd_get_panel("XVGA");
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if (!fb->panel)
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return -EINVAL;
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return versatile_clcd_setup_dma(fb, framesize);
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}
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static struct clcd_board ct_ca9x4_clcd_data = {
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.name = "CT-CA9X4",
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.caps = CLCD_CAP_5551 | CLCD_CAP_565,
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.check = clcdfb_check,
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.decode = clcdfb_decode,
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.enable = ct_ca9x4_clcd_enable,
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.setup = ct_ca9x4_clcd_setup,
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.mmap = versatile_clcd_mmap_dma,
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.remove = versatile_clcd_remove_dma,
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};
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static AMBA_AHB_DEVICE(clcd, "ct:clcd", 0, CT_CA9X4_CLCDC, IRQ_CT_CA9X4_CLCDC, &ct_ca9x4_clcd_data);
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static AMBA_APB_DEVICE(dmc, "ct:dmc", 0, CT_CA9X4_DMC, IRQ_CT_CA9X4_DMC, NULL);
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static AMBA_APB_DEVICE(smc, "ct:smc", 0, CT_CA9X4_SMC, IRQ_CT_CA9X4_SMC, NULL);
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static AMBA_APB_DEVICE(gpio, "ct:gpio", 0, CT_CA9X4_GPIO, IRQ_CT_CA9X4_GPIO, NULL);
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static struct amba_device *ct_ca9x4_amba_devs[] __initdata = {
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&clcd_device,
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&dmc_device,
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&smc_device,
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&gpio_device,
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};
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static long ct_round(struct clk *clk, unsigned long rate)
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{
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return rate;
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}
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static int ct_set(struct clk *clk, unsigned long rate)
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{
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return v2m_cfg_write(SYS_CFG_OSC | SYS_CFG_SITE_DB1 | 1, rate);
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}
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static const struct clk_ops osc1_clk_ops = {
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.round = ct_round,
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.set = ct_set,
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};
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static struct clk osc1_clk = {
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.ops = &osc1_clk_ops,
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.rate = 24000000,
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};
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static struct clk ct_sp804_clk = {
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.rate = 1000000,
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};
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static struct clk_lookup lookups[] = {
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{ /* CLCD */
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.dev_id = "ct:clcd",
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.clk = &osc1_clk,
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}, { /* SP804 timers */
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.dev_id = "sp804",
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.con_id = "ct-timer0",
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.clk = &ct_sp804_clk,
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}, { /* SP804 timers */
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.dev_id = "sp804",
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.con_id = "ct-timer1",
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.clk = &ct_sp804_clk,
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},
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};
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static struct resource pmu_resources[] = {
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[0] = {
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.start = IRQ_CT_CA9X4_PMU_CPU0,
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.end = IRQ_CT_CA9X4_PMU_CPU0,
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.flags = IORESOURCE_IRQ,
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},
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[1] = {
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.start = IRQ_CT_CA9X4_PMU_CPU1,
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.end = IRQ_CT_CA9X4_PMU_CPU1,
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.flags = IORESOURCE_IRQ,
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},
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[2] = {
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.start = IRQ_CT_CA9X4_PMU_CPU2,
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.end = IRQ_CT_CA9X4_PMU_CPU2,
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.flags = IORESOURCE_IRQ,
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},
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[3] = {
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.start = IRQ_CT_CA9X4_PMU_CPU3,
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.end = IRQ_CT_CA9X4_PMU_CPU3,
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.flags = IORESOURCE_IRQ,
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},
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};
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static struct platform_device pmu_device = {
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.name = "arm-pmu",
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.id = ARM_PMU_DEVICE_CPU,
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.num_resources = ARRAY_SIZE(pmu_resources),
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.resource = pmu_resources,
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};
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static void __init ct_ca9x4_init_early(void)
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{
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clkdev_add_table(lookups, ARRAY_SIZE(lookups));
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}
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static void __init ct_ca9x4_init(void)
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{
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int i;
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#ifdef CONFIG_CACHE_L2X0
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void __iomem *l2x0_base = ioremap(CT_CA9X4_L2CC, SZ_4K);
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/* set RAM latencies to 1 cycle for this core tile. */
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writel(0, l2x0_base + L2X0_TAG_LATENCY_CTRL);
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writel(0, l2x0_base + L2X0_DATA_LATENCY_CTRL);
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l2x0_init(l2x0_base, 0x00400000, 0xfe0fffff);
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#endif
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for (i = 0; i < ARRAY_SIZE(ct_ca9x4_amba_devs); i++)
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amba_device_register(ct_ca9x4_amba_devs[i], &iomem_resource);
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platform_device_register(&pmu_device);
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}
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#ifdef CONFIG_SMP
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static void *ct_ca9x4_scu_base __initdata;
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static void __init ct_ca9x4_init_cpu_map(void)
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{
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int i, ncores;
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ct_ca9x4_scu_base = ioremap(A9_MPCORE_SCU, SZ_128);
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if (WARN_ON(!ct_ca9x4_scu_base))
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return;
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ncores = scu_get_core_count(ct_ca9x4_scu_base);
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if (ncores > nr_cpu_ids) {
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pr_warn("SMP: %u cores greater than maximum (%u), clipping\n",
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ncores, nr_cpu_ids);
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ncores = nr_cpu_ids;
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}
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for (i = 0; i < ncores; ++i)
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set_cpu_possible(i, true);
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set_smp_cross_call(gic_raise_softirq);
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}
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static void __init ct_ca9x4_smp_enable(unsigned int max_cpus)
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{
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scu_enable(ct_ca9x4_scu_base);
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}
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#endif
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struct ct_desc ct_ca9x4_desc __initdata = {
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.id = V2M_CT_ID_CA9,
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.name = "CA9x4",
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.map_io = ct_ca9x4_map_io,
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.init_early = ct_ca9x4_init_early,
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.init_irq = ct_ca9x4_init_irq,
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.init_tile = ct_ca9x4_init,
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#ifdef CONFIG_SMP
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.init_cpu_map = ct_ca9x4_init_cpu_map,
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.smp_enable = ct_ca9x4_smp_enable,
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#endif
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};
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