Stephen Boyd b03781920c Merge branches 'clk-mediatek', 'clk-hisi', 'clk-allwinner', 'clk-ux500' and 'clk-renesas' into clk-next ... * clk-mediatek: clk: mediatek: add audsys support for MT2701 clk: mediatek: add devm_of_platform_populate() for MT7622 audsys dt-bindings: clock: mediatek: add audsys support for MT2701 dt-bindings: clock: mediatek: update audsys documentation to adapt MFD device clk: mediatek: update missing clock data for MT7622 audsys clk: mediatek: fix PWM clock source by adding a fixed-factor clock dt-bindings: clock: mediatek: add binding for fixed-factor clock axisel_d4 * clk-hisi: clk: hisilicon: fix potential NULL dereference in hisi_clk_alloc() clk: hisilicon: mark wdt_mux_p[] as const clk: hisilicon: Mark phase_ops static clk: hi3798cv200: add emmc sample and drive clock clk: hisilicon: add hisi phase clock support clk: hi3798cv200: add COMBPHY0 clock support clk: hi3798cv200: fix define indentation clk: hi3798cv200: add support for HISTB_USB2_OTG_UTMI_CLK clk: hi3798cv200: correct IR clock parent clk: hi3798cv200: fix unregister call sequence in error path * clk-allwinner: clk: sunxi-ng: add missing hdmi-slow clock for H6 CCU clk: sunxi-ng: add support for the Allwinner H6 CCU dt-bindings: add device tree binding for Allwinner H6 main CCU clk: sunxi-ng: Support fixed post-dividers on NKMP style clocks clk: sunxi-ng: h3: h5: export CLK_PLL_VIDEO clk: sunxi-ng: h3: h5: Allow some clocks to set parent rate clk: sunxi-ng: h3: h5: Add minimal rate for video PLL clk: sunxi-ng: Add check for minimal rate to NM PLLs clk: sunxi-ng: Use u64 for calculation of nkmp rate clk: sunxi-ng: Mask nkmp factors when setting register clk: sunxi-ng: remove select on obsolete SUNXI_CCU_X kconfig name * clk-ux500: clk: ux500: Drop AB8540/9540 support * clk-renesas: (27 commits) clk: renesas: cpg-mssr: Adjust r8a77980 ifdef clk: renesas: rcar-gen3: Always use readl()/writel() clk: renesas: sh73a0: Always use readl()/writel() clk: renesas: rza1: Always use readl()/writel() clk: renesas: rcar-gen2: Always use readl()/writel() clk: renesas: r8a7740: Always use readl()/writel() clk: renesas: r8a73a4: Always use readl()/writel() clk: renesas: mstp: Always use readl()/writel() clk: renesas: div6: Always use readl()/writel() clk: fix false-positive Wmaybe-uninitialized warning clk: renesas: r8a77965: Replace DU2 clock clk: renesas: cpg-mssr: Add support for R-Car M3-N clk: renesas: cpg-mssr: add R8A77980 support dt-bindings: clock: add R8A77980 CPG core clock definitions clk: renesas: r8a7792: Add rwdt clock clk: renesas: r8a7794: Add rwdt clock clk: renesas: r8a7791/r8a7793: Add rwdt clock clk: renesas: r8a7790: Add rwdt clock clk: renesas: r8a7745: Add rwdt clock clk: renesas: r8a7743: Add rwdt clock ...		2018-04-06 13:21:57 -07:00
..
Kconfig	clk: mediatek: add audsys support for MT2701	2018-03-20 00:24:42 -07:00
Makefile	clk: mediatek: add audsys support for MT2701	2018-03-20 00:24:42 -07:00
clk-apmixed.c	clk: mediatek: Add USB clock support in MT8173 APMIXEDSYS	2015-10-01 12:06:00 +08:00
clk-cpumux.c	clk: Convert to using %pOF instead of full_name	2017-07-21 15:49:54 -07:00
clk-cpumux.h	clk: mediatek: add missing cpu mux causing Mediatek cpufreq can't work	2017-06-19 19:02:43 -07:00
clk-gate.c	clk: mediatek: Add MT2701 clock support	2016-11-08 15:59:49 -08:00
clk-gate.h	clk: mediatek: Add MT2701 clock support	2016-11-08 15:59:49 -08:00
clk-mt2701-aud.c	clk: mediatek: add audsys support for MT2701	2018-03-20 00:24:42 -07:00
clk-mt2701-bdp.c	clk: mediatek: Add MT2701 clock support	2016-11-08 15:59:49 -08:00
clk-mt2701-eth.c	clk: mediatek: add mt2701 ethernet reset	2017-04-21 19:20:33 -07:00
clk-mt2701-hif.c	reset: mediatek: Add MT2701 reset driver	2016-11-08 15:59:51 -08:00
clk-mt2701-img.c	clk: mediatek: Add MT2701 clock support	2016-11-08 15:59:49 -08:00
clk-mt2701-mm.c	clk: mediatek: Add MT2701 clock support	2016-11-08 15:59:49 -08:00
clk-mt2701-vdec.c	clk: mediatek: Add MT2701 clock support	2016-11-08 15:59:49 -08:00
clk-mt2701.c	clk: mediatek: fix PWM clock source by adding a fixed-factor clock	2018-03-19 13:25:30 -07:00
clk-mt2712-bdp.c	clk: mediatek: Add MT2712 clock support	2017-11-02 01:02:53 -07:00
clk-mt2712-img.c	clk: mediatek: Add MT2712 clock support	2017-11-02 01:02:53 -07:00
clk-mt2712-jpgdec.c	clk: mediatek: Add MT2712 clock support	2017-11-02 01:02:53 -07:00
clk-mt2712-mfg.c	clk: mediatek: Add MT2712 clock support	2017-11-02 01:02:53 -07:00
clk-mt2712-mm.c	clk: mediatek: Add MT2712 clock support	2017-11-02 01:02:53 -07:00
clk-mt2712-vdec.c	clk: mediatek: Add MT2712 clock support	2017-11-02 01:02:53 -07:00
clk-mt2712-venc.c	clk: mediatek: Add MT2712 clock support	2017-11-02 01:02:53 -07:00
clk-mt2712.c	clk: mediatek: update clock driver of MT2712	2018-03-19 14:37:40 -07:00
clk-mt6797-img.c	clk: mediatek: add clk support for MT6797	2017-04-19 09:20:21 -07:00
clk-mt6797-mm.c	clk: mediatek: add clk support for MT6797	2017-04-19 09:20:21 -07:00
clk-mt6797-vdec.c	clk: mediatek: add clk support for MT6797	2017-04-19 09:20:21 -07:00
clk-mt6797-venc.c	clk: mediatek: add clk support for MT6797	2017-04-19 09:20:21 -07:00
clk-mt6797.c	clk: mediatek: add clk support for MT6797	2017-04-19 09:20:21 -07:00
clk-mt7622-aud.c	clk: mediatek: add devm_of_platform_populate() for MT7622 audsys	2018-03-20 00:24:33 -07:00
clk-mt7622-eth.c	clk: mediatek: add clock support for MT7622 SoC	2017-11-02 01:10:12 -07:00
clk-mt7622-hif.c	clk: mediatek: add clock support for MT7622 SoC	2017-11-02 01:10:12 -07:00
clk-mt7622.c	clk: mediatek: add clock support for MT7622 SoC	2017-11-02 01:10:12 -07:00
clk-mt8135.c	clk: mediatek: Properly include clk.h	2015-07-20 10:53:09 -07:00
clk-mt8173.c	clk: mediatek: export cpu multiplexer clock for MT8173 SoCs	2017-06-19 19:02:44 -07:00
clk-mtk.c	clk: Convert to using %pOF instead of full_name	2017-07-21 15:49:54 -07:00
clk-mtk.h	clk: mediatek: adjust dependency of reset.c to avoid unexpectedly being built	2018-01-10 13:41:15 -08:00
clk-pll.c	clk: mediatek: add the option for determining PLL source clock	2017-11-02 01:07:51 -07:00
reset.c	clk: Convert to using %pOF instead of full_name	2017-07-21 15:49:54 -07:00