863 строки
23 KiB
C
863 строки
23 KiB
C
/*
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* linux/arch/arm/plat-mxc/dma-v1.c
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*
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* i.MX DMA registration and IRQ dispatching
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*
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* Copyright 2006 Pavel Pisa <pisa@cmp.felk.cvut.cz>
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* Copyright 2008 Juergen Beisert, <kernel@pengutronix.de>
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* Copyright 2008 Sascha Hauer, <s.hauer@pengutronix.de>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
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* MA 02110-1301, USA.
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*/
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#include <linux/module.h>
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#include <linux/init.h>
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#include <linux/kernel.h>
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#include <linux/interrupt.h>
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#include <linux/errno.h>
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#include <linux/clk.h>
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#include <linux/scatterlist.h>
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#include <linux/io.h>
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#include <asm/system.h>
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#include <asm/irq.h>
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#include <mach/hardware.h>
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#include <mach/dma-v1.h>
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#define DMA_DCR 0x00 /* Control Register */
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#define DMA_DISR 0x04 /* Interrupt status Register */
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#define DMA_DIMR 0x08 /* Interrupt mask Register */
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#define DMA_DBTOSR 0x0c /* Burst timeout status Register */
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#define DMA_DRTOSR 0x10 /* Request timeout Register */
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#define DMA_DSESR 0x14 /* Transfer Error Status Register */
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#define DMA_DBOSR 0x18 /* Buffer overflow status Register */
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#define DMA_DBTOCR 0x1c /* Burst timeout control Register */
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#define DMA_WSRA 0x40 /* W-Size Register A */
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#define DMA_XSRA 0x44 /* X-Size Register A */
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#define DMA_YSRA 0x48 /* Y-Size Register A */
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#define DMA_WSRB 0x4c /* W-Size Register B */
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#define DMA_XSRB 0x50 /* X-Size Register B */
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#define DMA_YSRB 0x54 /* Y-Size Register B */
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#define DMA_SAR(x) (0x80 + ((x) << 6)) /* Source Address Registers */
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#define DMA_DAR(x) (0x84 + ((x) << 6)) /* Destination Address Registers */
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#define DMA_CNTR(x) (0x88 + ((x) << 6)) /* Count Registers */
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#define DMA_CCR(x) (0x8c + ((x) << 6)) /* Control Registers */
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#define DMA_RSSR(x) (0x90 + ((x) << 6)) /* Request source select Registers */
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#define DMA_BLR(x) (0x94 + ((x) << 6)) /* Burst length Registers */
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#define DMA_RTOR(x) (0x98 + ((x) << 6)) /* Request timeout Registers */
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#define DMA_BUCR(x) (0x98 + ((x) << 6)) /* Bus Utilization Registers */
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#define DMA_CCNR(x) (0x9C + ((x) << 6)) /* Channel counter Registers */
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#define DCR_DRST (1<<1)
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#define DCR_DEN (1<<0)
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#define DBTOCR_EN (1<<15)
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#define DBTOCR_CNT(x) ((x) & 0x7fff)
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#define CNTR_CNT(x) ((x) & 0xffffff)
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#define CCR_ACRPT (1<<14)
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#define CCR_DMOD_LINEAR (0x0 << 12)
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#define CCR_DMOD_2D (0x1 << 12)
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#define CCR_DMOD_FIFO (0x2 << 12)
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#define CCR_DMOD_EOBFIFO (0x3 << 12)
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#define CCR_SMOD_LINEAR (0x0 << 10)
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#define CCR_SMOD_2D (0x1 << 10)
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#define CCR_SMOD_FIFO (0x2 << 10)
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#define CCR_SMOD_EOBFIFO (0x3 << 10)
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#define CCR_MDIR_DEC (1<<9)
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#define CCR_MSEL_B (1<<8)
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#define CCR_DSIZ_32 (0x0 << 6)
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#define CCR_DSIZ_8 (0x1 << 6)
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#define CCR_DSIZ_16 (0x2 << 6)
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#define CCR_SSIZ_32 (0x0 << 4)
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#define CCR_SSIZ_8 (0x1 << 4)
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#define CCR_SSIZ_16 (0x2 << 4)
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#define CCR_REN (1<<3)
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#define CCR_RPT (1<<2)
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#define CCR_FRC (1<<1)
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#define CCR_CEN (1<<0)
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#define RTOR_EN (1<<15)
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#define RTOR_CLK (1<<14)
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#define RTOR_PSC (1<<13)
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/*
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* struct imx_dma_channel - i.MX specific DMA extension
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* @name: name specified by DMA client
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* @irq_handler: client callback for end of transfer
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* @err_handler: client callback for error condition
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* @data: clients context data for callbacks
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* @dma_mode: direction of the transfer %DMA_MODE_READ or %DMA_MODE_WRITE
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* @sg: pointer to the actual read/written chunk for scatter-gather emulation
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* @resbytes: total residual number of bytes to transfer
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* (it can be lower or same as sum of SG mapped chunk sizes)
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* @sgcount: number of chunks to be read/written
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*
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* Structure is used for IMX DMA processing. It would be probably good
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* @struct dma_struct in the future for external interfacing and use
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* @struct imx_dma_channel only as extension to it.
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*/
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struct imx_dma_channel {
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const char *name;
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void (*irq_handler) (int, void *);
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void (*err_handler) (int, void *, int errcode);
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void (*prog_handler) (int, void *, struct scatterlist *);
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void *data;
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unsigned int dma_mode;
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struct scatterlist *sg;
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unsigned int resbytes;
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int dma_num;
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int in_use;
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u32 ccr_from_device;
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u32 ccr_to_device;
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struct timer_list watchdog;
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int hw_chaining;
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};
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static void __iomem *imx_dmav1_baseaddr;
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static void imx_dmav1_writel(unsigned val, unsigned offset)
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{
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__raw_writel(val, imx_dmav1_baseaddr + offset);
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}
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static unsigned imx_dmav1_readl(unsigned offset)
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{
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return __raw_readl(imx_dmav1_baseaddr + offset);
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}
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static struct imx_dma_channel imx_dma_channels[IMX_DMA_CHANNELS];
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static struct clk *dma_clk;
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static int imx_dma_hw_chain(struct imx_dma_channel *imxdma)
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{
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if (cpu_is_mx27())
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return imxdma->hw_chaining;
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else
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return 0;
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}
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/*
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* imx_dma_sg_next - prepare next chunk for scatter-gather DMA emulation
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*/
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static inline int imx_dma_sg_next(int channel, struct scatterlist *sg)
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{
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struct imx_dma_channel *imxdma = &imx_dma_channels[channel];
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unsigned long now;
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if (!imxdma->name) {
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printk(KERN_CRIT "%s: called for not allocated channel %d\n",
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__func__, channel);
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return 0;
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}
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now = min(imxdma->resbytes, sg->length);
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if (imxdma->resbytes != IMX_DMA_LENGTH_LOOP)
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imxdma->resbytes -= now;
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if ((imxdma->dma_mode & DMA_MODE_MASK) == DMA_MODE_READ)
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imx_dmav1_writel(sg->dma_address, DMA_DAR(channel));
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else
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imx_dmav1_writel(sg->dma_address, DMA_SAR(channel));
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imx_dmav1_writel(now, DMA_CNTR(channel));
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pr_debug("imxdma%d: next sg chunk dst 0x%08x, src 0x%08x, "
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"size 0x%08x\n", channel,
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imx_dmav1_readl(DMA_DAR(channel)),
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imx_dmav1_readl(DMA_SAR(channel)),
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imx_dmav1_readl(DMA_CNTR(channel)));
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return now;
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}
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/**
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* imx_dma_setup_single - setup i.MX DMA channel for linear memory to/from
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* device transfer
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*
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* @channel: i.MX DMA channel number
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* @dma_address: the DMA/physical memory address of the linear data block
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* to transfer
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* @dma_length: length of the data block in bytes
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* @dev_addr: physical device port address
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* @dmamode: DMA transfer mode, %DMA_MODE_READ from the device to the memory
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* or %DMA_MODE_WRITE from memory to the device
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*
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* Return value: if incorrect parameters are provided -%EINVAL.
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* Zero indicates success.
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*/
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int
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imx_dma_setup_single(int channel, dma_addr_t dma_address,
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unsigned int dma_length, unsigned int dev_addr,
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unsigned int dmamode)
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{
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struct imx_dma_channel *imxdma = &imx_dma_channels[channel];
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imxdma->sg = NULL;
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imxdma->dma_mode = dmamode;
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if (!dma_address) {
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printk(KERN_ERR "imxdma%d: imx_dma_setup_single null address\n",
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channel);
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return -EINVAL;
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}
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if (!dma_length) {
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printk(KERN_ERR "imxdma%d: imx_dma_setup_single zero length\n",
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channel);
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return -EINVAL;
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}
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if ((dmamode & DMA_MODE_MASK) == DMA_MODE_READ) {
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pr_debug("imxdma%d: %s dma_addressg=0x%08x dma_length=%d "
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"dev_addr=0x%08x for read\n",
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channel, __func__, (unsigned int)dma_address,
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dma_length, dev_addr);
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imx_dmav1_writel(dev_addr, DMA_SAR(channel));
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imx_dmav1_writel(dma_address, DMA_DAR(channel));
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imx_dmav1_writel(imxdma->ccr_from_device, DMA_CCR(channel));
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} else if ((dmamode & DMA_MODE_MASK) == DMA_MODE_WRITE) {
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pr_debug("imxdma%d: %s dma_addressg=0x%08x dma_length=%d "
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"dev_addr=0x%08x for write\n",
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channel, __func__, (unsigned int)dma_address,
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dma_length, dev_addr);
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imx_dmav1_writel(dma_address, DMA_SAR(channel));
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imx_dmav1_writel(dev_addr, DMA_DAR(channel));
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imx_dmav1_writel(imxdma->ccr_to_device,
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DMA_CCR(channel));
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} else {
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printk(KERN_ERR "imxdma%d: imx_dma_setup_single bad dmamode\n",
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channel);
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return -EINVAL;
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}
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imx_dmav1_writel(dma_length, DMA_CNTR(channel));
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return 0;
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}
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EXPORT_SYMBOL(imx_dma_setup_single);
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/**
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* imx_dma_setup_sg - setup i.MX DMA channel SG list to/from device transfer
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* @channel: i.MX DMA channel number
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* @sg: pointer to the scatter-gather list/vector
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* @sgcount: scatter-gather list hungs count
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* @dma_length: total length of the transfer request in bytes
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* @dev_addr: physical device port address
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* @dmamode: DMA transfer mode, %DMA_MODE_READ from the device to the memory
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* or %DMA_MODE_WRITE from memory to the device
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*
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* The function sets up DMA channel state and registers to be ready for
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* transfer specified by provided parameters. The scatter-gather emulation
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* is set up according to the parameters.
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*
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* The full preparation of the transfer requires setup of more register
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* by the caller before imx_dma_enable() can be called.
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*
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* %BLR(channel) holds transfer burst length in bytes, 0 means 64 bytes
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*
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* %RSSR(channel) has to be set to the DMA request line source %DMA_REQ_xxx
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*
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* %CCR(channel) has to specify transfer parameters, the next settings is
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* typical for linear or simple scatter-gather transfers if %DMA_MODE_READ is
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* specified
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*
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* %CCR_DMOD_LINEAR | %CCR_DSIZ_32 | %CCR_SMOD_FIFO | %CCR_SSIZ_x
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*
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* The typical setup for %DMA_MODE_WRITE is specified by next options
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* combination
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*
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* %CCR_SMOD_LINEAR | %CCR_SSIZ_32 | %CCR_DMOD_FIFO | %CCR_DSIZ_x
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*
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* Be careful here and do not mistakenly mix source and target device
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* port sizes constants, they are really different:
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* %CCR_SSIZ_8, %CCR_SSIZ_16, %CCR_SSIZ_32,
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* %CCR_DSIZ_8, %CCR_DSIZ_16, %CCR_DSIZ_32
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*
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* Return value: if incorrect parameters are provided -%EINVAL.
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* Zero indicates success.
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*/
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int
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imx_dma_setup_sg(int channel,
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struct scatterlist *sg, unsigned int sgcount,
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unsigned int dma_length, unsigned int dev_addr,
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unsigned int dmamode)
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{
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struct imx_dma_channel *imxdma = &imx_dma_channels[channel];
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if (imxdma->in_use)
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return -EBUSY;
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imxdma->sg = sg;
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imxdma->dma_mode = dmamode;
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imxdma->resbytes = dma_length;
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if (!sg || !sgcount) {
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printk(KERN_ERR "imxdma%d: imx_dma_setup_sg empty sg list\n",
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channel);
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return -EINVAL;
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}
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if (!sg->length) {
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printk(KERN_ERR "imxdma%d: imx_dma_setup_sg zero length\n",
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channel);
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return -EINVAL;
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}
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if ((dmamode & DMA_MODE_MASK) == DMA_MODE_READ) {
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pr_debug("imxdma%d: %s sg=%p sgcount=%d total length=%d "
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"dev_addr=0x%08x for read\n",
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channel, __func__, sg, sgcount, dma_length, dev_addr);
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imx_dmav1_writel(dev_addr, DMA_SAR(channel));
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imx_dmav1_writel(imxdma->ccr_from_device, DMA_CCR(channel));
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} else if ((dmamode & DMA_MODE_MASK) == DMA_MODE_WRITE) {
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pr_debug("imxdma%d: %s sg=%p sgcount=%d total length=%d "
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"dev_addr=0x%08x for write\n",
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channel, __func__, sg, sgcount, dma_length, dev_addr);
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imx_dmav1_writel(dev_addr, DMA_DAR(channel));
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imx_dmav1_writel(imxdma->ccr_to_device, DMA_CCR(channel));
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} else {
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printk(KERN_ERR "imxdma%d: imx_dma_setup_sg bad dmamode\n",
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channel);
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return -EINVAL;
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}
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imx_dma_sg_next(channel, sg);
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return 0;
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}
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EXPORT_SYMBOL(imx_dma_setup_sg);
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int
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imx_dma_config_channel(int channel, unsigned int config_port,
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unsigned int config_mem, unsigned int dmareq, int hw_chaining)
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{
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struct imx_dma_channel *imxdma = &imx_dma_channels[channel];
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u32 dreq = 0;
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imxdma->hw_chaining = 0;
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if (hw_chaining) {
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imxdma->hw_chaining = 1;
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if (!imx_dma_hw_chain(imxdma))
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return -EINVAL;
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}
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if (dmareq)
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dreq = CCR_REN;
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imxdma->ccr_from_device = config_port | (config_mem << 2) | dreq;
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imxdma->ccr_to_device = config_mem | (config_port << 2) | dreq;
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imx_dmav1_writel(dmareq, DMA_RSSR(channel));
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return 0;
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}
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EXPORT_SYMBOL(imx_dma_config_channel);
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void imx_dma_config_burstlen(int channel, unsigned int burstlen)
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{
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imx_dmav1_writel(burstlen, DMA_BLR(channel));
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}
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EXPORT_SYMBOL(imx_dma_config_burstlen);
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/**
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* imx_dma_setup_handlers - setup i.MX DMA channel end and error notification
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* handlers
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* @channel: i.MX DMA channel number
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* @irq_handler: the pointer to the function called if the transfer
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* ends successfully
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* @err_handler: the pointer to the function called if the premature
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* end caused by error occurs
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* @data: user specified value to be passed to the handlers
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*/
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int
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imx_dma_setup_handlers(int channel,
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void (*irq_handler) (int, void *),
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void (*err_handler) (int, void *, int),
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void *data)
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{
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struct imx_dma_channel *imxdma = &imx_dma_channels[channel];
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unsigned long flags;
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if (!imxdma->name) {
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printk(KERN_CRIT "%s: called for not allocated channel %d\n",
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__func__, channel);
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return -ENODEV;
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}
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local_irq_save(flags);
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imx_dmav1_writel(1 << channel, DMA_DISR);
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imxdma->irq_handler = irq_handler;
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imxdma->err_handler = err_handler;
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imxdma->data = data;
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local_irq_restore(flags);
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return 0;
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}
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EXPORT_SYMBOL(imx_dma_setup_handlers);
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/**
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* imx_dma_setup_progression_handler - setup i.MX DMA channel progression
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* handlers
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* @channel: i.MX DMA channel number
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* @prog_handler: the pointer to the function called if the transfer progresses
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*/
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int
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imx_dma_setup_progression_handler(int channel,
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void (*prog_handler) (int, void*, struct scatterlist*))
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{
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struct imx_dma_channel *imxdma = &imx_dma_channels[channel];
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unsigned long flags;
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if (!imxdma->name) {
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printk(KERN_CRIT "%s: called for not allocated channel %d\n",
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__func__, channel);
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return -ENODEV;
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}
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local_irq_save(flags);
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imxdma->prog_handler = prog_handler;
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local_irq_restore(flags);
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return 0;
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}
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EXPORT_SYMBOL(imx_dma_setup_progression_handler);
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/**
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* imx_dma_enable - function to start i.MX DMA channel operation
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* @channel: i.MX DMA channel number
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*
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* The channel has to be allocated by driver through imx_dma_request()
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* or imx_dma_request_by_prio() function.
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* The transfer parameters has to be set to the channel registers through
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* call of the imx_dma_setup_single() or imx_dma_setup_sg() function
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* and registers %BLR(channel), %RSSR(channel) and %CCR(channel) has to
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* be set prior this function call by the channel user.
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*/
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void imx_dma_enable(int channel)
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{
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struct imx_dma_channel *imxdma = &imx_dma_channels[channel];
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unsigned long flags;
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pr_debug("imxdma%d: imx_dma_enable\n", channel);
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if (!imxdma->name) {
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printk(KERN_CRIT "%s: called for not allocated channel %d\n",
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__func__, channel);
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return;
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}
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if (imxdma->in_use)
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return;
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local_irq_save(flags);
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imx_dmav1_writel(1 << channel, DMA_DISR);
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imx_dmav1_writel(imx_dmav1_readl(DMA_DIMR) & ~(1 << channel), DMA_DIMR);
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imx_dmav1_writel(imx_dmav1_readl(DMA_CCR(channel)) | CCR_CEN |
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CCR_ACRPT, DMA_CCR(channel));
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#ifdef CONFIG_ARCH_MX2
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if ((cpu_is_mx21() || cpu_is_mx27()) &&
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imxdma->sg && imx_dma_hw_chain(imxdma)) {
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imxdma->sg = sg_next(imxdma->sg);
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if (imxdma->sg) {
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u32 tmp;
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imx_dma_sg_next(channel, imxdma->sg);
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tmp = imx_dmav1_readl(DMA_CCR(channel));
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imx_dmav1_writel(tmp | CCR_RPT | CCR_ACRPT,
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DMA_CCR(channel));
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}
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}
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#endif
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imxdma->in_use = 1;
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local_irq_restore(flags);
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}
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EXPORT_SYMBOL(imx_dma_enable);
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/**
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* imx_dma_disable - stop, finish i.MX DMA channel operatin
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* @channel: i.MX DMA channel number
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*/
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void imx_dma_disable(int channel)
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{
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struct imx_dma_channel *imxdma = &imx_dma_channels[channel];
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unsigned long flags;
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pr_debug("imxdma%d: imx_dma_disable\n", channel);
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if (imx_dma_hw_chain(imxdma))
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del_timer(&imxdma->watchdog);
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local_irq_save(flags);
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imx_dmav1_writel(imx_dmav1_readl(DMA_DIMR) | (1 << channel), DMA_DIMR);
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imx_dmav1_writel(imx_dmav1_readl(DMA_CCR(channel)) & ~CCR_CEN,
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DMA_CCR(channel));
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imx_dmav1_writel(1 << channel, DMA_DISR);
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imxdma->in_use = 0;
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local_irq_restore(flags);
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}
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EXPORT_SYMBOL(imx_dma_disable);
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#ifdef CONFIG_ARCH_MX2
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static void imx_dma_watchdog(unsigned long chno)
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{
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struct imx_dma_channel *imxdma = &imx_dma_channels[chno];
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imx_dmav1_writel(0, DMA_CCR(chno));
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imxdma->in_use = 0;
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imxdma->sg = NULL;
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if (imxdma->err_handler)
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imxdma->err_handler(chno, imxdma->data, IMX_DMA_ERR_TIMEOUT);
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}
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#endif
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static irqreturn_t dma_err_handler(int irq, void *dev_id)
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{
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int i, disr;
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struct imx_dma_channel *imxdma;
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unsigned int err_mask;
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int errcode;
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disr = imx_dmav1_readl(DMA_DISR);
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err_mask = imx_dmav1_readl(DMA_DBTOSR) |
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imx_dmav1_readl(DMA_DRTOSR) |
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imx_dmav1_readl(DMA_DSESR) |
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imx_dmav1_readl(DMA_DBOSR);
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if (!err_mask)
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return IRQ_HANDLED;
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imx_dmav1_writel(disr & err_mask, DMA_DISR);
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for (i = 0; i < IMX_DMA_CHANNELS; i++) {
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if (!(err_mask & (1 << i)))
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continue;
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imxdma = &imx_dma_channels[i];
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errcode = 0;
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if (imx_dmav1_readl(DMA_DBTOSR) & (1 << i)) {
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imx_dmav1_writel(1 << i, DMA_DBTOSR);
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errcode |= IMX_DMA_ERR_BURST;
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}
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if (imx_dmav1_readl(DMA_DRTOSR) & (1 << i)) {
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imx_dmav1_writel(1 << i, DMA_DRTOSR);
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errcode |= IMX_DMA_ERR_REQUEST;
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}
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if (imx_dmav1_readl(DMA_DSESR) & (1 << i)) {
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imx_dmav1_writel(1 << i, DMA_DSESR);
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errcode |= IMX_DMA_ERR_TRANSFER;
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}
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if (imx_dmav1_readl(DMA_DBOSR) & (1 << i)) {
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imx_dmav1_writel(1 << i, DMA_DBOSR);
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errcode |= IMX_DMA_ERR_BUFFER;
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}
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if (imxdma->name && imxdma->err_handler) {
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imxdma->err_handler(i, imxdma->data, errcode);
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continue;
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}
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imx_dma_channels[i].sg = NULL;
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printk(KERN_WARNING
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"DMA timeout on channel %d (%s) -%s%s%s%s\n",
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i, imxdma->name,
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errcode & IMX_DMA_ERR_BURST ? " burst" : "",
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errcode & IMX_DMA_ERR_REQUEST ? " request" : "",
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errcode & IMX_DMA_ERR_TRANSFER ? " transfer" : "",
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errcode & IMX_DMA_ERR_BUFFER ? " buffer" : "");
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}
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return IRQ_HANDLED;
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}
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static void dma_irq_handle_channel(int chno)
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{
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struct imx_dma_channel *imxdma = &imx_dma_channels[chno];
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if (!imxdma->name) {
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/*
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* IRQ for an unregistered DMA channel:
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* let's clear the interrupts and disable it.
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*/
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printk(KERN_WARNING
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"spurious IRQ for DMA channel %d\n", chno);
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return;
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}
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if (imxdma->sg) {
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u32 tmp;
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struct scatterlist *current_sg = imxdma->sg;
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imxdma->sg = sg_next(imxdma->sg);
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if (imxdma->sg) {
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imx_dma_sg_next(chno, imxdma->sg);
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tmp = imx_dmav1_readl(DMA_CCR(chno));
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if (imx_dma_hw_chain(imxdma)) {
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/* FIXME: The timeout should probably be
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* configurable
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*/
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mod_timer(&imxdma->watchdog,
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jiffies + msecs_to_jiffies(500));
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tmp |= CCR_CEN | CCR_RPT | CCR_ACRPT;
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imx_dmav1_writel(tmp, DMA_CCR(chno));
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} else {
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imx_dmav1_writel(tmp & ~CCR_CEN, DMA_CCR(chno));
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tmp |= CCR_CEN;
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}
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imx_dmav1_writel(tmp, DMA_CCR(chno));
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if (imxdma->prog_handler)
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imxdma->prog_handler(chno, imxdma->data,
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current_sg);
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return;
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}
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if (imx_dma_hw_chain(imxdma)) {
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del_timer(&imxdma->watchdog);
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return;
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}
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}
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imx_dmav1_writel(0, DMA_CCR(chno));
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imxdma->in_use = 0;
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if (imxdma->irq_handler)
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imxdma->irq_handler(chno, imxdma->data);
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}
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static irqreturn_t dma_irq_handler(int irq, void *dev_id)
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{
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int i, disr;
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#ifdef CONFIG_ARCH_MX2
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if (cpu_is_mx21() || cpu_is_mx27())
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dma_err_handler(irq, dev_id);
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#endif
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disr = imx_dmav1_readl(DMA_DISR);
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pr_debug("imxdma: dma_irq_handler called, disr=0x%08x\n",
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disr);
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imx_dmav1_writel(disr, DMA_DISR);
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for (i = 0; i < IMX_DMA_CHANNELS; i++) {
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if (disr & (1 << i))
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dma_irq_handle_channel(i);
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}
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return IRQ_HANDLED;
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}
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/**
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* imx_dma_request - request/allocate specified channel number
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* @channel: i.MX DMA channel number
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* @name: the driver/caller own non-%NULL identification
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*/
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int imx_dma_request(int channel, const char *name)
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{
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struct imx_dma_channel *imxdma = &imx_dma_channels[channel];
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unsigned long flags;
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int ret = 0;
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/* basic sanity checks */
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if (!name)
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return -EINVAL;
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if (channel >= IMX_DMA_CHANNELS) {
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printk(KERN_CRIT "%s: called for non-existed channel %d\n",
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__func__, channel);
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return -EINVAL;
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}
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local_irq_save(flags);
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if (imxdma->name) {
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local_irq_restore(flags);
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return -EBUSY;
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}
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memset(imxdma, 0, sizeof(imxdma));
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imxdma->name = name;
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local_irq_restore(flags); /* request_irq() can block */
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#ifdef CONFIG_ARCH_MX2
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if (cpu_is_mx21() || cpu_is_mx27()) {
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ret = request_irq(MX2x_INT_DMACH0 + channel,
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dma_irq_handler, 0, "DMA", NULL);
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if (ret) {
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imxdma->name = NULL;
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pr_crit("Can't register IRQ %d for DMA channel %d\n",
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MX2x_INT_DMACH0 + channel, channel);
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return ret;
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}
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init_timer(&imxdma->watchdog);
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imxdma->watchdog.function = &imx_dma_watchdog;
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imxdma->watchdog.data = channel;
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}
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#endif
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return ret;
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}
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EXPORT_SYMBOL(imx_dma_request);
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|
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/**
|
|
* imx_dma_free - release previously acquired channel
|
|
* @channel: i.MX DMA channel number
|
|
*/
|
|
void imx_dma_free(int channel)
|
|
{
|
|
unsigned long flags;
|
|
struct imx_dma_channel *imxdma = &imx_dma_channels[channel];
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|
|
|
if (!imxdma->name) {
|
|
printk(KERN_CRIT
|
|
"%s: trying to free free channel %d\n",
|
|
__func__, channel);
|
|
return;
|
|
}
|
|
|
|
local_irq_save(flags);
|
|
/* Disable interrupts */
|
|
imx_dma_disable(channel);
|
|
imxdma->name = NULL;
|
|
|
|
#ifdef CONFIG_ARCH_MX2
|
|
if (cpu_is_mx21() || cpu_is_mx27())
|
|
free_irq(MX2x_INT_DMACH0 + channel, NULL);
|
|
#endif
|
|
|
|
local_irq_restore(flags);
|
|
}
|
|
EXPORT_SYMBOL(imx_dma_free);
|
|
|
|
/**
|
|
* imx_dma_request_by_prio - find and request some of free channels best
|
|
* suiting requested priority
|
|
* @channel: i.MX DMA channel number
|
|
* @name: the driver/caller own non-%NULL identification
|
|
*
|
|
* This function tries to find a free channel in the specified priority group
|
|
* if the priority cannot be achieved it tries to look for free channel
|
|
* in the higher and then even lower priority groups.
|
|
*
|
|
* Return value: If there is no free channel to allocate, -%ENODEV is returned.
|
|
* On successful allocation channel is returned.
|
|
*/
|
|
int imx_dma_request_by_prio(const char *name, enum imx_dma_prio prio)
|
|
{
|
|
int i;
|
|
int best;
|
|
|
|
switch (prio) {
|
|
case (DMA_PRIO_HIGH):
|
|
best = 8;
|
|
break;
|
|
case (DMA_PRIO_MEDIUM):
|
|
best = 4;
|
|
break;
|
|
case (DMA_PRIO_LOW):
|
|
default:
|
|
best = 0;
|
|
break;
|
|
}
|
|
|
|
for (i = best; i < IMX_DMA_CHANNELS; i++)
|
|
if (!imx_dma_request(i, name))
|
|
return i;
|
|
|
|
for (i = best - 1; i >= 0; i--)
|
|
if (!imx_dma_request(i, name))
|
|
return i;
|
|
|
|
printk(KERN_ERR "%s: no free DMA channel found\n", __func__);
|
|
|
|
return -ENODEV;
|
|
}
|
|
EXPORT_SYMBOL(imx_dma_request_by_prio);
|
|
|
|
static int __init imx_dma_init(void)
|
|
{
|
|
int ret = 0;
|
|
int i;
|
|
|
|
#ifdef CONFIG_ARCH_MX1
|
|
if (cpu_is_mx1())
|
|
imx_dmav1_baseaddr = MX1_IO_ADDRESS(MX1_DMA_BASE_ADDR);
|
|
else
|
|
#endif
|
|
#ifdef CONFIG_MACH_MX21
|
|
if (cpu_is_mx21())
|
|
imx_dmav1_baseaddr = MX21_IO_ADDRESS(MX21_DMA_BASE_ADDR);
|
|
else
|
|
#endif
|
|
#ifdef CONFIG_MACH_MX27
|
|
if (cpu_is_mx27())
|
|
imx_dmav1_baseaddr = MX27_IO_ADDRESS(MX27_DMA_BASE_ADDR);
|
|
else
|
|
#endif
|
|
BUG();
|
|
|
|
dma_clk = clk_get(NULL, "dma");
|
|
clk_enable(dma_clk);
|
|
|
|
/* reset DMA module */
|
|
imx_dmav1_writel(DCR_DRST, DMA_DCR);
|
|
|
|
#ifdef CONFIG_ARCH_MX1
|
|
if (cpu_is_mx1()) {
|
|
ret = request_irq(MX1_DMA_INT, dma_irq_handler, 0, "DMA", NULL);
|
|
if (ret) {
|
|
pr_crit("Wow! Can't register IRQ for DMA\n");
|
|
return ret;
|
|
}
|
|
|
|
ret = request_irq(MX1_DMA_ERR, dma_err_handler, 0, "DMA", NULL);
|
|
if (ret) {
|
|
pr_crit("Wow! Can't register ERRIRQ for DMA\n");
|
|
free_irq(MX1_DMA_INT, NULL);
|
|
return ret;
|
|
}
|
|
}
|
|
#endif
|
|
/* enable DMA module */
|
|
imx_dmav1_writel(DCR_DEN, DMA_DCR);
|
|
|
|
/* clear all interrupts */
|
|
imx_dmav1_writel((1 << IMX_DMA_CHANNELS) - 1, DMA_DISR);
|
|
|
|
/* disable interrupts */
|
|
imx_dmav1_writel((1 << IMX_DMA_CHANNELS) - 1, DMA_DIMR);
|
|
|
|
for (i = 0; i < IMX_DMA_CHANNELS; i++) {
|
|
imx_dma_channels[i].sg = NULL;
|
|
imx_dma_channels[i].dma_num = i;
|
|
}
|
|
|
|
return ret;
|
|
}
|
|
|
|
arch_initcall(imx_dma_init);
|