Christoffer Dall 5b0d2cc280 KVM: arm64: Ensure LRs are clear when they should be ... We currently have some code to clear the list registers on GICv3, but we never call this code, because the caller got nuked when removing the old vgic. We also used to have a similar GICv2 part, but that got lost in the process too. Let's reintroduce the logic for GICv2 and call the logic when we initialize the use of hypervisors on the CPU, for example when first loading KVM or when exiting a low power state. Reviewed-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>		2017-04-04 14:33:58 +02:00
..
arm_arch_timer.h	KVM: arm/arm64: Emulate the EL1 phys timer registers	2017-02-08 15:13:37 +00:00
arm_pmu.h	arm64: KVM: fix build with CONFIG_ARM_PMU disabled	2016-06-27 12:55:51 +02:00
arm_vgic.h	KVM: arm64: Ensure LRs are clear when they should be	2017-04-04 14:33:58 +02:00
iodev.h	…