1154 строки
25 KiB
C
1154 строки
25 KiB
C
#include <linux/module.h>
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#include <linux/slab.h>
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#include "mce_amd.h"
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static struct amd_decoder_ops *fam_ops;
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static u8 xec_mask = 0xf;
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static bool report_gart_errors;
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static void (*decode_dram_ecc)(int node_id, struct mce *m);
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void amd_report_gart_errors(bool v)
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{
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report_gart_errors = v;
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}
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EXPORT_SYMBOL_GPL(amd_report_gart_errors);
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void amd_register_ecc_decoder(void (*f)(int, struct mce *))
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{
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decode_dram_ecc = f;
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}
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EXPORT_SYMBOL_GPL(amd_register_ecc_decoder);
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void amd_unregister_ecc_decoder(void (*f)(int, struct mce *))
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{
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if (decode_dram_ecc) {
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WARN_ON(decode_dram_ecc != f);
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decode_dram_ecc = NULL;
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}
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}
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EXPORT_SYMBOL_GPL(amd_unregister_ecc_decoder);
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/*
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* string representation for the different MCA reported error types, see F3x48
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* or MSR0000_0411.
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*/
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/* transaction type */
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static const char * const tt_msgs[] = { "INSN", "DATA", "GEN", "RESV" };
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/* cache level */
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static const char * const ll_msgs[] = { "RESV", "L1", "L2", "L3/GEN" };
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/* memory transaction type */
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static const char * const rrrr_msgs[] = {
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"GEN", "RD", "WR", "DRD", "DWR", "IRD", "PRF", "EV", "SNP"
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};
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/* participating processor */
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const char * const pp_msgs[] = { "SRC", "RES", "OBS", "GEN" };
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EXPORT_SYMBOL_GPL(pp_msgs);
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/* request timeout */
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static const char * const to_msgs[] = { "no timeout", "timed out" };
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/* memory or i/o */
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static const char * const ii_msgs[] = { "MEM", "RESV", "IO", "GEN" };
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/* internal error type */
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static const char * const uu_msgs[] = { "RESV", "RESV", "HWA", "RESV" };
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static const char * const f15h_mc1_mce_desc[] = {
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"UC during a demand linefill from L2",
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"Parity error during data load from IC",
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"Parity error for IC valid bit",
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"Main tag parity error",
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"Parity error in prediction queue",
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"PFB data/address parity error",
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"Parity error in the branch status reg",
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"PFB promotion address error",
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"Tag error during probe/victimization",
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"Parity error for IC probe tag valid bit",
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"PFB non-cacheable bit parity error",
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"PFB valid bit parity error", /* xec = 0xd */
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"Microcode Patch Buffer", /* xec = 010 */
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"uop queue",
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"insn buffer",
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"predecode buffer",
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"fetch address FIFO",
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"dispatch uop queue"
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};
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static const char * const f15h_mc2_mce_desc[] = {
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"Fill ECC error on data fills", /* xec = 0x4 */
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"Fill parity error on insn fills",
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"Prefetcher request FIFO parity error",
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"PRQ address parity error",
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"PRQ data parity error",
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"WCC Tag ECC error",
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"WCC Data ECC error",
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"WCB Data parity error",
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"VB Data ECC or parity error",
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"L2 Tag ECC error", /* xec = 0x10 */
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"Hard L2 Tag ECC error",
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"Multiple hits on L2 tag",
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"XAB parity error",
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"PRB address parity error"
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};
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static const char * const mc4_mce_desc[] = {
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"DRAM ECC error detected on the NB",
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"CRC error detected on HT link",
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"Link-defined sync error packets detected on HT link",
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"HT Master abort",
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"HT Target abort",
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"Invalid GART PTE entry during GART table walk",
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"Unsupported atomic RMW received from an IO link",
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"Watchdog timeout due to lack of progress",
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"DRAM ECC error detected on the NB",
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"SVM DMA Exclusion Vector error",
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"HT data error detected on link",
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"Protocol error (link, L3, probe filter)",
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"NB internal arrays parity error",
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"DRAM addr/ctl signals parity error",
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"IO link transmission error",
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"L3 data cache ECC error", /* xec = 0x1c */
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"L3 cache tag error",
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"L3 LRU parity bits error",
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"ECC Error in the Probe Filter directory"
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};
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static const char * const mc5_mce_desc[] = {
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"CPU Watchdog timer expire",
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"Wakeup array dest tag",
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"AG payload array",
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"EX payload array",
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"IDRF array",
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"Retire dispatch queue",
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"Mapper checkpoint array",
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"Physical register file EX0 port",
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"Physical register file EX1 port",
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"Physical register file AG0 port",
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"Physical register file AG1 port",
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"Flag register file",
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"DE error occurred",
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"Retire status queue"
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};
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static const char * const mc6_mce_desc[] = {
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"Hardware Assertion",
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"Free List",
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"Physical Register File",
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"Retire Queue",
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"Scheduler table",
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"Status Register File",
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};
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/* Scalable MCA error strings */
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static const char * const smca_ls_mce_desc[] = {
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"Load queue parity",
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"Store queue parity",
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"Miss address buffer payload parity",
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"L1 TLB parity",
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"Reserved",
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"DC tag error type 6",
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"DC tag error type 1",
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"Internal error type 1",
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"Internal error type 2",
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"Sys Read data error thread 0",
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"Sys read data error thread 1",
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"DC tag error type 2",
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"DC data error type 1 (poison consumption)",
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"DC data error type 2",
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"DC data error type 3",
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"DC tag error type 4",
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"L2 TLB parity",
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"PDC parity error",
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"DC tag error type 3",
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"DC tag error type 5",
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"L2 fill data error",
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};
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static const char * const smca_if_mce_desc[] = {
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"microtag probe port parity error",
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"IC microtag or full tag multi-hit error",
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"IC full tag parity",
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"IC data array parity",
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"Decoupling queue phys addr parity error",
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"L0 ITLB parity error",
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"L1 ITLB parity error",
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"L2 ITLB parity error",
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"BPQ snoop parity on Thread 0",
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"BPQ snoop parity on Thread 1",
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"L1 BTB multi-match error",
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"L2 BTB multi-match error",
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"L2 Cache Response Poison error",
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"System Read Data error",
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};
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static const char * const smca_l2_mce_desc[] = {
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"L2M tag multi-way-hit error",
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"L2M tag ECC error",
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"L2M data ECC error",
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"HW assert",
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};
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static const char * const smca_de_mce_desc[] = {
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"uop cache tag parity error",
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"uop cache data parity error",
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"Insn buffer parity error",
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"uop queue parity error",
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"Insn dispatch queue parity error",
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"Fetch address FIFO parity",
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"Patch RAM data parity",
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"Patch RAM sequencer parity",
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"uop buffer parity"
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};
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static const char * const smca_ex_mce_desc[] = {
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"Watchdog timeout error",
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"Phy register file parity",
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"Flag register file parity",
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"Immediate displacement register file parity",
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"Address generator payload parity",
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"EX payload parity",
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"Checkpoint queue parity",
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"Retire dispatch queue parity",
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"Retire status queue parity error",
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"Scheduling queue parity error",
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"Branch buffer queue parity error",
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};
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static const char * const smca_fp_mce_desc[] = {
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"Physical register file parity",
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"Freelist parity error",
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"Schedule queue parity",
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"NSQ parity error",
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"Retire queue parity",
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"Status register file parity",
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"Hardware assertion",
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};
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static const char * const smca_l3_mce_desc[] = {
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"Shadow tag macro ECC error",
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"Shadow tag macro multi-way-hit error",
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"L3M tag ECC error",
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"L3M tag multi-way-hit error",
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"L3M data ECC error",
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"XI parity, L3 fill done channel error",
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"L3 victim queue parity",
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"L3 HW assert",
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};
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static const char * const smca_cs_mce_desc[] = {
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"Illegal request from transport layer",
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"Address violation",
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"Security violation",
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"Illegal response from transport layer",
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"Unexpected response",
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"Parity error on incoming request or probe response data",
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"Parity error on incoming read response data",
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"Atomic request parity",
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"ECC error on probe filter access",
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};
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static const char * const smca_pie_mce_desc[] = {
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"HW assert",
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"Internal PIE register security violation",
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"Error on GMI link",
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"Poison data written to internal PIE register",
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};
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static const char * const smca_umc_mce_desc[] = {
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"DRAM ECC error",
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"Data poison error on DRAM",
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"SDP parity error",
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"Advanced peripheral bus error",
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"Command/address parity error",
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"Write data CRC error",
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};
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static const char * const smca_pb_mce_desc[] = {
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"Parameter Block RAM ECC error",
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};
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static const char * const smca_psp_mce_desc[] = {
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"PSP RAM ECC or parity error",
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};
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static const char * const smca_smu_mce_desc[] = {
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"SMU RAM ECC or parity error",
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};
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struct smca_mce_desc {
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const char * const *descs;
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unsigned int num_descs;
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};
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static struct smca_mce_desc smca_mce_descs[] = {
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[SMCA_LS] = { smca_ls_mce_desc, ARRAY_SIZE(smca_ls_mce_desc) },
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[SMCA_IF] = { smca_if_mce_desc, ARRAY_SIZE(smca_if_mce_desc) },
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[SMCA_L2_CACHE] = { smca_l2_mce_desc, ARRAY_SIZE(smca_l2_mce_desc) },
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[SMCA_DE] = { smca_de_mce_desc, ARRAY_SIZE(smca_de_mce_desc) },
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[SMCA_EX] = { smca_ex_mce_desc, ARRAY_SIZE(smca_ex_mce_desc) },
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[SMCA_FP] = { smca_fp_mce_desc, ARRAY_SIZE(smca_fp_mce_desc) },
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[SMCA_L3_CACHE] = { smca_l3_mce_desc, ARRAY_SIZE(smca_l3_mce_desc) },
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[SMCA_CS] = { smca_cs_mce_desc, ARRAY_SIZE(smca_cs_mce_desc) },
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[SMCA_PIE] = { smca_pie_mce_desc, ARRAY_SIZE(smca_pie_mce_desc) },
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[SMCA_UMC] = { smca_umc_mce_desc, ARRAY_SIZE(smca_umc_mce_desc) },
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[SMCA_PB] = { smca_pb_mce_desc, ARRAY_SIZE(smca_pb_mce_desc) },
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[SMCA_PSP] = { smca_psp_mce_desc, ARRAY_SIZE(smca_psp_mce_desc) },
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[SMCA_SMU] = { smca_smu_mce_desc, ARRAY_SIZE(smca_smu_mce_desc) },
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};
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static bool f12h_mc0_mce(u16 ec, u8 xec)
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{
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bool ret = false;
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if (MEM_ERROR(ec)) {
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u8 ll = LL(ec);
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ret = true;
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if (ll == LL_L2)
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pr_cont("during L1 linefill from L2.\n");
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else if (ll == LL_L1)
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pr_cont("Data/Tag %s error.\n", R4_MSG(ec));
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else
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ret = false;
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}
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return ret;
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}
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static bool f10h_mc0_mce(u16 ec, u8 xec)
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{
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if (R4(ec) == R4_GEN && LL(ec) == LL_L1) {
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pr_cont("during data scrub.\n");
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return true;
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}
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return f12h_mc0_mce(ec, xec);
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}
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static bool k8_mc0_mce(u16 ec, u8 xec)
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{
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if (BUS_ERROR(ec)) {
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pr_cont("during system linefill.\n");
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return true;
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}
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return f10h_mc0_mce(ec, xec);
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}
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static bool cat_mc0_mce(u16 ec, u8 xec)
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{
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u8 r4 = R4(ec);
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bool ret = true;
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if (MEM_ERROR(ec)) {
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if (TT(ec) != TT_DATA || LL(ec) != LL_L1)
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return false;
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switch (r4) {
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case R4_DRD:
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case R4_DWR:
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pr_cont("Data/Tag parity error due to %s.\n",
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(r4 == R4_DRD ? "load/hw prf" : "store"));
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break;
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case R4_EVICT:
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pr_cont("Copyback parity error on a tag miss.\n");
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break;
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case R4_SNOOP:
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pr_cont("Tag parity error during snoop.\n");
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break;
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default:
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ret = false;
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}
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} else if (BUS_ERROR(ec)) {
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if ((II(ec) != II_MEM && II(ec) != II_IO) || LL(ec) != LL_LG)
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return false;
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pr_cont("System read data error on a ");
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switch (r4) {
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case R4_RD:
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pr_cont("TLB reload.\n");
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break;
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case R4_DWR:
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pr_cont("store.\n");
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break;
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case R4_DRD:
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pr_cont("load.\n");
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break;
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default:
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ret = false;
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}
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} else {
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ret = false;
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}
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return ret;
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}
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static bool f15h_mc0_mce(u16 ec, u8 xec)
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{
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bool ret = true;
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if (MEM_ERROR(ec)) {
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switch (xec) {
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case 0x0:
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pr_cont("Data Array access error.\n");
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break;
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case 0x1:
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pr_cont("UC error during a linefill from L2/NB.\n");
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break;
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case 0x2:
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case 0x11:
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pr_cont("STQ access error.\n");
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break;
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case 0x3:
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pr_cont("SCB access error.\n");
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break;
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case 0x10:
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pr_cont("Tag error.\n");
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break;
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case 0x12:
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pr_cont("LDQ access error.\n");
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break;
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default:
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ret = false;
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}
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} else if (BUS_ERROR(ec)) {
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if (!xec)
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pr_cont("System Read Data Error.\n");
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else
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pr_cont(" Internal error condition type %d.\n", xec);
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} else if (INT_ERROR(ec)) {
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if (xec <= 0x1f)
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pr_cont("Hardware Assert.\n");
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else
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ret = false;
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} else
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ret = false;
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return ret;
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}
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static void decode_mc0_mce(struct mce *m)
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{
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u16 ec = EC(m->status);
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u8 xec = XEC(m->status, xec_mask);
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pr_emerg(HW_ERR "MC0 Error: ");
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/* TLB error signatures are the same across families */
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if (TLB_ERROR(ec)) {
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if (TT(ec) == TT_DATA) {
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pr_cont("%s TLB %s.\n", LL_MSG(ec),
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((xec == 2) ? "locked miss"
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: (xec ? "multimatch" : "parity")));
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return;
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}
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} else if (fam_ops->mc0_mce(ec, xec))
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;
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else
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pr_emerg(HW_ERR "Corrupted MC0 MCE info?\n");
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}
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static bool k8_mc1_mce(u16 ec, u8 xec)
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{
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u8 ll = LL(ec);
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bool ret = true;
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if (!MEM_ERROR(ec))
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return false;
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if (ll == 0x2)
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pr_cont("during a linefill from L2.\n");
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else if (ll == 0x1) {
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switch (R4(ec)) {
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case R4_IRD:
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pr_cont("Parity error during data load.\n");
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break;
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case R4_EVICT:
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pr_cont("Copyback Parity/Victim error.\n");
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break;
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case R4_SNOOP:
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pr_cont("Tag Snoop error.\n");
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break;
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default:
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ret = false;
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break;
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}
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} else
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ret = false;
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return ret;
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}
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static bool cat_mc1_mce(u16 ec, u8 xec)
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{
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u8 r4 = R4(ec);
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bool ret = true;
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if (!MEM_ERROR(ec))
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return false;
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if (TT(ec) != TT_INSTR)
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return false;
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if (r4 == R4_IRD)
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pr_cont("Data/tag array parity error for a tag hit.\n");
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else if (r4 == R4_SNOOP)
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pr_cont("Tag error during snoop/victimization.\n");
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else if (xec == 0x0)
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pr_cont("Tag parity error from victim castout.\n");
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else if (xec == 0x2)
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pr_cont("Microcode patch RAM parity error.\n");
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else
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ret = false;
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return ret;
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}
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static bool f15h_mc1_mce(u16 ec, u8 xec)
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{
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bool ret = true;
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if (!MEM_ERROR(ec))
|
|
return false;
|
|
|
|
switch (xec) {
|
|
case 0x0 ... 0xa:
|
|
pr_cont("%s.\n", f15h_mc1_mce_desc[xec]);
|
|
break;
|
|
|
|
case 0xd:
|
|
pr_cont("%s.\n", f15h_mc1_mce_desc[xec-2]);
|
|
break;
|
|
|
|
case 0x10:
|
|
pr_cont("%s.\n", f15h_mc1_mce_desc[xec-4]);
|
|
break;
|
|
|
|
case 0x11 ... 0x15:
|
|
pr_cont("Decoder %s parity error.\n", f15h_mc1_mce_desc[xec-4]);
|
|
break;
|
|
|
|
default:
|
|
ret = false;
|
|
}
|
|
return ret;
|
|
}
|
|
|
|
static void decode_mc1_mce(struct mce *m)
|
|
{
|
|
u16 ec = EC(m->status);
|
|
u8 xec = XEC(m->status, xec_mask);
|
|
|
|
pr_emerg(HW_ERR "MC1 Error: ");
|
|
|
|
if (TLB_ERROR(ec))
|
|
pr_cont("%s TLB %s.\n", LL_MSG(ec),
|
|
(xec ? "multimatch" : "parity error"));
|
|
else if (BUS_ERROR(ec)) {
|
|
bool k8 = (boot_cpu_data.x86 == 0xf && (m->status & BIT_64(58)));
|
|
|
|
pr_cont("during %s.\n", (k8 ? "system linefill" : "NB data read"));
|
|
} else if (INT_ERROR(ec)) {
|
|
if (xec <= 0x3f)
|
|
pr_cont("Hardware Assert.\n");
|
|
else
|
|
goto wrong_mc1_mce;
|
|
} else if (fam_ops->mc1_mce(ec, xec))
|
|
;
|
|
else
|
|
goto wrong_mc1_mce;
|
|
|
|
return;
|
|
|
|
wrong_mc1_mce:
|
|
pr_emerg(HW_ERR "Corrupted MC1 MCE info?\n");
|
|
}
|
|
|
|
static bool k8_mc2_mce(u16 ec, u8 xec)
|
|
{
|
|
bool ret = true;
|
|
|
|
if (xec == 0x1)
|
|
pr_cont(" in the write data buffers.\n");
|
|
else if (xec == 0x3)
|
|
pr_cont(" in the victim data buffers.\n");
|
|
else if (xec == 0x2 && MEM_ERROR(ec))
|
|
pr_cont(": %s error in the L2 cache tags.\n", R4_MSG(ec));
|
|
else if (xec == 0x0) {
|
|
if (TLB_ERROR(ec))
|
|
pr_cont("%s error in a Page Descriptor Cache or Guest TLB.\n",
|
|
TT_MSG(ec));
|
|
else if (BUS_ERROR(ec))
|
|
pr_cont(": %s/ECC error in data read from NB: %s.\n",
|
|
R4_MSG(ec), PP_MSG(ec));
|
|
else if (MEM_ERROR(ec)) {
|
|
u8 r4 = R4(ec);
|
|
|
|
if (r4 >= 0x7)
|
|
pr_cont(": %s error during data copyback.\n",
|
|
R4_MSG(ec));
|
|
else if (r4 <= 0x1)
|
|
pr_cont(": %s parity/ECC error during data "
|
|
"access from L2.\n", R4_MSG(ec));
|
|
else
|
|
ret = false;
|
|
} else
|
|
ret = false;
|
|
} else
|
|
ret = false;
|
|
|
|
return ret;
|
|
}
|
|
|
|
static bool f15h_mc2_mce(u16 ec, u8 xec)
|
|
{
|
|
bool ret = true;
|
|
|
|
if (TLB_ERROR(ec)) {
|
|
if (xec == 0x0)
|
|
pr_cont("Data parity TLB read error.\n");
|
|
else if (xec == 0x1)
|
|
pr_cont("Poison data provided for TLB fill.\n");
|
|
else
|
|
ret = false;
|
|
} else if (BUS_ERROR(ec)) {
|
|
if (xec > 2)
|
|
ret = false;
|
|
|
|
pr_cont("Error during attempted NB data read.\n");
|
|
} else if (MEM_ERROR(ec)) {
|
|
switch (xec) {
|
|
case 0x4 ... 0xc:
|
|
pr_cont("%s.\n", f15h_mc2_mce_desc[xec - 0x4]);
|
|
break;
|
|
|
|
case 0x10 ... 0x14:
|
|
pr_cont("%s.\n", f15h_mc2_mce_desc[xec - 0x7]);
|
|
break;
|
|
|
|
default:
|
|
ret = false;
|
|
}
|
|
} else if (INT_ERROR(ec)) {
|
|
if (xec <= 0x3f)
|
|
pr_cont("Hardware Assert.\n");
|
|
else
|
|
ret = false;
|
|
}
|
|
|
|
return ret;
|
|
}
|
|
|
|
static bool f16h_mc2_mce(u16 ec, u8 xec)
|
|
{
|
|
u8 r4 = R4(ec);
|
|
|
|
if (!MEM_ERROR(ec))
|
|
return false;
|
|
|
|
switch (xec) {
|
|
case 0x04 ... 0x05:
|
|
pr_cont("%cBUFF parity error.\n", (r4 == R4_RD) ? 'I' : 'O');
|
|
break;
|
|
|
|
case 0x09 ... 0x0b:
|
|
case 0x0d ... 0x0f:
|
|
pr_cont("ECC error in L2 tag (%s).\n",
|
|
((r4 == R4_GEN) ? "BankReq" :
|
|
((r4 == R4_SNOOP) ? "Prb" : "Fill")));
|
|
break;
|
|
|
|
case 0x10 ... 0x19:
|
|
case 0x1b:
|
|
pr_cont("ECC error in L2 data array (%s).\n",
|
|
(((r4 == R4_RD) && !(xec & 0x3)) ? "Hit" :
|
|
((r4 == R4_GEN) ? "Attr" :
|
|
((r4 == R4_EVICT) ? "Vict" : "Fill"))));
|
|
break;
|
|
|
|
case 0x1c ... 0x1d:
|
|
case 0x1f:
|
|
pr_cont("Parity error in L2 attribute bits (%s).\n",
|
|
((r4 == R4_RD) ? "Hit" :
|
|
((r4 == R4_GEN) ? "Attr" : "Fill")));
|
|
break;
|
|
|
|
default:
|
|
return false;
|
|
}
|
|
|
|
return true;
|
|
}
|
|
|
|
static void decode_mc2_mce(struct mce *m)
|
|
{
|
|
u16 ec = EC(m->status);
|
|
u8 xec = XEC(m->status, xec_mask);
|
|
|
|
pr_emerg(HW_ERR "MC2 Error: ");
|
|
|
|
if (!fam_ops->mc2_mce(ec, xec))
|
|
pr_cont(HW_ERR "Corrupted MC2 MCE info?\n");
|
|
}
|
|
|
|
static void decode_mc3_mce(struct mce *m)
|
|
{
|
|
u16 ec = EC(m->status);
|
|
u8 xec = XEC(m->status, xec_mask);
|
|
|
|
if (boot_cpu_data.x86 >= 0x14) {
|
|
pr_emerg("You shouldn't be seeing MC3 MCE on this cpu family,"
|
|
" please report on LKML.\n");
|
|
return;
|
|
}
|
|
|
|
pr_emerg(HW_ERR "MC3 Error");
|
|
|
|
if (xec == 0x0) {
|
|
u8 r4 = R4(ec);
|
|
|
|
if (!BUS_ERROR(ec) || (r4 != R4_DRD && r4 != R4_DWR))
|
|
goto wrong_mc3_mce;
|
|
|
|
pr_cont(" during %s.\n", R4_MSG(ec));
|
|
} else
|
|
goto wrong_mc3_mce;
|
|
|
|
return;
|
|
|
|
wrong_mc3_mce:
|
|
pr_emerg(HW_ERR "Corrupted MC3 MCE info?\n");
|
|
}
|
|
|
|
static void decode_mc4_mce(struct mce *m)
|
|
{
|
|
struct cpuinfo_x86 *c = &boot_cpu_data;
|
|
int node_id = amd_get_nb_id(m->extcpu);
|
|
u16 ec = EC(m->status);
|
|
u8 xec = XEC(m->status, 0x1f);
|
|
u8 offset = 0;
|
|
|
|
pr_emerg(HW_ERR "MC4 Error (node %d): ", node_id);
|
|
|
|
switch (xec) {
|
|
case 0x0 ... 0xe:
|
|
|
|
/* special handling for DRAM ECCs */
|
|
if (xec == 0x0 || xec == 0x8) {
|
|
/* no ECCs on F11h */
|
|
if (c->x86 == 0x11)
|
|
goto wrong_mc4_mce;
|
|
|
|
pr_cont("%s.\n", mc4_mce_desc[xec]);
|
|
|
|
if (decode_dram_ecc)
|
|
decode_dram_ecc(node_id, m);
|
|
return;
|
|
}
|
|
break;
|
|
|
|
case 0xf:
|
|
if (TLB_ERROR(ec))
|
|
pr_cont("GART Table Walk data error.\n");
|
|
else if (BUS_ERROR(ec))
|
|
pr_cont("DMA Exclusion Vector Table Walk error.\n");
|
|
else
|
|
goto wrong_mc4_mce;
|
|
return;
|
|
|
|
case 0x19:
|
|
if (boot_cpu_data.x86 == 0x15 || boot_cpu_data.x86 == 0x16)
|
|
pr_cont("Compute Unit Data Error.\n");
|
|
else
|
|
goto wrong_mc4_mce;
|
|
return;
|
|
|
|
case 0x1c ... 0x1f:
|
|
offset = 13;
|
|
break;
|
|
|
|
default:
|
|
goto wrong_mc4_mce;
|
|
}
|
|
|
|
pr_cont("%s.\n", mc4_mce_desc[xec - offset]);
|
|
return;
|
|
|
|
wrong_mc4_mce:
|
|
pr_emerg(HW_ERR "Corrupted MC4 MCE info?\n");
|
|
}
|
|
|
|
static void decode_mc5_mce(struct mce *m)
|
|
{
|
|
struct cpuinfo_x86 *c = &boot_cpu_data;
|
|
u16 ec = EC(m->status);
|
|
u8 xec = XEC(m->status, xec_mask);
|
|
|
|
if (c->x86 == 0xf || c->x86 == 0x11)
|
|
goto wrong_mc5_mce;
|
|
|
|
pr_emerg(HW_ERR "MC5 Error: ");
|
|
|
|
if (INT_ERROR(ec)) {
|
|
if (xec <= 0x1f) {
|
|
pr_cont("Hardware Assert.\n");
|
|
return;
|
|
} else
|
|
goto wrong_mc5_mce;
|
|
}
|
|
|
|
if (xec == 0x0 || xec == 0xc)
|
|
pr_cont("%s.\n", mc5_mce_desc[xec]);
|
|
else if (xec <= 0xd)
|
|
pr_cont("%s parity error.\n", mc5_mce_desc[xec]);
|
|
else
|
|
goto wrong_mc5_mce;
|
|
|
|
return;
|
|
|
|
wrong_mc5_mce:
|
|
pr_emerg(HW_ERR "Corrupted MC5 MCE info?\n");
|
|
}
|
|
|
|
static void decode_mc6_mce(struct mce *m)
|
|
{
|
|
u8 xec = XEC(m->status, xec_mask);
|
|
|
|
pr_emerg(HW_ERR "MC6 Error: ");
|
|
|
|
if (xec > 0x5)
|
|
goto wrong_mc6_mce;
|
|
|
|
pr_cont("%s parity error.\n", mc6_mce_desc[xec]);
|
|
return;
|
|
|
|
wrong_mc6_mce:
|
|
pr_emerg(HW_ERR "Corrupted MC6 MCE info?\n");
|
|
}
|
|
|
|
/* Decode errors according to Scalable MCA specification */
|
|
static void decode_smca_errors(struct mce *m)
|
|
{
|
|
struct smca_hwid *hwid;
|
|
unsigned int bank_type;
|
|
const char *ip_name;
|
|
u8 xec = XEC(m->status, xec_mask);
|
|
|
|
if (m->bank >= ARRAY_SIZE(smca_banks))
|
|
return;
|
|
|
|
if (boot_cpu_data.x86 >= 0x17 && m->bank == 4)
|
|
pr_emerg(HW_ERR "Bank 4 is reserved on Fam17h.\n");
|
|
|
|
hwid = smca_banks[m->bank].hwid;
|
|
if (!hwid)
|
|
return;
|
|
|
|
bank_type = hwid->bank_type;
|
|
ip_name = smca_get_long_name(bank_type);
|
|
|
|
pr_emerg(HW_ERR "%s Extended Error Code: %d\n", ip_name, xec);
|
|
|
|
/* Only print the decode of valid error codes */
|
|
if (xec < smca_mce_descs[bank_type].num_descs &&
|
|
(hwid->xec_bitmap & BIT_ULL(xec))) {
|
|
pr_emerg(HW_ERR "%s Error: ", ip_name);
|
|
pr_cont("%s.\n", smca_mce_descs[bank_type].descs[xec]);
|
|
}
|
|
|
|
/*
|
|
* amd_get_nb_id() returns the last level cache id.
|
|
* The last level cache on Fam17h is 1 level below the node.
|
|
*/
|
|
if (bank_type == SMCA_UMC && xec == 0 && decode_dram_ecc)
|
|
decode_dram_ecc(amd_get_nb_id(m->extcpu) >> 1, m);
|
|
}
|
|
|
|
static inline void amd_decode_err_code(u16 ec)
|
|
{
|
|
if (INT_ERROR(ec)) {
|
|
pr_emerg(HW_ERR "internal: %s\n", UU_MSG(ec));
|
|
return;
|
|
}
|
|
|
|
pr_emerg(HW_ERR "cache level: %s", LL_MSG(ec));
|
|
|
|
if (BUS_ERROR(ec))
|
|
pr_cont(", mem/io: %s", II_MSG(ec));
|
|
else
|
|
pr_cont(", tx: %s", TT_MSG(ec));
|
|
|
|
if (MEM_ERROR(ec) || BUS_ERROR(ec)) {
|
|
pr_cont(", mem-tx: %s", R4_MSG(ec));
|
|
|
|
if (BUS_ERROR(ec))
|
|
pr_cont(", part-proc: %s (%s)", PP_MSG(ec), TO_MSG(ec));
|
|
}
|
|
|
|
pr_cont("\n");
|
|
}
|
|
|
|
/*
|
|
* Filter out unwanted MCE signatures here.
|
|
*/
|
|
static bool amd_filter_mce(struct mce *m)
|
|
{
|
|
u8 xec = (m->status >> 16) & 0x1f;
|
|
|
|
/*
|
|
* NB GART TLB error reporting is disabled by default.
|
|
*/
|
|
if (m->bank == 4 && xec == 0x5 && !report_gart_errors)
|
|
return true;
|
|
|
|
return false;
|
|
}
|
|
|
|
static const char *decode_error_status(struct mce *m)
|
|
{
|
|
if (m->status & MCI_STATUS_UC) {
|
|
if (m->status & MCI_STATUS_PCC)
|
|
return "System Fatal error.";
|
|
if (m->mcgstatus & MCG_STATUS_RIPV)
|
|
return "Uncorrected, software restartable error.";
|
|
return "Uncorrected, software containable error.";
|
|
}
|
|
|
|
if (m->status & MCI_STATUS_DEFERRED)
|
|
return "Deferred error, no action required.";
|
|
|
|
return "Corrected error, no action required.";
|
|
}
|
|
|
|
static int
|
|
amd_decode_mce(struct notifier_block *nb, unsigned long val, void *data)
|
|
{
|
|
struct mce *m = (struct mce *)data;
|
|
struct cpuinfo_x86 *c = &cpu_data(m->extcpu);
|
|
int ecc;
|
|
|
|
if (amd_filter_mce(m))
|
|
return NOTIFY_STOP;
|
|
|
|
pr_emerg(HW_ERR "%s\n", decode_error_status(m));
|
|
|
|
pr_emerg(HW_ERR "CPU:%d (%x:%x:%x) MC%d_STATUS[%s|%s|%s|%s|%s",
|
|
m->extcpu,
|
|
c->x86, c->x86_model, c->x86_mask,
|
|
m->bank,
|
|
((m->status & MCI_STATUS_OVER) ? "Over" : "-"),
|
|
((m->status & MCI_STATUS_UC) ? "UE" :
|
|
(m->status & MCI_STATUS_DEFERRED) ? "-" : "CE"),
|
|
((m->status & MCI_STATUS_MISCV) ? "MiscV" : "-"),
|
|
((m->status & MCI_STATUS_PCC) ? "PCC" : "-"),
|
|
((m->status & MCI_STATUS_ADDRV) ? "AddrV" : "-"));
|
|
|
|
if (c->x86 >= 0x15) {
|
|
pr_cont("|%s", (m->status & MCI_STATUS_DEFERRED ? "Deferred" : "-"));
|
|
|
|
/* F15h, bank4, bit 43 is part of McaStatSubCache. */
|
|
if (c->x86 != 0x15 || m->bank != 4)
|
|
pr_cont("|%s", (m->status & MCI_STATUS_POISON ? "Poison" : "-"));
|
|
}
|
|
|
|
if (boot_cpu_has(X86_FEATURE_SMCA)) {
|
|
u32 low, high;
|
|
u32 addr = MSR_AMD64_SMCA_MCx_CONFIG(m->bank);
|
|
|
|
pr_cont("|%s", ((m->status & MCI_STATUS_SYNDV) ? "SyndV" : "-"));
|
|
|
|
if (!rdmsr_safe(addr, &low, &high) &&
|
|
(low & MCI_CONFIG_MCAX))
|
|
pr_cont("|%s", ((m->status & MCI_STATUS_TCC) ? "TCC" : "-"));
|
|
}
|
|
|
|
/* do the two bits[14:13] together */
|
|
ecc = (m->status >> 45) & 0x3;
|
|
if (ecc)
|
|
pr_cont("|%sECC", ((ecc == 2) ? "C" : "U"));
|
|
|
|
pr_cont("]: 0x%016llx\n", m->status);
|
|
|
|
if (m->status & MCI_STATUS_ADDRV)
|
|
pr_emerg(HW_ERR "Error Addr: 0x%016llx\n", m->addr);
|
|
|
|
if (boot_cpu_has(X86_FEATURE_SMCA)) {
|
|
pr_emerg(HW_ERR "IPID: 0x%016llx", m->ipid);
|
|
|
|
if (m->status & MCI_STATUS_SYNDV)
|
|
pr_cont(", Syndrome: 0x%016llx", m->synd);
|
|
|
|
pr_cont("\n");
|
|
|
|
decode_smca_errors(m);
|
|
goto err_code;
|
|
}
|
|
|
|
if (m->tsc)
|
|
pr_emerg(HW_ERR "TSC: %llu\n", m->tsc);
|
|
|
|
if (!fam_ops)
|
|
goto err_code;
|
|
|
|
switch (m->bank) {
|
|
case 0:
|
|
decode_mc0_mce(m);
|
|
break;
|
|
|
|
case 1:
|
|
decode_mc1_mce(m);
|
|
break;
|
|
|
|
case 2:
|
|
decode_mc2_mce(m);
|
|
break;
|
|
|
|
case 3:
|
|
decode_mc3_mce(m);
|
|
break;
|
|
|
|
case 4:
|
|
decode_mc4_mce(m);
|
|
break;
|
|
|
|
case 5:
|
|
decode_mc5_mce(m);
|
|
break;
|
|
|
|
case 6:
|
|
decode_mc6_mce(m);
|
|
break;
|
|
|
|
default:
|
|
break;
|
|
}
|
|
|
|
err_code:
|
|
amd_decode_err_code(m->status & 0xffff);
|
|
|
|
return NOTIFY_STOP;
|
|
}
|
|
|
|
static struct notifier_block amd_mce_dec_nb = {
|
|
.notifier_call = amd_decode_mce,
|
|
.priority = MCE_PRIO_EDAC,
|
|
};
|
|
|
|
static int __init mce_amd_init(void)
|
|
{
|
|
struct cpuinfo_x86 *c = &boot_cpu_data;
|
|
|
|
if (c->x86_vendor != X86_VENDOR_AMD)
|
|
return -ENODEV;
|
|
|
|
fam_ops = kzalloc(sizeof(struct amd_decoder_ops), GFP_KERNEL);
|
|
if (!fam_ops)
|
|
return -ENOMEM;
|
|
|
|
switch (c->x86) {
|
|
case 0xf:
|
|
fam_ops->mc0_mce = k8_mc0_mce;
|
|
fam_ops->mc1_mce = k8_mc1_mce;
|
|
fam_ops->mc2_mce = k8_mc2_mce;
|
|
break;
|
|
|
|
case 0x10:
|
|
fam_ops->mc0_mce = f10h_mc0_mce;
|
|
fam_ops->mc1_mce = k8_mc1_mce;
|
|
fam_ops->mc2_mce = k8_mc2_mce;
|
|
break;
|
|
|
|
case 0x11:
|
|
fam_ops->mc0_mce = k8_mc0_mce;
|
|
fam_ops->mc1_mce = k8_mc1_mce;
|
|
fam_ops->mc2_mce = k8_mc2_mce;
|
|
break;
|
|
|
|
case 0x12:
|
|
fam_ops->mc0_mce = f12h_mc0_mce;
|
|
fam_ops->mc1_mce = k8_mc1_mce;
|
|
fam_ops->mc2_mce = k8_mc2_mce;
|
|
break;
|
|
|
|
case 0x14:
|
|
fam_ops->mc0_mce = cat_mc0_mce;
|
|
fam_ops->mc1_mce = cat_mc1_mce;
|
|
fam_ops->mc2_mce = k8_mc2_mce;
|
|
break;
|
|
|
|
case 0x15:
|
|
xec_mask = c->x86_model == 0x60 ? 0x3f : 0x1f;
|
|
|
|
fam_ops->mc0_mce = f15h_mc0_mce;
|
|
fam_ops->mc1_mce = f15h_mc1_mce;
|
|
fam_ops->mc2_mce = f15h_mc2_mce;
|
|
break;
|
|
|
|
case 0x16:
|
|
xec_mask = 0x1f;
|
|
fam_ops->mc0_mce = cat_mc0_mce;
|
|
fam_ops->mc1_mce = cat_mc1_mce;
|
|
fam_ops->mc2_mce = f16h_mc2_mce;
|
|
break;
|
|
|
|
case 0x17:
|
|
xec_mask = 0x3f;
|
|
if (!boot_cpu_has(X86_FEATURE_SMCA)) {
|
|
printk(KERN_WARNING "Decoding supported only on Scalable MCA processors.\n");
|
|
goto err_out;
|
|
}
|
|
break;
|
|
|
|
default:
|
|
printk(KERN_WARNING "Huh? What family is it: 0x%x?!\n", c->x86);
|
|
goto err_out;
|
|
}
|
|
|
|
pr_info("MCE: In-kernel MCE decoding enabled.\n");
|
|
|
|
mce_register_decode_chain(&amd_mce_dec_nb);
|
|
|
|
return 0;
|
|
|
|
err_out:
|
|
kfree(fam_ops);
|
|
fam_ops = NULL;
|
|
return -EINVAL;
|
|
}
|
|
early_initcall(mce_amd_init);
|
|
|
|
#ifdef MODULE
|
|
static void __exit mce_amd_exit(void)
|
|
{
|
|
mce_unregister_decode_chain(&amd_mce_dec_nb);
|
|
kfree(fam_ops);
|
|
}
|
|
|
|
MODULE_DESCRIPTION("AMD MCE decoder");
|
|
MODULE_ALIAS("edac-mce-amd");
|
|
MODULE_LICENSE("GPL");
|
|
module_exit(mce_amd_exit);
|
|
#endif
|