422 строки
10 KiB
C
422 строки
10 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (c) 2017 Pengutronix, Oleksij Rempel <kernel@pengutronix.de>
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*/
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#include <linux/clk.h>
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#include <linux/err.h>
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#include <linux/interrupt.h>
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#include <linux/kernel.h>
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#include <linux/mfd/syscon.h>
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#include <linux/module.h>
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#include <linux/of_address.h>
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#include <linux/of_device.h>
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#include <linux/platform_device.h>
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#include <linux/regmap.h>
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#include <linux/remoteproc.h>
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#define IMX7D_SRC_SCR 0x0C
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#define IMX7D_ENABLE_M4 BIT(3)
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#define IMX7D_SW_M4P_RST BIT(2)
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#define IMX7D_SW_M4C_RST BIT(1)
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#define IMX7D_SW_M4C_NON_SCLR_RST BIT(0)
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#define IMX7D_M4_RST_MASK (IMX7D_ENABLE_M4 | IMX7D_SW_M4P_RST \
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| IMX7D_SW_M4C_RST \
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| IMX7D_SW_M4C_NON_SCLR_RST)
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#define IMX7D_M4_START (IMX7D_ENABLE_M4 | IMX7D_SW_M4P_RST \
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| IMX7D_SW_M4C_RST)
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#define IMX7D_M4_STOP IMX7D_SW_M4C_NON_SCLR_RST
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/* Address: 0x020D8000 */
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#define IMX6SX_SRC_SCR 0x00
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#define IMX6SX_ENABLE_M4 BIT(22)
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#define IMX6SX_SW_M4P_RST BIT(12)
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#define IMX6SX_SW_M4C_NON_SCLR_RST BIT(4)
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#define IMX6SX_SW_M4C_RST BIT(3)
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#define IMX6SX_M4_START (IMX6SX_ENABLE_M4 | IMX6SX_SW_M4P_RST \
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| IMX6SX_SW_M4C_RST)
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#define IMX6SX_M4_STOP IMX6SX_SW_M4C_NON_SCLR_RST
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#define IMX6SX_M4_RST_MASK (IMX6SX_ENABLE_M4 | IMX6SX_SW_M4P_RST \
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| IMX6SX_SW_M4C_NON_SCLR_RST \
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| IMX6SX_SW_M4C_RST)
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#define IMX7D_RPROC_MEM_MAX 8
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/**
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* struct imx_rproc_mem - slim internal memory structure
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* @cpu_addr: MPU virtual address of the memory region
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* @sys_addr: Bus address used to access the memory region
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* @size: Size of the memory region
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*/
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struct imx_rproc_mem {
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void __iomem *cpu_addr;
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phys_addr_t sys_addr;
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size_t size;
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};
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/* att flags */
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/* M4 own area. Can be mapped at probe */
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#define ATT_OWN BIT(1)
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/* address translation table */
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struct imx_rproc_att {
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u32 da; /* device address (From Cortex M4 view)*/
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u32 sa; /* system bus address */
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u32 size; /* size of reg range */
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int flags;
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};
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struct imx_rproc_dcfg {
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u32 src_reg;
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u32 src_mask;
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u32 src_start;
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u32 src_stop;
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const struct imx_rproc_att *att;
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size_t att_size;
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};
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struct imx_rproc {
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struct device *dev;
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struct regmap *regmap;
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struct rproc *rproc;
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const struct imx_rproc_dcfg *dcfg;
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struct imx_rproc_mem mem[IMX7D_RPROC_MEM_MAX];
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struct clk *clk;
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};
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static const struct imx_rproc_att imx_rproc_att_imx7d[] = {
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/* dev addr , sys addr , size , flags */
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/* OCRAM_S (M4 Boot code) - alias */
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{ 0x00000000, 0x00180000, 0x00008000, 0 },
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/* OCRAM_S (Code) */
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{ 0x00180000, 0x00180000, 0x00008000, ATT_OWN },
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/* OCRAM (Code) - alias */
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{ 0x00900000, 0x00900000, 0x00020000, 0 },
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/* OCRAM_EPDC (Code) - alias */
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{ 0x00920000, 0x00920000, 0x00020000, 0 },
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/* OCRAM_PXP (Code) - alias */
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{ 0x00940000, 0x00940000, 0x00008000, 0 },
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/* TCML (Code) */
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{ 0x1FFF8000, 0x007F8000, 0x00008000, ATT_OWN },
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/* DDR (Code) - alias, first part of DDR (Data) */
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{ 0x10000000, 0x80000000, 0x0FFF0000, 0 },
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/* TCMU (Data) */
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{ 0x20000000, 0x00800000, 0x00008000, ATT_OWN },
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/* OCRAM (Data) */
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{ 0x20200000, 0x00900000, 0x00020000, 0 },
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/* OCRAM_EPDC (Data) */
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{ 0x20220000, 0x00920000, 0x00020000, 0 },
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/* OCRAM_PXP (Data) */
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{ 0x20240000, 0x00940000, 0x00008000, 0 },
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/* DDR (Data) */
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{ 0x80000000, 0x80000000, 0x60000000, 0 },
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};
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static const struct imx_rproc_att imx_rproc_att_imx6sx[] = {
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/* dev addr , sys addr , size , flags */
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/* TCML (M4 Boot Code) - alias */
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{ 0x00000000, 0x007F8000, 0x00008000, 0 },
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/* OCRAM_S (Code) */
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{ 0x00180000, 0x008F8000, 0x00004000, 0 },
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/* OCRAM_S (Code) - alias */
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{ 0x00180000, 0x008FC000, 0x00004000, 0 },
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/* TCML (Code) */
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{ 0x1FFF8000, 0x007F8000, 0x00008000, ATT_OWN },
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/* DDR (Code) - alias, first part of DDR (Data) */
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{ 0x10000000, 0x80000000, 0x0FFF8000, 0 },
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/* TCMU (Data) */
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{ 0x20000000, 0x00800000, 0x00008000, ATT_OWN },
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/* OCRAM_S (Data) - alias? */
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{ 0x208F8000, 0x008F8000, 0x00004000, 0 },
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/* DDR (Data) */
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{ 0x80000000, 0x80000000, 0x60000000, 0 },
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};
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static const struct imx_rproc_dcfg imx_rproc_cfg_imx7d = {
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.src_reg = IMX7D_SRC_SCR,
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.src_mask = IMX7D_M4_RST_MASK,
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.src_start = IMX7D_M4_START,
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.src_stop = IMX7D_M4_STOP,
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.att = imx_rproc_att_imx7d,
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.att_size = ARRAY_SIZE(imx_rproc_att_imx7d),
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};
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static const struct imx_rproc_dcfg imx_rproc_cfg_imx6sx = {
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.src_reg = IMX6SX_SRC_SCR,
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.src_mask = IMX6SX_M4_RST_MASK,
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.src_start = IMX6SX_M4_START,
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.src_stop = IMX6SX_M4_STOP,
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.att = imx_rproc_att_imx6sx,
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.att_size = ARRAY_SIZE(imx_rproc_att_imx6sx),
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};
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static int imx_rproc_start(struct rproc *rproc)
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{
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struct imx_rproc *priv = rproc->priv;
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const struct imx_rproc_dcfg *dcfg = priv->dcfg;
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struct device *dev = priv->dev;
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int ret;
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ret = regmap_update_bits(priv->regmap, dcfg->src_reg,
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dcfg->src_mask, dcfg->src_start);
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if (ret)
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dev_err(dev, "Failed to enable M4!\n");
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return ret;
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}
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static int imx_rproc_stop(struct rproc *rproc)
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{
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struct imx_rproc *priv = rproc->priv;
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const struct imx_rproc_dcfg *dcfg = priv->dcfg;
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struct device *dev = priv->dev;
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int ret;
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ret = regmap_update_bits(priv->regmap, dcfg->src_reg,
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dcfg->src_mask, dcfg->src_stop);
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if (ret)
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dev_err(dev, "Failed to stop M4!\n");
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return ret;
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}
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static int imx_rproc_da_to_sys(struct imx_rproc *priv, u64 da,
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int len, u64 *sys)
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{
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const struct imx_rproc_dcfg *dcfg = priv->dcfg;
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int i;
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/* parse address translation table */
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for (i = 0; i < dcfg->att_size; i++) {
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const struct imx_rproc_att *att = &dcfg->att[i];
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if (da >= att->da && da + len < att->da + att->size) {
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unsigned int offset = da - att->da;
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*sys = att->sa + offset;
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return 0;
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}
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}
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dev_warn(priv->dev, "Translation failed: da = 0x%llx len = 0x%x\n",
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da, len);
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return -ENOENT;
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}
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static void *imx_rproc_da_to_va(struct rproc *rproc, u64 da, int len)
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{
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struct imx_rproc *priv = rproc->priv;
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void *va = NULL;
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u64 sys;
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int i;
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if (len <= 0)
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return NULL;
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/*
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* On device side we have many aliases, so we need to convert device
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* address (M4) to system bus address first.
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*/
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if (imx_rproc_da_to_sys(priv, da, len, &sys))
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return NULL;
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for (i = 0; i < IMX7D_RPROC_MEM_MAX; i++) {
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if (sys >= priv->mem[i].sys_addr && sys + len <
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priv->mem[i].sys_addr + priv->mem[i].size) {
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unsigned int offset = sys - priv->mem[i].sys_addr;
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/* __force to make sparse happy with type conversion */
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va = (__force void *)(priv->mem[i].cpu_addr + offset);
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break;
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}
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}
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dev_dbg(&rproc->dev, "da = 0x%llx len = 0x%x va = 0x%p\n", da, len, va);
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return va;
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}
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static const struct rproc_ops imx_rproc_ops = {
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.start = imx_rproc_start,
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.stop = imx_rproc_stop,
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.da_to_va = imx_rproc_da_to_va,
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};
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static int imx_rproc_addr_init(struct imx_rproc *priv,
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struct platform_device *pdev)
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{
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const struct imx_rproc_dcfg *dcfg = priv->dcfg;
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struct device *dev = &pdev->dev;
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struct device_node *np = dev->of_node;
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int a, b = 0, err, nph;
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/* remap required addresses */
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for (a = 0; a < dcfg->att_size; a++) {
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const struct imx_rproc_att *att = &dcfg->att[a];
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if (!(att->flags & ATT_OWN))
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continue;
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if (b >= IMX7D_RPROC_MEM_MAX)
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break;
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priv->mem[b].cpu_addr = devm_ioremap(&pdev->dev,
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att->sa, att->size);
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if (!priv->mem[b].cpu_addr) {
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dev_err(dev, "devm_ioremap_resource failed\n");
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return -ENOMEM;
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}
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priv->mem[b].sys_addr = att->sa;
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priv->mem[b].size = att->size;
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b++;
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}
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/* memory-region is optional property */
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nph = of_count_phandle_with_args(np, "memory-region", NULL);
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if (nph <= 0)
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return 0;
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/* remap optional addresses */
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for (a = 0; a < nph; a++) {
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struct device_node *node;
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struct resource res;
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node = of_parse_phandle(np, "memory-region", a);
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err = of_address_to_resource(node, 0, &res);
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if (err) {
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dev_err(dev, "unable to resolve memory region\n");
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return err;
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}
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if (b >= IMX7D_RPROC_MEM_MAX)
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break;
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priv->mem[b].cpu_addr = devm_ioremap_resource(&pdev->dev, &res);
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if (IS_ERR(priv->mem[b].cpu_addr)) {
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dev_err(dev, "devm_ioremap_resource failed\n");
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err = PTR_ERR(priv->mem[b].cpu_addr);
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return err;
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}
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priv->mem[b].sys_addr = res.start;
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priv->mem[b].size = resource_size(&res);
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b++;
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}
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return 0;
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}
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static int imx_rproc_probe(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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struct device_node *np = dev->of_node;
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struct imx_rproc *priv;
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struct rproc *rproc;
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struct regmap_config config = { .name = "imx-rproc" };
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const struct imx_rproc_dcfg *dcfg;
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struct regmap *regmap;
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int ret;
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regmap = syscon_regmap_lookup_by_phandle(np, "syscon");
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if (IS_ERR(regmap)) {
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dev_err(dev, "failed to find syscon\n");
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return PTR_ERR(regmap);
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}
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regmap_attach_dev(dev, regmap, &config);
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/* set some other name then imx */
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rproc = rproc_alloc(dev, "imx-rproc", &imx_rproc_ops,
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NULL, sizeof(*priv));
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if (!rproc)
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return -ENOMEM;
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dcfg = of_device_get_match_data(dev);
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if (!dcfg) {
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ret = -EINVAL;
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goto err_put_rproc;
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}
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priv = rproc->priv;
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priv->rproc = rproc;
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priv->regmap = regmap;
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priv->dcfg = dcfg;
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priv->dev = dev;
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dev_set_drvdata(dev, rproc);
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ret = imx_rproc_addr_init(priv, pdev);
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if (ret) {
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dev_err(dev, "failed on imx_rproc_addr_init\n");
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goto err_put_rproc;
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}
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priv->clk = devm_clk_get(dev, NULL);
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if (IS_ERR(priv->clk)) {
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dev_err(dev, "Failed to get clock\n");
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ret = PTR_ERR(priv->clk);
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goto err_put_rproc;
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}
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/*
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* clk for M4 block including memory. Should be
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* enabled before .start for FW transfer.
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*/
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ret = clk_prepare_enable(priv->clk);
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if (ret) {
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dev_err(&rproc->dev, "Failed to enable clock\n");
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goto err_put_rproc;
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}
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ret = rproc_add(rproc);
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if (ret) {
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dev_err(dev, "rproc_add failed\n");
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goto err_put_clk;
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}
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return 0;
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err_put_clk:
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clk_disable_unprepare(priv->clk);
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err_put_rproc:
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rproc_free(rproc);
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return ret;
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}
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static int imx_rproc_remove(struct platform_device *pdev)
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{
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struct rproc *rproc = platform_get_drvdata(pdev);
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struct imx_rproc *priv = rproc->priv;
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clk_disable_unprepare(priv->clk);
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rproc_del(rproc);
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rproc_free(rproc);
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return 0;
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}
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static const struct of_device_id imx_rproc_of_match[] = {
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{ .compatible = "fsl,imx7d-cm4", .data = &imx_rproc_cfg_imx7d },
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{ .compatible = "fsl,imx6sx-cm4", .data = &imx_rproc_cfg_imx6sx },
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{},
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};
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MODULE_DEVICE_TABLE(of, imx_rproc_of_match);
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static struct platform_driver imx_rproc_driver = {
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.probe = imx_rproc_probe,
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.remove = imx_rproc_remove,
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.driver = {
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.name = "imx-rproc",
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.of_match_table = imx_rproc_of_match,
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},
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};
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module_platform_driver(imx_rproc_driver);
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MODULE_LICENSE("GPL v2");
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MODULE_DESCRIPTION("IMX6SX/7D remote processor control driver");
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MODULE_AUTHOR("Oleksij Rempel <o.rempel@pengutronix.de>");
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