692 строки
22 KiB
C
692 строки
22 KiB
C
/*
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* (C) COPYRIGHT 2016 ARM Limited. All rights reserved.
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* Author: Liviu Dudau <Liviu.Dudau@arm.com>
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*
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* This program is free software and is provided to you under the terms of the
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* GNU General Public License version 2 as published by the Free Software
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* Foundation, and any use by you of this program is subject to the terms
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* of such GNU licence.
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*
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* ARM Mali DP500/DP550/DP650 hardware manipulation routines. This is where
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* the difference between various versions of the hardware is being dealt with
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* in an attempt to provide to the rest of the driver code a unified view
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*/
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#include <linux/types.h>
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#include <linux/io.h>
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#include <drm/drmP.h>
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#include <video/videomode.h>
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#include <video/display_timing.h>
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#include "malidp_drv.h"
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#include "malidp_hw.h"
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static const struct malidp_input_format malidp500_de_formats[] = {
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/* fourcc, layers supporting the format, internal id */
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{ DRM_FORMAT_ARGB2101010, DE_VIDEO1 | DE_GRAPHICS1 | DE_GRAPHICS2, 0 },
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{ DRM_FORMAT_ABGR2101010, DE_VIDEO1 | DE_GRAPHICS1 | DE_GRAPHICS2, 1 },
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{ DRM_FORMAT_ARGB8888, DE_VIDEO1 | DE_GRAPHICS1 | DE_GRAPHICS2, 2 },
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{ DRM_FORMAT_ABGR8888, DE_VIDEO1 | DE_GRAPHICS1 | DE_GRAPHICS2, 3 },
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{ DRM_FORMAT_XRGB8888, DE_VIDEO1 | DE_GRAPHICS1 | DE_GRAPHICS2, 4 },
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{ DRM_FORMAT_XBGR8888, DE_VIDEO1 | DE_GRAPHICS1 | DE_GRAPHICS2, 5 },
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{ DRM_FORMAT_RGB888, DE_VIDEO1 | DE_GRAPHICS1 | DE_GRAPHICS2, 6 },
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{ DRM_FORMAT_BGR888, DE_VIDEO1 | DE_GRAPHICS1 | DE_GRAPHICS2, 7 },
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{ DRM_FORMAT_RGBA5551, DE_VIDEO1 | DE_GRAPHICS1 | DE_GRAPHICS2, 8 },
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{ DRM_FORMAT_ABGR1555, DE_VIDEO1 | DE_GRAPHICS1 | DE_GRAPHICS2, 9 },
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{ DRM_FORMAT_RGB565, DE_VIDEO1 | DE_GRAPHICS1 | DE_GRAPHICS2, 10 },
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{ DRM_FORMAT_BGR565, DE_VIDEO1 | DE_GRAPHICS1 | DE_GRAPHICS2, 11 },
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{ DRM_FORMAT_UYVY, DE_VIDEO1, 12 },
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{ DRM_FORMAT_YUYV, DE_VIDEO1, 13 },
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{ DRM_FORMAT_NV12, DE_VIDEO1, 14 },
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{ DRM_FORMAT_YUV420, DE_VIDEO1, 15 },
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};
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#define MALIDP_ID(__group, __format) \
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((((__group) & 0x7) << 3) | ((__format) & 0x7))
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#define MALIDP_COMMON_FORMATS \
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/* fourcc, layers supporting the format, internal id */ \
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{ DRM_FORMAT_ARGB2101010, DE_VIDEO1 | DE_GRAPHICS1 | DE_VIDEO2, MALIDP_ID(0, 0) }, \
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{ DRM_FORMAT_ABGR2101010, DE_VIDEO1 | DE_GRAPHICS1 | DE_VIDEO2, MALIDP_ID(0, 1) }, \
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{ DRM_FORMAT_RGBA1010102, DE_VIDEO1 | DE_GRAPHICS1 | DE_VIDEO2, MALIDP_ID(0, 2) }, \
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{ DRM_FORMAT_BGRA1010102, DE_VIDEO1 | DE_GRAPHICS1 | DE_VIDEO2, MALIDP_ID(0, 3) }, \
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{ DRM_FORMAT_ARGB8888, DE_VIDEO1 | DE_GRAPHICS1 | DE_VIDEO2 | DE_SMART, MALIDP_ID(1, 0) }, \
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{ DRM_FORMAT_ABGR8888, DE_VIDEO1 | DE_GRAPHICS1 | DE_VIDEO2 | DE_SMART, MALIDP_ID(1, 1) }, \
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{ DRM_FORMAT_RGBA8888, DE_VIDEO1 | DE_GRAPHICS1 | DE_VIDEO2 | DE_SMART, MALIDP_ID(1, 2) }, \
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{ DRM_FORMAT_BGRA8888, DE_VIDEO1 | DE_GRAPHICS1 | DE_VIDEO2 | DE_SMART, MALIDP_ID(1, 3) }, \
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{ DRM_FORMAT_XRGB8888, DE_VIDEO1 | DE_GRAPHICS1 | DE_VIDEO2 | DE_SMART, MALIDP_ID(2, 0) }, \
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{ DRM_FORMAT_XBGR8888, DE_VIDEO1 | DE_GRAPHICS1 | DE_VIDEO2 | DE_SMART, MALIDP_ID(2, 1) }, \
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{ DRM_FORMAT_RGBX8888, DE_VIDEO1 | DE_GRAPHICS1 | DE_VIDEO2 | DE_SMART, MALIDP_ID(2, 2) }, \
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{ DRM_FORMAT_BGRX8888, DE_VIDEO1 | DE_GRAPHICS1 | DE_VIDEO2 | DE_SMART, MALIDP_ID(2, 3) }, \
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{ DRM_FORMAT_RGB888, DE_VIDEO1 | DE_GRAPHICS1 | DE_VIDEO2, MALIDP_ID(3, 0) }, \
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{ DRM_FORMAT_BGR888, DE_VIDEO1 | DE_GRAPHICS1 | DE_VIDEO2, MALIDP_ID(3, 1) }, \
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{ DRM_FORMAT_RGBA5551, DE_VIDEO1 | DE_GRAPHICS1 | DE_VIDEO2, MALIDP_ID(4, 0) }, \
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{ DRM_FORMAT_ABGR1555, DE_VIDEO1 | DE_GRAPHICS1 | DE_VIDEO2, MALIDP_ID(4, 1) }, \
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{ DRM_FORMAT_RGB565, DE_VIDEO1 | DE_GRAPHICS1 | DE_VIDEO2, MALIDP_ID(4, 2) }, \
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{ DRM_FORMAT_BGR565, DE_VIDEO1 | DE_GRAPHICS1 | DE_VIDEO2, MALIDP_ID(4, 3) }, \
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{ DRM_FORMAT_YUYV, DE_VIDEO1 | DE_VIDEO2, MALIDP_ID(5, 2) }, \
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{ DRM_FORMAT_UYVY, DE_VIDEO1 | DE_VIDEO2, MALIDP_ID(5, 3) }, \
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{ DRM_FORMAT_NV12, DE_VIDEO1 | DE_VIDEO2, MALIDP_ID(5, 6) }, \
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{ DRM_FORMAT_YUV420, DE_VIDEO1 | DE_VIDEO2, MALIDP_ID(5, 7) }
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static const struct malidp_input_format malidp550_de_formats[] = {
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MALIDP_COMMON_FORMATS,
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};
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static const struct malidp_layer malidp500_layers[] = {
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{ DE_VIDEO1, MALIDP500_DE_LV_BASE, MALIDP500_DE_LV_PTR_BASE },
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{ DE_GRAPHICS1, MALIDP500_DE_LG1_BASE, MALIDP500_DE_LG1_PTR_BASE },
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{ DE_GRAPHICS2, MALIDP500_DE_LG2_BASE, MALIDP500_DE_LG2_PTR_BASE },
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};
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static const struct malidp_layer malidp550_layers[] = {
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{ DE_VIDEO1, MALIDP550_DE_LV1_BASE, MALIDP550_DE_LV1_PTR_BASE },
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{ DE_GRAPHICS1, MALIDP550_DE_LG_BASE, MALIDP550_DE_LG_PTR_BASE },
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{ DE_VIDEO2, MALIDP550_DE_LV2_BASE, MALIDP550_DE_LV2_PTR_BASE },
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{ DE_SMART, MALIDP550_DE_LS_BASE, MALIDP550_DE_LS_PTR_BASE },
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};
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#define MALIDP_DE_DEFAULT_PREFETCH_START 5
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static int malidp500_query_hw(struct malidp_hw_device *hwdev)
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{
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u32 conf = malidp_hw_read(hwdev, MALIDP500_CONFIG_ID);
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/* bit 4 of the CONFIG_ID register holds the line size multiplier */
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u8 ln_size_mult = conf & 0x10 ? 2 : 1;
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hwdev->min_line_size = 2;
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hwdev->max_line_size = SZ_2K * ln_size_mult;
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hwdev->rotation_memory[0] = SZ_1K * 64 * ln_size_mult;
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hwdev->rotation_memory[1] = 0; /* no second rotation memory bank */
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return 0;
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}
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static void malidp500_enter_config_mode(struct malidp_hw_device *hwdev)
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{
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u32 status, count = 100;
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malidp_hw_setbits(hwdev, MALIDP500_DC_CONFIG_REQ, MALIDP500_DC_CONTROL);
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while (count) {
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status = malidp_hw_read(hwdev, hwdev->map.dc_base + MALIDP_REG_STATUS);
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if ((status & MALIDP500_DC_CONFIG_REQ) == MALIDP500_DC_CONFIG_REQ)
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break;
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/*
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* entering config mode can take as long as the rendering
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* of a full frame, hence the long sleep here
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*/
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usleep_range(1000, 10000);
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count--;
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}
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WARN(count == 0, "timeout while entering config mode");
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}
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static void malidp500_leave_config_mode(struct malidp_hw_device *hwdev)
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{
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u32 status, count = 100;
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malidp_hw_clearbits(hwdev, MALIDP500_DC_CONFIG_REQ, MALIDP500_DC_CONTROL);
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while (count) {
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status = malidp_hw_read(hwdev, hwdev->map.dc_base + MALIDP_REG_STATUS);
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if ((status & MALIDP500_DC_CONFIG_REQ) == 0)
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break;
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usleep_range(100, 1000);
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count--;
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}
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WARN(count == 0, "timeout while leaving config mode");
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}
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static bool malidp500_in_config_mode(struct malidp_hw_device *hwdev)
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{
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u32 status;
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status = malidp_hw_read(hwdev, hwdev->map.dc_base + MALIDP_REG_STATUS);
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if ((status & MALIDP500_DC_CONFIG_REQ) == MALIDP500_DC_CONFIG_REQ)
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return true;
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return false;
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}
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static void malidp500_set_config_valid(struct malidp_hw_device *hwdev)
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{
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malidp_hw_setbits(hwdev, MALIDP_CFG_VALID, MALIDP500_CONFIG_VALID);
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}
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static void malidp500_modeset(struct malidp_hw_device *hwdev, struct videomode *mode)
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{
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u32 val = 0;
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malidp_hw_clearbits(hwdev, MALIDP500_DC_CLEAR_MASK, MALIDP500_DC_CONTROL);
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if (mode->flags & DISPLAY_FLAGS_HSYNC_HIGH)
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val |= MALIDP500_HSYNCPOL;
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if (mode->flags & DISPLAY_FLAGS_VSYNC_HIGH)
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val |= MALIDP500_VSYNCPOL;
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val |= MALIDP_DE_DEFAULT_PREFETCH_START;
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malidp_hw_setbits(hwdev, val, MALIDP500_DC_CONTROL);
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/*
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* Mali-DP500 encodes the background color like this:
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* - red @ MALIDP500_BGND_COLOR[12:0]
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* - green @ MALIDP500_BGND_COLOR[27:16]
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* - blue @ (MALIDP500_BGND_COLOR + 4)[12:0]
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*/
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val = ((MALIDP_BGND_COLOR_G & 0xfff) << 16) |
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(MALIDP_BGND_COLOR_R & 0xfff);
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malidp_hw_write(hwdev, val, MALIDP500_BGND_COLOR);
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malidp_hw_write(hwdev, MALIDP_BGND_COLOR_B, MALIDP500_BGND_COLOR + 4);
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val = MALIDP_DE_H_FRONTPORCH(mode->hfront_porch) |
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MALIDP_DE_H_BACKPORCH(mode->hback_porch);
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malidp_hw_write(hwdev, val, MALIDP500_TIMINGS_BASE + MALIDP_DE_H_TIMINGS);
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val = MALIDP500_DE_V_FRONTPORCH(mode->vfront_porch) |
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MALIDP_DE_V_BACKPORCH(mode->vback_porch);
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malidp_hw_write(hwdev, val, MALIDP500_TIMINGS_BASE + MALIDP_DE_V_TIMINGS);
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val = MALIDP_DE_H_SYNCWIDTH(mode->hsync_len) |
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MALIDP_DE_V_SYNCWIDTH(mode->vsync_len);
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malidp_hw_write(hwdev, val, MALIDP500_TIMINGS_BASE + MALIDP_DE_SYNC_WIDTH);
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val = MALIDP_DE_H_ACTIVE(mode->hactive) | MALIDP_DE_V_ACTIVE(mode->vactive);
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malidp_hw_write(hwdev, val, MALIDP500_TIMINGS_BASE + MALIDP_DE_HV_ACTIVE);
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if (mode->flags & DISPLAY_FLAGS_INTERLACED)
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malidp_hw_setbits(hwdev, MALIDP_DISP_FUNC_ILACED, MALIDP_DE_DISPLAY_FUNC);
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else
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malidp_hw_clearbits(hwdev, MALIDP_DISP_FUNC_ILACED, MALIDP_DE_DISPLAY_FUNC);
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}
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static int malidp500_rotmem_required(struct malidp_hw_device *hwdev, u16 w, u16 h, u32 fmt)
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{
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unsigned int depth;
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int bpp;
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/* RGB888 or BGR888 can't be rotated */
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if ((fmt == DRM_FORMAT_RGB888) || (fmt == DRM_FORMAT_BGR888))
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return -EINVAL;
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/*
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* Each layer needs enough rotation memory to fit 8 lines
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* worth of pixel data. Required size is then:
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* size = rotated_width * (bpp / 8) * 8;
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*/
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drm_fb_get_bpp_depth(fmt, &depth, &bpp);
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return w * bpp;
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}
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static int malidp550_query_hw(struct malidp_hw_device *hwdev)
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{
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u32 conf = malidp_hw_read(hwdev, MALIDP550_CONFIG_ID);
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u8 ln_size = (conf >> 4) & 0x3, rsize;
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hwdev->min_line_size = 2;
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switch (ln_size) {
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case 0:
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hwdev->max_line_size = SZ_2K;
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/* two banks of 64KB for rotation memory */
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rsize = 64;
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break;
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case 1:
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hwdev->max_line_size = SZ_4K;
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/* two banks of 128KB for rotation memory */
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rsize = 128;
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break;
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case 2:
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hwdev->max_line_size = 1280;
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/* two banks of 40KB for rotation memory */
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rsize = 40;
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break;
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case 3:
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/* reserved value */
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hwdev->max_line_size = 0;
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return -EINVAL;
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}
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hwdev->rotation_memory[0] = hwdev->rotation_memory[1] = rsize * SZ_1K;
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return 0;
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}
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static void malidp550_enter_config_mode(struct malidp_hw_device *hwdev)
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{
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u32 status, count = 100;
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malidp_hw_setbits(hwdev, MALIDP550_DC_CONFIG_REQ, MALIDP550_DC_CONTROL);
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while (count) {
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status = malidp_hw_read(hwdev, hwdev->map.dc_base + MALIDP_REG_STATUS);
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if ((status & MALIDP550_DC_CONFIG_REQ) == MALIDP550_DC_CONFIG_REQ)
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break;
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/*
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* entering config mode can take as long as the rendering
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* of a full frame, hence the long sleep here
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*/
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usleep_range(1000, 10000);
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count--;
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}
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WARN(count == 0, "timeout while entering config mode");
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}
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static void malidp550_leave_config_mode(struct malidp_hw_device *hwdev)
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{
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u32 status, count = 100;
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malidp_hw_clearbits(hwdev, MALIDP550_DC_CONFIG_REQ, MALIDP550_DC_CONTROL);
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while (count) {
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status = malidp_hw_read(hwdev, hwdev->map.dc_base + MALIDP_REG_STATUS);
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if ((status & MALIDP550_DC_CONFIG_REQ) == 0)
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break;
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usleep_range(100, 1000);
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count--;
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}
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WARN(count == 0, "timeout while leaving config mode");
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}
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static bool malidp550_in_config_mode(struct malidp_hw_device *hwdev)
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{
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u32 status;
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status = malidp_hw_read(hwdev, hwdev->map.dc_base + MALIDP_REG_STATUS);
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if ((status & MALIDP550_DC_CONFIG_REQ) == MALIDP550_DC_CONFIG_REQ)
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return true;
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return false;
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}
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static void malidp550_set_config_valid(struct malidp_hw_device *hwdev)
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{
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malidp_hw_setbits(hwdev, MALIDP_CFG_VALID, MALIDP550_CONFIG_VALID);
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}
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static void malidp550_modeset(struct malidp_hw_device *hwdev, struct videomode *mode)
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{
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u32 val = MALIDP_DE_DEFAULT_PREFETCH_START;
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malidp_hw_write(hwdev, val, MALIDP550_DE_CONTROL);
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/*
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* Mali-DP550 and Mali-DP650 encode the background color like this:
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* - red @ MALIDP550_DE_BGND_COLOR[23:16]
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* - green @ MALIDP550_DE_BGND_COLOR[15:8]
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* - blue @ MALIDP550_DE_BGND_COLOR[7:0]
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*
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* We need to truncate the least significant 4 bits from the default
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* MALIDP_BGND_COLOR_x values
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*/
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val = (((MALIDP_BGND_COLOR_R >> 4) & 0xff) << 16) |
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(((MALIDP_BGND_COLOR_G >> 4) & 0xff) << 8) |
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((MALIDP_BGND_COLOR_B >> 4) & 0xff);
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malidp_hw_write(hwdev, val, MALIDP550_DE_BGND_COLOR);
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val = MALIDP_DE_H_FRONTPORCH(mode->hfront_porch) |
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MALIDP_DE_H_BACKPORCH(mode->hback_porch);
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malidp_hw_write(hwdev, val, MALIDP550_TIMINGS_BASE + MALIDP_DE_H_TIMINGS);
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val = MALIDP550_DE_V_FRONTPORCH(mode->vfront_porch) |
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MALIDP_DE_V_BACKPORCH(mode->vback_porch);
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malidp_hw_write(hwdev, val, MALIDP550_TIMINGS_BASE + MALIDP_DE_V_TIMINGS);
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val = MALIDP_DE_H_SYNCWIDTH(mode->hsync_len) |
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MALIDP_DE_V_SYNCWIDTH(mode->vsync_len);
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if (mode->flags & DISPLAY_FLAGS_HSYNC_HIGH)
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val |= MALIDP550_HSYNCPOL;
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if (mode->flags & DISPLAY_FLAGS_VSYNC_HIGH)
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val |= MALIDP550_VSYNCPOL;
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malidp_hw_write(hwdev, val, MALIDP550_TIMINGS_BASE + MALIDP_DE_SYNC_WIDTH);
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val = MALIDP_DE_H_ACTIVE(mode->hactive) | MALIDP_DE_V_ACTIVE(mode->vactive);
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malidp_hw_write(hwdev, val, MALIDP550_TIMINGS_BASE + MALIDP_DE_HV_ACTIVE);
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if (mode->flags & DISPLAY_FLAGS_INTERLACED)
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malidp_hw_setbits(hwdev, MALIDP_DISP_FUNC_ILACED, MALIDP_DE_DISPLAY_FUNC);
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else
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malidp_hw_clearbits(hwdev, MALIDP_DISP_FUNC_ILACED, MALIDP_DE_DISPLAY_FUNC);
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}
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static int malidp550_rotmem_required(struct malidp_hw_device *hwdev, u16 w, u16 h, u32 fmt)
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{
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u32 bytes_per_col;
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/* raw RGB888 or BGR888 can't be rotated */
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if ((fmt == DRM_FORMAT_RGB888) || (fmt == DRM_FORMAT_BGR888))
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return -EINVAL;
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switch (fmt) {
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/* 8 lines at 4 bytes per pixel */
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case DRM_FORMAT_ARGB2101010:
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case DRM_FORMAT_ABGR2101010:
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case DRM_FORMAT_RGBA1010102:
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case DRM_FORMAT_BGRA1010102:
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case DRM_FORMAT_ARGB8888:
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case DRM_FORMAT_ABGR8888:
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case DRM_FORMAT_RGBA8888:
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case DRM_FORMAT_BGRA8888:
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case DRM_FORMAT_XRGB8888:
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case DRM_FORMAT_XBGR8888:
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case DRM_FORMAT_RGBX8888:
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case DRM_FORMAT_BGRX8888:
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case DRM_FORMAT_RGB888:
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case DRM_FORMAT_BGR888:
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/* 16 lines at 2 bytes per pixel */
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case DRM_FORMAT_RGBA5551:
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case DRM_FORMAT_ABGR1555:
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case DRM_FORMAT_RGB565:
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case DRM_FORMAT_BGR565:
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case DRM_FORMAT_UYVY:
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case DRM_FORMAT_YUYV:
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bytes_per_col = 32;
|
|
break;
|
|
/* 16 lines at 1.5 bytes per pixel */
|
|
case DRM_FORMAT_NV12:
|
|
case DRM_FORMAT_YUV420:
|
|
bytes_per_col = 24;
|
|
break;
|
|
default:
|
|
return -EINVAL;
|
|
}
|
|
|
|
return w * bytes_per_col;
|
|
}
|
|
|
|
static int malidp650_query_hw(struct malidp_hw_device *hwdev)
|
|
{
|
|
u32 conf = malidp_hw_read(hwdev, MALIDP550_CONFIG_ID);
|
|
u8 ln_size = (conf >> 4) & 0x3, rsize;
|
|
|
|
hwdev->min_line_size = 4;
|
|
|
|
switch (ln_size) {
|
|
case 0:
|
|
case 2:
|
|
/* reserved values */
|
|
hwdev->max_line_size = 0;
|
|
return -EINVAL;
|
|
case 1:
|
|
hwdev->max_line_size = SZ_4K;
|
|
/* two banks of 128KB for rotation memory */
|
|
rsize = 128;
|
|
break;
|
|
case 3:
|
|
hwdev->max_line_size = 2560;
|
|
/* two banks of 80KB for rotation memory */
|
|
rsize = 80;
|
|
}
|
|
|
|
hwdev->rotation_memory[0] = hwdev->rotation_memory[1] = rsize * SZ_1K;
|
|
return 0;
|
|
}
|
|
|
|
const struct malidp_hw_device malidp_device[MALIDP_MAX_DEVICES] = {
|
|
[MALIDP_500] = {
|
|
.map = {
|
|
.se_base = MALIDP500_SE_BASE,
|
|
.dc_base = MALIDP500_DC_BASE,
|
|
.out_depth_base = MALIDP500_OUTPUT_DEPTH,
|
|
.features = 0, /* no CLEARIRQ register */
|
|
.n_layers = ARRAY_SIZE(malidp500_layers),
|
|
.layers = malidp500_layers,
|
|
.de_irq_map = {
|
|
.irq_mask = MALIDP_DE_IRQ_UNDERRUN |
|
|
MALIDP500_DE_IRQ_AXI_ERR |
|
|
MALIDP500_DE_IRQ_VSYNC |
|
|
MALIDP500_DE_IRQ_GLOBAL,
|
|
.vsync_irq = MALIDP500_DE_IRQ_VSYNC,
|
|
},
|
|
.se_irq_map = {
|
|
.irq_mask = MALIDP500_SE_IRQ_CONF_MODE,
|
|
.vsync_irq = 0,
|
|
},
|
|
.dc_irq_map = {
|
|
.irq_mask = MALIDP500_DE_IRQ_CONF_VALID,
|
|
.vsync_irq = MALIDP500_DE_IRQ_CONF_VALID,
|
|
},
|
|
.input_formats = malidp500_de_formats,
|
|
.n_input_formats = ARRAY_SIZE(malidp500_de_formats),
|
|
},
|
|
.query_hw = malidp500_query_hw,
|
|
.enter_config_mode = malidp500_enter_config_mode,
|
|
.leave_config_mode = malidp500_leave_config_mode,
|
|
.in_config_mode = malidp500_in_config_mode,
|
|
.set_config_valid = malidp500_set_config_valid,
|
|
.modeset = malidp500_modeset,
|
|
.rotmem_required = malidp500_rotmem_required,
|
|
},
|
|
[MALIDP_550] = {
|
|
.map = {
|
|
.se_base = MALIDP550_SE_BASE,
|
|
.dc_base = MALIDP550_DC_BASE,
|
|
.out_depth_base = MALIDP550_DE_OUTPUT_DEPTH,
|
|
.features = MALIDP_REGMAP_HAS_CLEARIRQ,
|
|
.n_layers = ARRAY_SIZE(malidp550_layers),
|
|
.layers = malidp550_layers,
|
|
.de_irq_map = {
|
|
.irq_mask = MALIDP_DE_IRQ_UNDERRUN |
|
|
MALIDP550_DE_IRQ_VSYNC,
|
|
.vsync_irq = MALIDP550_DE_IRQ_VSYNC,
|
|
},
|
|
.se_irq_map = {
|
|
.irq_mask = MALIDP550_SE_IRQ_EOW |
|
|
MALIDP550_SE_IRQ_AXI_ERR,
|
|
},
|
|
.dc_irq_map = {
|
|
.irq_mask = MALIDP550_DC_IRQ_CONF_VALID,
|
|
.vsync_irq = MALIDP550_DC_IRQ_CONF_VALID,
|
|
},
|
|
.input_formats = malidp550_de_formats,
|
|
.n_input_formats = ARRAY_SIZE(malidp550_de_formats),
|
|
},
|
|
.query_hw = malidp550_query_hw,
|
|
.enter_config_mode = malidp550_enter_config_mode,
|
|
.leave_config_mode = malidp550_leave_config_mode,
|
|
.in_config_mode = malidp550_in_config_mode,
|
|
.set_config_valid = malidp550_set_config_valid,
|
|
.modeset = malidp550_modeset,
|
|
.rotmem_required = malidp550_rotmem_required,
|
|
},
|
|
[MALIDP_650] = {
|
|
.map = {
|
|
.se_base = MALIDP550_SE_BASE,
|
|
.dc_base = MALIDP550_DC_BASE,
|
|
.out_depth_base = MALIDP550_DE_OUTPUT_DEPTH,
|
|
.features = MALIDP_REGMAP_HAS_CLEARIRQ,
|
|
.n_layers = ARRAY_SIZE(malidp550_layers),
|
|
.layers = malidp550_layers,
|
|
.de_irq_map = {
|
|
.irq_mask = MALIDP_DE_IRQ_UNDERRUN |
|
|
MALIDP650_DE_IRQ_DRIFT |
|
|
MALIDP550_DE_IRQ_VSYNC,
|
|
.vsync_irq = MALIDP550_DE_IRQ_VSYNC,
|
|
},
|
|
.se_irq_map = {
|
|
.irq_mask = MALIDP550_SE_IRQ_EOW |
|
|
MALIDP550_SE_IRQ_AXI_ERR,
|
|
},
|
|
.dc_irq_map = {
|
|
.irq_mask = MALIDP550_DC_IRQ_CONF_VALID,
|
|
.vsync_irq = MALIDP550_DC_IRQ_CONF_VALID,
|
|
},
|
|
.input_formats = malidp550_de_formats,
|
|
.n_input_formats = ARRAY_SIZE(malidp550_de_formats),
|
|
},
|
|
.query_hw = malidp650_query_hw,
|
|
.enter_config_mode = malidp550_enter_config_mode,
|
|
.leave_config_mode = malidp550_leave_config_mode,
|
|
.in_config_mode = malidp550_in_config_mode,
|
|
.set_config_valid = malidp550_set_config_valid,
|
|
.modeset = malidp550_modeset,
|
|
.rotmem_required = malidp550_rotmem_required,
|
|
},
|
|
};
|
|
|
|
u8 malidp_hw_get_format_id(const struct malidp_hw_regmap *map,
|
|
u8 layer_id, u32 format)
|
|
{
|
|
unsigned int i;
|
|
|
|
for (i = 0; i < map->n_input_formats; i++) {
|
|
if (((map->input_formats[i].layer & layer_id) == layer_id) &&
|
|
(map->input_formats[i].format == format))
|
|
return map->input_formats[i].id;
|
|
}
|
|
|
|
return MALIDP_INVALID_FORMAT_ID;
|
|
}
|
|
|
|
static void malidp_hw_clear_irq(struct malidp_hw_device *hwdev, u8 block, u32 irq)
|
|
{
|
|
u32 base = malidp_get_block_base(hwdev, block);
|
|
|
|
if (hwdev->map.features & MALIDP_REGMAP_HAS_CLEARIRQ)
|
|
malidp_hw_write(hwdev, irq, base + MALIDP_REG_CLEARIRQ);
|
|
else
|
|
malidp_hw_write(hwdev, irq, base + MALIDP_REG_STATUS);
|
|
}
|
|
|
|
static irqreturn_t malidp_de_irq(int irq, void *arg)
|
|
{
|
|
struct drm_device *drm = arg;
|
|
struct malidp_drm *malidp = drm->dev_private;
|
|
struct malidp_hw_device *hwdev;
|
|
const struct malidp_irq_map *de;
|
|
u32 status, mask, dc_status;
|
|
irqreturn_t ret = IRQ_NONE;
|
|
|
|
if (!drm->dev_private)
|
|
return IRQ_HANDLED;
|
|
|
|
hwdev = malidp->dev;
|
|
de = &hwdev->map.de_irq_map;
|
|
|
|
/* first handle the config valid IRQ */
|
|
dc_status = malidp_hw_read(hwdev, hwdev->map.dc_base + MALIDP_REG_STATUS);
|
|
if (dc_status & hwdev->map.dc_irq_map.vsync_irq) {
|
|
/* we have a page flip event */
|
|
atomic_set(&malidp->config_valid, 1);
|
|
malidp_hw_clear_irq(hwdev, MALIDP_DC_BLOCK, dc_status);
|
|
ret = IRQ_WAKE_THREAD;
|
|
}
|
|
|
|
status = malidp_hw_read(hwdev, MALIDP_REG_STATUS);
|
|
if (!(status & de->irq_mask))
|
|
return ret;
|
|
|
|
mask = malidp_hw_read(hwdev, MALIDP_REG_MASKIRQ);
|
|
status &= mask;
|
|
if (status & de->vsync_irq)
|
|
drm_crtc_handle_vblank(&malidp->crtc);
|
|
|
|
malidp_hw_clear_irq(hwdev, MALIDP_DE_BLOCK, status);
|
|
|
|
return (ret == IRQ_NONE) ? IRQ_HANDLED : ret;
|
|
}
|
|
|
|
static irqreturn_t malidp_de_irq_thread_handler(int irq, void *arg)
|
|
{
|
|
struct drm_device *drm = arg;
|
|
struct malidp_drm *malidp = drm->dev_private;
|
|
|
|
wake_up(&malidp->wq);
|
|
|
|
return IRQ_HANDLED;
|
|
}
|
|
|
|
int malidp_de_irq_init(struct drm_device *drm, int irq)
|
|
{
|
|
struct malidp_drm *malidp = drm->dev_private;
|
|
struct malidp_hw_device *hwdev = malidp->dev;
|
|
int ret;
|
|
|
|
/* ensure interrupts are disabled */
|
|
malidp_hw_disable_irq(hwdev, MALIDP_DE_BLOCK, 0xffffffff);
|
|
malidp_hw_clear_irq(hwdev, MALIDP_DE_BLOCK, 0xffffffff);
|
|
malidp_hw_disable_irq(hwdev, MALIDP_DC_BLOCK, 0xffffffff);
|
|
malidp_hw_clear_irq(hwdev, MALIDP_DC_BLOCK, 0xffffffff);
|
|
|
|
ret = devm_request_threaded_irq(drm->dev, irq, malidp_de_irq,
|
|
malidp_de_irq_thread_handler,
|
|
IRQF_SHARED, "malidp-de", drm);
|
|
if (ret < 0) {
|
|
DRM_ERROR("failed to install DE IRQ handler\n");
|
|
return ret;
|
|
}
|
|
|
|
/* first enable the DC block IRQs */
|
|
malidp_hw_enable_irq(hwdev, MALIDP_DC_BLOCK,
|
|
hwdev->map.dc_irq_map.irq_mask);
|
|
|
|
/* now enable the DE block IRQs */
|
|
malidp_hw_enable_irq(hwdev, MALIDP_DE_BLOCK,
|
|
hwdev->map.de_irq_map.irq_mask);
|
|
|
|
return 0;
|
|
}
|
|
|
|
void malidp_de_irq_fini(struct drm_device *drm)
|
|
{
|
|
struct malidp_drm *malidp = drm->dev_private;
|
|
struct malidp_hw_device *hwdev = malidp->dev;
|
|
|
|
malidp_hw_disable_irq(hwdev, MALIDP_DE_BLOCK,
|
|
hwdev->map.de_irq_map.irq_mask);
|
|
malidp_hw_disable_irq(hwdev, MALIDP_DC_BLOCK,
|
|
hwdev->map.dc_irq_map.irq_mask);
|
|
}
|
|
|
|
static irqreturn_t malidp_se_irq(int irq, void *arg)
|
|
{
|
|
struct drm_device *drm = arg;
|
|
struct malidp_drm *malidp = drm->dev_private;
|
|
struct malidp_hw_device *hwdev = malidp->dev;
|
|
u32 status, mask;
|
|
|
|
status = malidp_hw_read(hwdev, hwdev->map.se_base + MALIDP_REG_STATUS);
|
|
if (!(status & hwdev->map.se_irq_map.irq_mask))
|
|
return IRQ_NONE;
|
|
|
|
mask = malidp_hw_read(hwdev, hwdev->map.se_base + MALIDP_REG_MASKIRQ);
|
|
status = malidp_hw_read(hwdev, hwdev->map.se_base + MALIDP_REG_STATUS);
|
|
status &= mask;
|
|
/* ToDo: status decoding and firing up of VSYNC and page flip events */
|
|
|
|
malidp_hw_clear_irq(hwdev, MALIDP_SE_BLOCK, status);
|
|
|
|
return IRQ_HANDLED;
|
|
}
|
|
|
|
static irqreturn_t malidp_se_irq_thread_handler(int irq, void *arg)
|
|
{
|
|
return IRQ_HANDLED;
|
|
}
|
|
|
|
int malidp_se_irq_init(struct drm_device *drm, int irq)
|
|
{
|
|
struct malidp_drm *malidp = drm->dev_private;
|
|
struct malidp_hw_device *hwdev = malidp->dev;
|
|
int ret;
|
|
|
|
/* ensure interrupts are disabled */
|
|
malidp_hw_disable_irq(hwdev, MALIDP_SE_BLOCK, 0xffffffff);
|
|
malidp_hw_clear_irq(hwdev, MALIDP_SE_BLOCK, 0xffffffff);
|
|
|
|
ret = devm_request_threaded_irq(drm->dev, irq, malidp_se_irq,
|
|
malidp_se_irq_thread_handler,
|
|
IRQF_SHARED, "malidp-se", drm);
|
|
if (ret < 0) {
|
|
DRM_ERROR("failed to install SE IRQ handler\n");
|
|
return ret;
|
|
}
|
|
|
|
malidp_hw_enable_irq(hwdev, MALIDP_SE_BLOCK,
|
|
hwdev->map.se_irq_map.irq_mask);
|
|
|
|
return 0;
|
|
}
|
|
|
|
void malidp_se_irq_fini(struct drm_device *drm)
|
|
{
|
|
struct malidp_drm *malidp = drm->dev_private;
|
|
struct malidp_hw_device *hwdev = malidp->dev;
|
|
|
|
malidp_hw_disable_irq(hwdev, MALIDP_SE_BLOCK,
|
|
hwdev->map.se_irq_map.irq_mask);
|
|
}
|