710 строки
18 KiB
C
710 строки
18 KiB
C
/* Various workarounds for chipset bugs.
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This code runs very early and can't use the regular PCI subsystem
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The entries are keyed to PCI bridges which usually identify chipsets
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uniquely.
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This is only for whole classes of chipsets with specific problems which
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need early invasive action (e.g. before the timers are initialized).
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Most PCI device specific workarounds can be done later and should be
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in standard PCI quirks
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Mainboard specific bugs should be handled by DMI entries.
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CPU specific bugs in setup.c */
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#include <linux/pci.h>
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#include <linux/acpi.h>
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#include <linux/pci_ids.h>
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#include <drm/i915_drm.h>
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#include <asm/pci-direct.h>
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#include <asm/dma.h>
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#include <asm/io_apic.h>
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#include <asm/apic.h>
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#include <asm/hpet.h>
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#include <asm/iommu.h>
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#include <asm/gart.h>
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#include <asm/irq_remapping.h>
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static void __init fix_hypertransport_config(int num, int slot, int func)
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{
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u32 htcfg;
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/*
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* we found a hypertransport bus
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* make sure that we are broadcasting
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* interrupts to all cpus on the ht bus
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* if we're using extended apic ids
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*/
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htcfg = read_pci_config(num, slot, func, 0x68);
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if (htcfg & (1 << 18)) {
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printk(KERN_INFO "Detected use of extended apic ids "
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"on hypertransport bus\n");
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if ((htcfg & (1 << 17)) == 0) {
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printk(KERN_INFO "Enabling hypertransport extended "
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"apic interrupt broadcast\n");
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printk(KERN_INFO "Note this is a bios bug, "
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"please contact your hw vendor\n");
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htcfg |= (1 << 17);
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write_pci_config(num, slot, func, 0x68, htcfg);
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}
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}
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}
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static void __init via_bugs(int num, int slot, int func)
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{
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#ifdef CONFIG_GART_IOMMU
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if ((max_pfn > MAX_DMA32_PFN || force_iommu) &&
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!gart_iommu_aperture_allowed) {
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printk(KERN_INFO
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"Looks like a VIA chipset. Disabling IOMMU."
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" Override with iommu=allowed\n");
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gart_iommu_aperture_disabled = 1;
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}
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#endif
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}
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#ifdef CONFIG_ACPI
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#ifdef CONFIG_X86_IO_APIC
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static int __init nvidia_hpet_check(struct acpi_table_header *header)
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{
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return 0;
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}
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#endif /* CONFIG_X86_IO_APIC */
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#endif /* CONFIG_ACPI */
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static void __init nvidia_bugs(int num, int slot, int func)
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{
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#ifdef CONFIG_ACPI
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#ifdef CONFIG_X86_IO_APIC
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/*
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* All timer overrides on Nvidia are
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* wrong unless HPET is enabled.
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* Unfortunately that's not true on many Asus boards.
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* We don't know yet how to detect this automatically, but
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* at least allow a command line override.
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*/
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if (acpi_use_timer_override)
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return;
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if (acpi_table_parse(ACPI_SIG_HPET, nvidia_hpet_check)) {
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acpi_skip_timer_override = 1;
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printk(KERN_INFO "Nvidia board "
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"detected. Ignoring ACPI "
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"timer override.\n");
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printk(KERN_INFO "If you got timer trouble "
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"try acpi_use_timer_override\n");
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}
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#endif
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#endif
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/* RED-PEN skip them on mptables too? */
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}
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#if defined(CONFIG_ACPI) && defined(CONFIG_X86_IO_APIC)
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static u32 __init ati_ixp4x0_rev(int num, int slot, int func)
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{
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u32 d;
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u8 b;
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b = read_pci_config_byte(num, slot, func, 0xac);
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b &= ~(1<<5);
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write_pci_config_byte(num, slot, func, 0xac, b);
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d = read_pci_config(num, slot, func, 0x70);
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d |= 1<<8;
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write_pci_config(num, slot, func, 0x70, d);
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d = read_pci_config(num, slot, func, 0x8);
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d &= 0xff;
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return d;
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}
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static void __init ati_bugs(int num, int slot, int func)
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{
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u32 d;
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u8 b;
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if (acpi_use_timer_override)
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return;
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d = ati_ixp4x0_rev(num, slot, func);
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if (d < 0x82)
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acpi_skip_timer_override = 1;
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else {
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/* check for IRQ0 interrupt swap */
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outb(0x72, 0xcd6); b = inb(0xcd7);
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if (!(b & 0x2))
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acpi_skip_timer_override = 1;
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}
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if (acpi_skip_timer_override) {
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printk(KERN_INFO "SB4X0 revision 0x%x\n", d);
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printk(KERN_INFO "Ignoring ACPI timer override.\n");
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printk(KERN_INFO "If you got timer trouble "
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"try acpi_use_timer_override\n");
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}
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}
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static u32 __init ati_sbx00_rev(int num, int slot, int func)
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{
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u32 d;
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d = read_pci_config(num, slot, func, 0x8);
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d &= 0xff;
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return d;
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}
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static void __init ati_bugs_contd(int num, int slot, int func)
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{
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u32 d, rev;
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rev = ati_sbx00_rev(num, slot, func);
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if (rev >= 0x40)
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acpi_fix_pin2_polarity = 1;
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/*
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* SB600: revisions 0x11, 0x12, 0x13, 0x14, ...
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* SB700: revisions 0x39, 0x3a, ...
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* SB800: revisions 0x40, 0x41, ...
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*/
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if (rev >= 0x39)
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return;
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if (acpi_use_timer_override)
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return;
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/* check for IRQ0 interrupt swap */
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d = read_pci_config(num, slot, func, 0x64);
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if (!(d & (1<<14)))
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acpi_skip_timer_override = 1;
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if (acpi_skip_timer_override) {
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printk(KERN_INFO "SB600 revision 0x%x\n", rev);
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printk(KERN_INFO "Ignoring ACPI timer override.\n");
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printk(KERN_INFO "If you got timer trouble "
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"try acpi_use_timer_override\n");
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}
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}
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#else
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static void __init ati_bugs(int num, int slot, int func)
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{
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}
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static void __init ati_bugs_contd(int num, int slot, int func)
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{
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}
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#endif
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static void __init intel_remapping_check(int num, int slot, int func)
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{
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u8 revision;
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u16 device;
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device = read_pci_config_16(num, slot, func, PCI_DEVICE_ID);
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revision = read_pci_config_byte(num, slot, func, PCI_REVISION_ID);
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/*
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* Revision <= 13 of all triggering devices id in this quirk
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* have a problem draining interrupts when irq remapping is
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* enabled, and should be flagged as broken. Additionally
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* revision 0x22 of device id 0x3405 has this problem.
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*/
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if (revision <= 0x13)
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set_irq_remapping_broken();
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else if (device == 0x3405 && revision == 0x22)
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set_irq_remapping_broken();
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}
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/*
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* Systems with Intel graphics controllers set aside memory exclusively
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* for gfx driver use. This memory is not marked in the E820 as reserved
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* or as RAM, and so is subject to overlap from E820 manipulation later
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* in the boot process. On some systems, MMIO space is allocated on top,
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* despite the efforts of the "RAM buffer" approach, which simply rounds
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* memory boundaries up to 64M to try to catch space that may decode
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* as RAM and so is not suitable for MMIO.
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*
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* And yes, so far on current devices the base addr is always under 4G.
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*/
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static u32 __init intel_stolen_base(int num, int slot, int func, size_t stolen_size)
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{
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u32 base;
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/*
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* For the PCI IDs in this quirk, the stolen base is always
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* in 0x5c, aka the BDSM register (yes that's really what
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* it's called).
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*/
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base = read_pci_config(num, slot, func, 0x5c);
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base &= ~((1<<20) - 1);
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return base;
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}
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#define KB(x) ((x) * 1024UL)
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#define MB(x) (KB (KB (x)))
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#define GB(x) (MB (KB (x)))
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static size_t __init i830_tseg_size(void)
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{
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u8 tmp = read_pci_config_byte(0, 0, 0, I830_ESMRAMC);
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if (!(tmp & TSEG_ENABLE))
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return 0;
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if (tmp & I830_TSEG_SIZE_1M)
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return MB(1);
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else
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return KB(512);
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}
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static size_t __init i845_tseg_size(void)
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{
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u8 tmp = read_pci_config_byte(0, 0, 0, I845_ESMRAMC);
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if (!(tmp & TSEG_ENABLE))
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return 0;
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switch (tmp & I845_TSEG_SIZE_MASK) {
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case I845_TSEG_SIZE_512K:
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return KB(512);
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case I845_TSEG_SIZE_1M:
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return MB(1);
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default:
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WARN_ON(1);
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return 0;
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}
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}
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static size_t __init i85x_tseg_size(void)
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{
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u8 tmp = read_pci_config_byte(0, 0, 0, I85X_ESMRAMC);
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if (!(tmp & TSEG_ENABLE))
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return 0;
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return MB(1);
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}
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static size_t __init i830_mem_size(void)
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{
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return read_pci_config_byte(0, 0, 0, I830_DRB3) * MB(32);
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}
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static size_t __init i85x_mem_size(void)
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{
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return read_pci_config_byte(0, 0, 1, I85X_DRB3) * MB(32);
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}
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/*
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* On 830/845/85x the stolen memory base isn't available in any
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* register. We need to calculate it as TOM-TSEG_SIZE-stolen_size.
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*/
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static u32 __init i830_stolen_base(int num, int slot, int func, size_t stolen_size)
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{
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return i830_mem_size() - i830_tseg_size() - stolen_size;
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}
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static u32 __init i845_stolen_base(int num, int slot, int func, size_t stolen_size)
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{
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return i830_mem_size() - i845_tseg_size() - stolen_size;
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}
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static u32 __init i85x_stolen_base(int num, int slot, int func, size_t stolen_size)
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{
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return i85x_mem_size() - i85x_tseg_size() - stolen_size;
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}
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static u32 __init i865_stolen_base(int num, int slot, int func, size_t stolen_size)
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{
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/*
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* FIXME is the graphics stolen memory region
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* always at TOUD? Ie. is it always the last
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* one to be allocated by the BIOS?
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*/
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return read_pci_config_16(0, 0, 0, I865_TOUD) << 16;
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}
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static size_t __init i830_stolen_size(int num, int slot, int func)
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{
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size_t stolen_size;
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u16 gmch_ctrl;
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gmch_ctrl = read_pci_config_16(0, 0, 0, I830_GMCH_CTRL);
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switch (gmch_ctrl & I830_GMCH_GMS_MASK) {
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case I830_GMCH_GMS_STOLEN_512:
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stolen_size = KB(512);
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break;
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case I830_GMCH_GMS_STOLEN_1024:
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stolen_size = MB(1);
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break;
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case I830_GMCH_GMS_STOLEN_8192:
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stolen_size = MB(8);
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break;
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case I830_GMCH_GMS_LOCAL:
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/* local memory isn't part of the normal address space */
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stolen_size = 0;
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break;
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default:
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return 0;
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}
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return stolen_size;
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}
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static size_t __init gen3_stolen_size(int num, int slot, int func)
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{
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size_t stolen_size;
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u16 gmch_ctrl;
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gmch_ctrl = read_pci_config_16(0, 0, 0, I830_GMCH_CTRL);
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switch (gmch_ctrl & I855_GMCH_GMS_MASK) {
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case I855_GMCH_GMS_STOLEN_1M:
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stolen_size = MB(1);
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break;
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case I855_GMCH_GMS_STOLEN_4M:
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stolen_size = MB(4);
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break;
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case I855_GMCH_GMS_STOLEN_8M:
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stolen_size = MB(8);
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break;
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case I855_GMCH_GMS_STOLEN_16M:
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stolen_size = MB(16);
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break;
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case I855_GMCH_GMS_STOLEN_32M:
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stolen_size = MB(32);
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break;
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case I915_GMCH_GMS_STOLEN_48M:
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stolen_size = MB(48);
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break;
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case I915_GMCH_GMS_STOLEN_64M:
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stolen_size = MB(64);
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break;
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case G33_GMCH_GMS_STOLEN_128M:
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stolen_size = MB(128);
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break;
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case G33_GMCH_GMS_STOLEN_256M:
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stolen_size = MB(256);
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break;
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case INTEL_GMCH_GMS_STOLEN_96M:
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stolen_size = MB(96);
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break;
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case INTEL_GMCH_GMS_STOLEN_160M:
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stolen_size = MB(160);
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break;
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case INTEL_GMCH_GMS_STOLEN_224M:
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stolen_size = MB(224);
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break;
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case INTEL_GMCH_GMS_STOLEN_352M:
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stolen_size = MB(352);
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break;
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default:
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stolen_size = 0;
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break;
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}
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return stolen_size;
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}
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static size_t __init gen6_stolen_size(int num, int slot, int func)
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{
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u16 gmch_ctrl;
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gmch_ctrl = read_pci_config_16(num, slot, func, SNB_GMCH_CTRL);
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gmch_ctrl >>= SNB_GMCH_GMS_SHIFT;
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gmch_ctrl &= SNB_GMCH_GMS_MASK;
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return gmch_ctrl << 25; /* 32 MB units */
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}
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static size_t __init gen8_stolen_size(int num, int slot, int func)
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{
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u16 gmch_ctrl;
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gmch_ctrl = read_pci_config_16(num, slot, func, SNB_GMCH_CTRL);
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gmch_ctrl >>= BDW_GMCH_GMS_SHIFT;
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gmch_ctrl &= BDW_GMCH_GMS_MASK;
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return gmch_ctrl << 25; /* 32 MB units */
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}
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static size_t __init chv_stolen_size(int num, int slot, int func)
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{
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u16 gmch_ctrl;
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gmch_ctrl = read_pci_config_16(num, slot, func, SNB_GMCH_CTRL);
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gmch_ctrl >>= SNB_GMCH_GMS_SHIFT;
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gmch_ctrl &= SNB_GMCH_GMS_MASK;
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/*
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* 0x0 to 0x10: 32MB increments starting at 0MB
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* 0x11 to 0x16: 4MB increments starting at 8MB
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* 0x17 to 0x1d: 4MB increments start at 36MB
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*/
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if (gmch_ctrl < 0x11)
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return gmch_ctrl << 25;
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else if (gmch_ctrl < 0x17)
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return (gmch_ctrl - 0x11 + 2) << 22;
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else
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return (gmch_ctrl - 0x17 + 9) << 22;
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}
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struct intel_stolen_funcs {
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size_t (*size)(int num, int slot, int func);
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u32 (*base)(int num, int slot, int func, size_t size);
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};
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static size_t __init gen9_stolen_size(int num, int slot, int func)
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{
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u16 gmch_ctrl;
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gmch_ctrl = read_pci_config_16(num, slot, func, SNB_GMCH_CTRL);
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gmch_ctrl >>= BDW_GMCH_GMS_SHIFT;
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gmch_ctrl &= BDW_GMCH_GMS_MASK;
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if (gmch_ctrl < 0xf0)
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return gmch_ctrl << 25; /* 32 MB units */
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else
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/* 4MB increments starting at 0xf0 for 4MB */
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return (gmch_ctrl - 0xf0 + 1) << 22;
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}
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typedef size_t (*stolen_size_fn)(int num, int slot, int func);
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static const struct intel_stolen_funcs i830_stolen_funcs __initconst = {
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.base = i830_stolen_base,
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.size = i830_stolen_size,
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};
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static const struct intel_stolen_funcs i845_stolen_funcs __initconst = {
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.base = i845_stolen_base,
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.size = i830_stolen_size,
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};
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static const struct intel_stolen_funcs i85x_stolen_funcs __initconst = {
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.base = i85x_stolen_base,
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.size = gen3_stolen_size,
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};
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static const struct intel_stolen_funcs i865_stolen_funcs __initconst = {
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.base = i865_stolen_base,
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.size = gen3_stolen_size,
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};
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static const struct intel_stolen_funcs gen3_stolen_funcs __initconst = {
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.base = intel_stolen_base,
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.size = gen3_stolen_size,
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};
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static const struct intel_stolen_funcs gen6_stolen_funcs __initconst = {
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.base = intel_stolen_base,
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.size = gen6_stolen_size,
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};
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static const struct intel_stolen_funcs gen8_stolen_funcs __initconst = {
|
|
.base = intel_stolen_base,
|
|
.size = gen8_stolen_size,
|
|
};
|
|
|
|
static const struct intel_stolen_funcs gen9_stolen_funcs __initconst = {
|
|
.base = intel_stolen_base,
|
|
.size = gen9_stolen_size,
|
|
};
|
|
|
|
static const struct intel_stolen_funcs chv_stolen_funcs __initconst = {
|
|
.base = intel_stolen_base,
|
|
.size = chv_stolen_size,
|
|
};
|
|
|
|
static const struct pci_device_id intel_stolen_ids[] __initconst = {
|
|
INTEL_I830_IDS(&i830_stolen_funcs),
|
|
INTEL_I845G_IDS(&i845_stolen_funcs),
|
|
INTEL_I85X_IDS(&i85x_stolen_funcs),
|
|
INTEL_I865G_IDS(&i865_stolen_funcs),
|
|
INTEL_I915G_IDS(&gen3_stolen_funcs),
|
|
INTEL_I915GM_IDS(&gen3_stolen_funcs),
|
|
INTEL_I945G_IDS(&gen3_stolen_funcs),
|
|
INTEL_I945GM_IDS(&gen3_stolen_funcs),
|
|
INTEL_VLV_M_IDS(&gen6_stolen_funcs),
|
|
INTEL_VLV_D_IDS(&gen6_stolen_funcs),
|
|
INTEL_PINEVIEW_IDS(&gen3_stolen_funcs),
|
|
INTEL_I965G_IDS(&gen3_stolen_funcs),
|
|
INTEL_G33_IDS(&gen3_stolen_funcs),
|
|
INTEL_I965GM_IDS(&gen3_stolen_funcs),
|
|
INTEL_GM45_IDS(&gen3_stolen_funcs),
|
|
INTEL_G45_IDS(&gen3_stolen_funcs),
|
|
INTEL_IRONLAKE_D_IDS(&gen3_stolen_funcs),
|
|
INTEL_IRONLAKE_M_IDS(&gen3_stolen_funcs),
|
|
INTEL_SNB_D_IDS(&gen6_stolen_funcs),
|
|
INTEL_SNB_M_IDS(&gen6_stolen_funcs),
|
|
INTEL_IVB_M_IDS(&gen6_stolen_funcs),
|
|
INTEL_IVB_D_IDS(&gen6_stolen_funcs),
|
|
INTEL_HSW_D_IDS(&gen6_stolen_funcs),
|
|
INTEL_HSW_M_IDS(&gen6_stolen_funcs),
|
|
INTEL_BDW_M_IDS(&gen8_stolen_funcs),
|
|
INTEL_BDW_D_IDS(&gen8_stolen_funcs),
|
|
INTEL_CHV_IDS(&chv_stolen_funcs),
|
|
INTEL_SKL_IDS(&gen9_stolen_funcs),
|
|
INTEL_BXT_IDS(&gen9_stolen_funcs),
|
|
INTEL_KBL_IDS(&gen9_stolen_funcs),
|
|
};
|
|
|
|
static void __init intel_graphics_stolen(int num, int slot, int func)
|
|
{
|
|
size_t size;
|
|
int i;
|
|
u32 start;
|
|
u16 device, subvendor, subdevice;
|
|
|
|
device = read_pci_config_16(num, slot, func, PCI_DEVICE_ID);
|
|
subvendor = read_pci_config_16(num, slot, func,
|
|
PCI_SUBSYSTEM_VENDOR_ID);
|
|
subdevice = read_pci_config_16(num, slot, func, PCI_SUBSYSTEM_ID);
|
|
|
|
for (i = 0; i < ARRAY_SIZE(intel_stolen_ids); i++) {
|
|
if (intel_stolen_ids[i].device == device) {
|
|
const struct intel_stolen_funcs *stolen_funcs =
|
|
(const struct intel_stolen_funcs *)intel_stolen_ids[i].driver_data;
|
|
size = stolen_funcs->size(num, slot, func);
|
|
start = stolen_funcs->base(num, slot, func, size);
|
|
if (size && start) {
|
|
printk(KERN_INFO "Reserving Intel graphics stolen memory at 0x%x-0x%x\n",
|
|
start, start + (u32)size - 1);
|
|
/* Mark this space as reserved */
|
|
e820_add_region(start, size, E820_RESERVED);
|
|
sanitize_e820_map(e820.map,
|
|
ARRAY_SIZE(e820.map),
|
|
&e820.nr_map);
|
|
}
|
|
return;
|
|
}
|
|
}
|
|
}
|
|
|
|
static void __init force_disable_hpet(int num, int slot, int func)
|
|
{
|
|
#ifdef CONFIG_HPET_TIMER
|
|
boot_hpet_disable = true;
|
|
pr_info("x86/hpet: Will disable the HPET for this platform because it's not reliable\n");
|
|
#endif
|
|
}
|
|
|
|
|
|
#define QFLAG_APPLY_ONCE 0x1
|
|
#define QFLAG_APPLIED 0x2
|
|
#define QFLAG_DONE (QFLAG_APPLY_ONCE|QFLAG_APPLIED)
|
|
struct chipset {
|
|
u32 vendor;
|
|
u32 device;
|
|
u32 class;
|
|
u32 class_mask;
|
|
u32 flags;
|
|
void (*f)(int num, int slot, int func);
|
|
};
|
|
|
|
/*
|
|
* Only works for devices on the root bus. If you add any devices
|
|
* not on bus 0 readd another loop level in early_quirks(). But
|
|
* be careful because at least the Nvidia quirk here relies on
|
|
* only matching on bus 0.
|
|
*/
|
|
static struct chipset early_qrk[] __initdata = {
|
|
{ PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID,
|
|
PCI_CLASS_BRIDGE_PCI, PCI_ANY_ID, QFLAG_APPLY_ONCE, nvidia_bugs },
|
|
{ PCI_VENDOR_ID_VIA, PCI_ANY_ID,
|
|
PCI_CLASS_BRIDGE_PCI, PCI_ANY_ID, QFLAG_APPLY_ONCE, via_bugs },
|
|
{ PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_K8_NB,
|
|
PCI_CLASS_BRIDGE_HOST, PCI_ANY_ID, 0, fix_hypertransport_config },
|
|
{ PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP400_SMBUS,
|
|
PCI_CLASS_SERIAL_SMBUS, PCI_ANY_ID, 0, ati_bugs },
|
|
{ PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_SBX00_SMBUS,
|
|
PCI_CLASS_SERIAL_SMBUS, PCI_ANY_ID, 0, ati_bugs_contd },
|
|
{ PCI_VENDOR_ID_INTEL, 0x3403, PCI_CLASS_BRIDGE_HOST,
|
|
PCI_BASE_CLASS_BRIDGE, 0, intel_remapping_check },
|
|
{ PCI_VENDOR_ID_INTEL, 0x3405, PCI_CLASS_BRIDGE_HOST,
|
|
PCI_BASE_CLASS_BRIDGE, 0, intel_remapping_check },
|
|
{ PCI_VENDOR_ID_INTEL, 0x3406, PCI_CLASS_BRIDGE_HOST,
|
|
PCI_BASE_CLASS_BRIDGE, 0, intel_remapping_check },
|
|
{ PCI_VENDOR_ID_INTEL, PCI_ANY_ID, PCI_CLASS_DISPLAY_VGA, PCI_ANY_ID,
|
|
QFLAG_APPLY_ONCE, intel_graphics_stolen },
|
|
/*
|
|
* HPET on the current version of the Baytrail platform has accuracy
|
|
* problems: it will halt in deep idle state - so we disable it.
|
|
*
|
|
* More details can be found in section 18.10.1.3 of the datasheet:
|
|
*
|
|
* http://www.intel.com/content/dam/www/public/us/en/documents/datasheets/atom-z8000-datasheet-vol-1.pdf
|
|
*/
|
|
{ PCI_VENDOR_ID_INTEL, 0x0f00,
|
|
PCI_CLASS_BRIDGE_HOST, PCI_ANY_ID, 0, force_disable_hpet},
|
|
{}
|
|
};
|
|
|
|
/**
|
|
* check_dev_quirk - apply early quirks to a given PCI device
|
|
* @num: bus number
|
|
* @slot: slot number
|
|
* @func: PCI function
|
|
*
|
|
* Check the vendor & device ID against the early quirks table.
|
|
*
|
|
* If the device is single function, let early_quirks() know so we don't
|
|
* poke at this device again.
|
|
*/
|
|
static int __init check_dev_quirk(int num, int slot, int func)
|
|
{
|
|
u16 class;
|
|
u16 vendor;
|
|
u16 device;
|
|
u8 type;
|
|
int i;
|
|
|
|
class = read_pci_config_16(num, slot, func, PCI_CLASS_DEVICE);
|
|
|
|
if (class == 0xffff)
|
|
return -1; /* no class, treat as single function */
|
|
|
|
vendor = read_pci_config_16(num, slot, func, PCI_VENDOR_ID);
|
|
|
|
device = read_pci_config_16(num, slot, func, PCI_DEVICE_ID);
|
|
|
|
for (i = 0; early_qrk[i].f != NULL; i++) {
|
|
if (((early_qrk[i].vendor == PCI_ANY_ID) ||
|
|
(early_qrk[i].vendor == vendor)) &&
|
|
((early_qrk[i].device == PCI_ANY_ID) ||
|
|
(early_qrk[i].device == device)) &&
|
|
(!((early_qrk[i].class ^ class) &
|
|
early_qrk[i].class_mask))) {
|
|
if ((early_qrk[i].flags &
|
|
QFLAG_DONE) != QFLAG_DONE)
|
|
early_qrk[i].f(num, slot, func);
|
|
early_qrk[i].flags |= QFLAG_APPLIED;
|
|
}
|
|
}
|
|
|
|
type = read_pci_config_byte(num, slot, func,
|
|
PCI_HEADER_TYPE);
|
|
if (!(type & 0x80))
|
|
return -1;
|
|
|
|
return 0;
|
|
}
|
|
|
|
void __init early_quirks(void)
|
|
{
|
|
int slot, func;
|
|
|
|
if (!early_pci_allowed())
|
|
return;
|
|
|
|
/* Poor man's PCI discovery */
|
|
/* Only scan the root bus */
|
|
for (slot = 0; slot < 32; slot++)
|
|
for (func = 0; func < 8; func++) {
|
|
/* Only probe function 0 on single fn devices */
|
|
if (check_dev_quirk(0, slot, func))
|
|
break;
|
|
}
|
|
}
|