391 строка
10 KiB
C
391 строка
10 KiB
C
/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 2003 Atheros Communications, Inc., All Rights Reserved.
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* Copyright (C) 2006 FON Technology, SL.
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* Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
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* Copyright (C) 2006-2009 Felix Fietkau <nbd@openwrt.org>
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* Copyright (C) 2012 Alexandros C. Couloumbis <alex@ozo.com>
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*/
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/*
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* Platform devices for Atheros AR5312 SoCs
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*/
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#include <linux/init.h>
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#include <linux/kernel.h>
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#include <linux/bitops.h>
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#include <linux/irqdomain.h>
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#include <linux/interrupt.h>
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#include <linux/memblock.h>
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#include <linux/platform_device.h>
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#include <linux/mtd/physmap.h>
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#include <linux/reboot.h>
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#include <asm/bootinfo.h>
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#include <asm/reboot.h>
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#include <asm/time.h>
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#include <ath25_platform.h>
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#include "devices.h"
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#include "ar5312.h"
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#include "ar5312_regs.h"
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static void __iomem *ar5312_rst_base;
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static struct irq_domain *ar5312_misc_irq_domain;
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static inline u32 ar5312_rst_reg_read(u32 reg)
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{
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return __raw_readl(ar5312_rst_base + reg);
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}
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static inline void ar5312_rst_reg_write(u32 reg, u32 val)
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{
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__raw_writel(val, ar5312_rst_base + reg);
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}
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static inline void ar5312_rst_reg_mask(u32 reg, u32 mask, u32 val)
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{
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u32 ret = ar5312_rst_reg_read(reg);
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ret &= ~mask;
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ret |= val;
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ar5312_rst_reg_write(reg, ret);
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}
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static irqreturn_t ar5312_ahb_err_handler(int cpl, void *dev_id)
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{
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u32 proc1 = ar5312_rst_reg_read(AR5312_PROC1);
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u32 proc_addr = ar5312_rst_reg_read(AR5312_PROCADDR); /* clears error */
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u32 dma1 = ar5312_rst_reg_read(AR5312_DMA1);
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u32 dma_addr = ar5312_rst_reg_read(AR5312_DMAADDR); /* clears error */
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pr_emerg("AHB interrupt: PROCADDR=0x%8.8x PROC1=0x%8.8x DMAADDR=0x%8.8x DMA1=0x%8.8x\n",
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proc_addr, proc1, dma_addr, dma1);
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machine_restart("AHB error"); /* Catastrophic failure */
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return IRQ_HANDLED;
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}
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static void ar5312_misc_irq_handler(struct irq_desc *desc)
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{
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u32 pending = ar5312_rst_reg_read(AR5312_ISR) &
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ar5312_rst_reg_read(AR5312_IMR);
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unsigned nr;
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int ret = 0;
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if (pending) {
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struct irq_domain *domain = irq_desc_get_handler_data(desc);
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nr = __ffs(pending);
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ret = generic_handle_domain_irq(domain, nr);
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if (nr == AR5312_MISC_IRQ_TIMER)
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ar5312_rst_reg_read(AR5312_TIMER);
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}
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if (!pending || ret)
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spurious_interrupt();
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}
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/* Enable the specified AR5312_MISC_IRQ interrupt */
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static void ar5312_misc_irq_unmask(struct irq_data *d)
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{
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ar5312_rst_reg_mask(AR5312_IMR, 0, BIT(d->hwirq));
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}
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/* Disable the specified AR5312_MISC_IRQ interrupt */
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static void ar5312_misc_irq_mask(struct irq_data *d)
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{
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ar5312_rst_reg_mask(AR5312_IMR, BIT(d->hwirq), 0);
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ar5312_rst_reg_read(AR5312_IMR); /* flush write buffer */
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}
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static struct irq_chip ar5312_misc_irq_chip = {
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.name = "ar5312-misc",
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.irq_unmask = ar5312_misc_irq_unmask,
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.irq_mask = ar5312_misc_irq_mask,
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};
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static int ar5312_misc_irq_map(struct irq_domain *d, unsigned irq,
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irq_hw_number_t hw)
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{
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irq_set_chip_and_handler(irq, &ar5312_misc_irq_chip, handle_level_irq);
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return 0;
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}
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static const struct irq_domain_ops ar5312_misc_irq_domain_ops = {
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.map = ar5312_misc_irq_map,
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};
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static void ar5312_irq_dispatch(void)
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{
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u32 pending = read_c0_status() & read_c0_cause();
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if (pending & CAUSEF_IP2)
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do_IRQ(AR5312_IRQ_WLAN0);
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else if (pending & CAUSEF_IP5)
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do_IRQ(AR5312_IRQ_WLAN1);
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else if (pending & CAUSEF_IP6)
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do_IRQ(AR5312_IRQ_MISC);
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else if (pending & CAUSEF_IP7)
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do_IRQ(ATH25_IRQ_CPU_CLOCK);
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else
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spurious_interrupt();
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}
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void __init ar5312_arch_init_irq(void)
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{
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struct irq_domain *domain;
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unsigned irq;
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ath25_irq_dispatch = ar5312_irq_dispatch;
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domain = irq_domain_add_linear(NULL, AR5312_MISC_IRQ_COUNT,
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&ar5312_misc_irq_domain_ops, NULL);
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if (!domain)
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panic("Failed to add IRQ domain");
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irq = irq_create_mapping(domain, AR5312_MISC_IRQ_AHB_PROC);
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if (request_irq(irq, ar5312_ahb_err_handler, 0, "ar5312-ahb-error",
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NULL))
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pr_err("Failed to register ar5312-ahb-error interrupt\n");
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irq_set_chained_handler_and_data(AR5312_IRQ_MISC,
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ar5312_misc_irq_handler, domain);
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ar5312_misc_irq_domain = domain;
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}
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static struct physmap_flash_data ar5312_flash_data = {
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.width = 2,
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};
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static struct resource ar5312_flash_resource = {
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.start = AR5312_FLASH_BASE,
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.end = AR5312_FLASH_BASE + AR5312_FLASH_SIZE - 1,
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.flags = IORESOURCE_MEM,
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};
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static struct platform_device ar5312_physmap_flash = {
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.name = "physmap-flash",
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.id = 0,
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.dev.platform_data = &ar5312_flash_data,
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.resource = &ar5312_flash_resource,
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.num_resources = 1,
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};
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static void __init ar5312_flash_init(void)
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{
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void __iomem *flashctl_base;
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u32 ctl;
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flashctl_base = ioremap(AR5312_FLASHCTL_BASE,
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AR5312_FLASHCTL_SIZE);
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ctl = __raw_readl(flashctl_base + AR5312_FLASHCTL0);
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ctl &= AR5312_FLASHCTL_MW;
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/* fixup flash width */
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switch (ctl) {
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case AR5312_FLASHCTL_MW16:
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ar5312_flash_data.width = 2;
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break;
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case AR5312_FLASHCTL_MW8:
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default:
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ar5312_flash_data.width = 1;
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break;
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}
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/*
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* Configure flash bank 0.
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* Assume 8M window size. Flash will be aliased if it's smaller
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*/
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ctl |= AR5312_FLASHCTL_E | AR5312_FLASHCTL_AC_8M | AR5312_FLASHCTL_RBLE;
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ctl |= 0x01 << AR5312_FLASHCTL_IDCY_S;
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ctl |= 0x07 << AR5312_FLASHCTL_WST1_S;
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ctl |= 0x07 << AR5312_FLASHCTL_WST2_S;
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__raw_writel(ctl, flashctl_base + AR5312_FLASHCTL0);
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/* Disable other flash banks */
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ctl = __raw_readl(flashctl_base + AR5312_FLASHCTL1);
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ctl &= ~(AR5312_FLASHCTL_E | AR5312_FLASHCTL_AC);
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__raw_writel(ctl, flashctl_base + AR5312_FLASHCTL1);
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ctl = __raw_readl(flashctl_base + AR5312_FLASHCTL2);
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ctl &= ~(AR5312_FLASHCTL_E | AR5312_FLASHCTL_AC);
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__raw_writel(ctl, flashctl_base + AR5312_FLASHCTL2);
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iounmap(flashctl_base);
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}
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void __init ar5312_init_devices(void)
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{
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struct ath25_boarddata *config;
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ar5312_flash_init();
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/* Locate board/radio config data */
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ath25_find_config(AR5312_FLASH_BASE, AR5312_FLASH_SIZE);
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config = ath25_board.config;
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/* AR2313 has CPU minor rev. 10 */
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if ((current_cpu_data.processor_id & 0xff) == 0x0a)
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ath25_soc = ATH25_SOC_AR2313;
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/* AR2312 shares the same Silicon ID as AR5312 */
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else if (config->flags & BD_ISCASPER)
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ath25_soc = ATH25_SOC_AR2312;
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/* Everything else is probably AR5312 or compatible */
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else
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ath25_soc = ATH25_SOC_AR5312;
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platform_device_register(&ar5312_physmap_flash);
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switch (ath25_soc) {
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case ATH25_SOC_AR5312:
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if (!ath25_board.radio)
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return;
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if (!(config->flags & BD_WLAN0))
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break;
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ath25_add_wmac(0, AR5312_WLAN0_BASE, AR5312_IRQ_WLAN0);
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break;
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case ATH25_SOC_AR2312:
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case ATH25_SOC_AR2313:
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if (!ath25_board.radio)
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return;
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break;
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default:
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break;
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}
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if (config->flags & BD_WLAN1)
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ath25_add_wmac(1, AR5312_WLAN1_BASE, AR5312_IRQ_WLAN1);
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}
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static void ar5312_restart(char *command)
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{
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/* reset the system */
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local_irq_disable();
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while (1)
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ar5312_rst_reg_write(AR5312_RESET, AR5312_RESET_SYSTEM);
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}
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/*
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* This table is indexed by bits 5..4 of the CLOCKCTL1 register
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* to determine the predevisor value.
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*/
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static unsigned clockctl1_predivide_table[4] __initdata = { 1, 2, 4, 5 };
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static unsigned __init ar5312_cpu_frequency(void)
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{
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u32 scratch, devid, clock_ctl1;
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u32 predivide_mask, multiplier_mask, doubler_mask;
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unsigned predivide_shift, multiplier_shift;
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unsigned predivide_select, predivisor, multiplier;
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/* Trust the bootrom's idea of cpu frequency. */
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scratch = ar5312_rst_reg_read(AR5312_SCRATCH);
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if (scratch)
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return scratch;
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devid = ar5312_rst_reg_read(AR5312_REV);
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devid = (devid & AR5312_REV_MAJ) >> AR5312_REV_MAJ_S;
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if (devid == AR5312_REV_MAJ_AR2313) {
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predivide_mask = AR2313_CLOCKCTL1_PREDIVIDE_MASK;
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predivide_shift = AR2313_CLOCKCTL1_PREDIVIDE_SHIFT;
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multiplier_mask = AR2313_CLOCKCTL1_MULTIPLIER_MASK;
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multiplier_shift = AR2313_CLOCKCTL1_MULTIPLIER_SHIFT;
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doubler_mask = AR2313_CLOCKCTL1_DOUBLER_MASK;
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} else { /* AR5312 and AR2312 */
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predivide_mask = AR5312_CLOCKCTL1_PREDIVIDE_MASK;
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predivide_shift = AR5312_CLOCKCTL1_PREDIVIDE_SHIFT;
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multiplier_mask = AR5312_CLOCKCTL1_MULTIPLIER_MASK;
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multiplier_shift = AR5312_CLOCKCTL1_MULTIPLIER_SHIFT;
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doubler_mask = AR5312_CLOCKCTL1_DOUBLER_MASK;
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}
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/*
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* Clocking is derived from a fixed 40MHz input clock.
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*
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* cpu_freq = input_clock * MULT (where MULT is PLL multiplier)
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* sys_freq = cpu_freq / 4 (used for APB clock, serial,
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* flash, Timer, Watchdog Timer)
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*
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* cnt_freq = cpu_freq / 2 (use for CPU count/compare)
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*
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* So, for example, with a PLL multiplier of 5, we have
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*
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* cpu_freq = 200MHz
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* sys_freq = 50MHz
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* cnt_freq = 100MHz
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*
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* We compute the CPU frequency, based on PLL settings.
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*/
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clock_ctl1 = ar5312_rst_reg_read(AR5312_CLOCKCTL1);
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predivide_select = (clock_ctl1 & predivide_mask) >> predivide_shift;
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predivisor = clockctl1_predivide_table[predivide_select];
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multiplier = (clock_ctl1 & multiplier_mask) >> multiplier_shift;
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if (clock_ctl1 & doubler_mask)
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multiplier <<= 1;
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return (40000000 / predivisor) * multiplier;
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}
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static inline unsigned ar5312_sys_frequency(void)
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{
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return ar5312_cpu_frequency() / 4;
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}
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void __init ar5312_plat_time_init(void)
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{
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mips_hpt_frequency = ar5312_cpu_frequency() / 2;
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}
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void __init ar5312_plat_mem_setup(void)
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{
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void __iomem *sdram_base;
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u32 memsize, memcfg, bank0_ac, bank1_ac;
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u32 devid;
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/* Detect memory size */
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sdram_base = ioremap(AR5312_SDRAMCTL_BASE,
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AR5312_SDRAMCTL_SIZE);
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memcfg = __raw_readl(sdram_base + AR5312_MEM_CFG1);
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bank0_ac = ATH25_REG_MS(memcfg, AR5312_MEM_CFG1_AC0);
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bank1_ac = ATH25_REG_MS(memcfg, AR5312_MEM_CFG1_AC1);
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memsize = (bank0_ac ? (1 << (bank0_ac + 1)) : 0) +
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(bank1_ac ? (1 << (bank1_ac + 1)) : 0);
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memsize <<= 20;
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memblock_add(0, memsize);
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iounmap(sdram_base);
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ar5312_rst_base = ioremap(AR5312_RST_BASE, AR5312_RST_SIZE);
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devid = ar5312_rst_reg_read(AR5312_REV);
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devid >>= AR5312_REV_WMAC_MIN_S;
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devid &= AR5312_REV_CHIP;
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ath25_board.devid = (u16)devid;
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/* Clear any lingering AHB errors */
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ar5312_rst_reg_read(AR5312_PROCADDR);
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ar5312_rst_reg_read(AR5312_DMAADDR);
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ar5312_rst_reg_write(AR5312_WDT_CTRL, AR5312_WDT_CTRL_IGNORE);
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_machine_restart = ar5312_restart;
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}
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void __init ar5312_arch_init(void)
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{
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unsigned irq = irq_create_mapping(ar5312_misc_irq_domain,
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AR5312_MISC_IRQ_UART0);
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ath25_serial_setup(AR5312_UART0_BASE, irq, ar5312_sys_frequency());
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}
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