324 строки
7.6 KiB
ArmAsm
324 строки
7.6 KiB
ArmAsm
/*
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* linux/arch/arm/mm/proc-sa1100.S
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*
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* Copyright (C) 1997-2002 Russell King
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* MMU functions for SA110
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*
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* These are the low level assembler for performing cache and TLB
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* functions on the StrongARM-1100 and StrongARM-1110.
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*
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* Note that SA1100 and SA1110 share everything but their name and CPU ID.
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*
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* 12-jun-2000, Erik Mouw (J.A.K.Mouw@its.tudelft.nl):
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* Flush the read buffer at context switches
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*/
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#include <linux/linkage.h>
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#include <linux/init.h>
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#include <asm/assembler.h>
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#include <asm/asm-offsets.h>
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#include <asm/procinfo.h>
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#include <asm/hardware.h>
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#include <asm/pgtable.h>
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/*
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* the cache line size of the I and D cache
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*/
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#define DCACHELINESIZE 32
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#define FLUSH_OFFSET 32768
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.macro flush_1100_dcache rd, ra, re
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ldr \rd, =flush_base
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ldr \ra, [\rd]
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eor \ra, \ra, #FLUSH_OFFSET
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str \ra, [\rd]
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add \re, \ra, #8192 @ only necessary for 8k
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1001: ldr \rd, [\ra], #DCACHELINESIZE
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teq \re, \ra
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bne 1001b
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#ifdef FLUSH_BASE_MINICACHE
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add \ra, \ra, #FLUSH_BASE_MINICACHE - FLUSH_BASE
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add \re, \ra, #512 @ only 512 bytes
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1002: ldr \rd, [\ra], #DCACHELINESIZE
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teq \re, \ra
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bne 1002b
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#endif
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.endm
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.data
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flush_base:
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.long FLUSH_BASE
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.text
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__INIT
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/*
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* cpu_sa1100_proc_init()
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*/
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ENTRY(cpu_sa1100_proc_init)
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mov r0, #0
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mcr p15, 0, r0, c15, c1, 2 @ Enable clock switching
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mcr p15, 0, r0, c9, c0, 5 @ Allow read-buffer operations from userland
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mov pc, lr
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.previous
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/*
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* cpu_sa1100_proc_fin()
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*
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* Prepare the CPU for reset:
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* - Disable interrupts
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* - Clean and turn off caches.
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*/
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ENTRY(cpu_sa1100_proc_fin)
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stmfd sp!, {lr}
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mov ip, #PSR_F_BIT | PSR_I_BIT | SVC_MODE
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msr cpsr_c, ip
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flush_1100_dcache r0, r1, r2 @ clean caches
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mov r0, #0
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mcr p15, 0, r0, c15, c2, 2 @ Disable clock switching
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mrc p15, 0, r0, c1, c0, 0 @ ctrl register
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bic r0, r0, #0x1000 @ ...i............
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bic r0, r0, #0x000e @ ............wca.
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mcr p15, 0, r0, c1, c0, 0 @ disable caches
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ldmfd sp!, {pc}
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/*
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* cpu_sa1100_reset(loc)
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*
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* Perform a soft reset of the system. Put the CPU into the
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* same state as it would be if it had been reset, and branch
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* to what would be the reset vector.
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*
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* loc: location to jump to for soft reset
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*/
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.align 5
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ENTRY(cpu_sa1100_reset)
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mov ip, #0
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mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
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mcr p15, 0, ip, c7, c10, 4 @ drain WB
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mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
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mrc p15, 0, ip, c1, c0, 0 @ ctrl register
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bic ip, ip, #0x000f @ ............wcam
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bic ip, ip, #0x1100 @ ...i...s........
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mcr p15, 0, ip, c1, c0, 0 @ ctrl register
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mov pc, r0
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/*
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* cpu_sa1100_do_idle(type)
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*
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* Cause the processor to idle
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*
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* type: call type:
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* 0 = slow idle
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* 1 = fast idle
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* 2 = switch to slow processor clock
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* 3 = switch to fast processor clock
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*/
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.align 5
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ENTRY(cpu_sa1100_do_idle)
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mov r0, r0 @ 4 nop padding
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mov r0, r0
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mov r0, r0
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mov r0, r0 @ 4 nop padding
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mov r0, r0
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mov r0, r0
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mov r0, #0
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ldr r1, =UNCACHEABLE_ADDR @ ptr to uncacheable address
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@ --- aligned to a cache line
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mcr p15, 0, r0, c15, c2, 2 @ disable clock switching
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ldr r1, [r1, #0] @ force switch to MCLK
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mcr p15, 0, r0, c15, c8, 2 @ wait for interrupt
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mov r0, r0 @ safety
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mcr p15, 0, r0, c15, c1, 2 @ enable clock switching
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mov pc, lr
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/* ================================= CACHE ================================ */
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/*
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* cpu_sa1100_dcache_clean_area(addr,sz)
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*
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* Clean the specified entry of any caches such that the MMU
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* translation fetches will obtain correct data.
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*
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* addr: cache-unaligned virtual address
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*/
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.align 5
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ENTRY(cpu_sa1100_dcache_clean_area)
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1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
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add r0, r0, #DCACHELINESIZE
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subs r1, r1, #DCACHELINESIZE
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bhi 1b
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mov pc, lr
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/* =============================== PageTable ============================== */
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/*
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* cpu_sa1100_switch_mm(pgd)
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*
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* Set the translation base pointer to be as described by pgd.
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*
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* pgd: new page tables
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*/
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.align 5
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ENTRY(cpu_sa1100_switch_mm)
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flush_1100_dcache r3, ip, r1
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mov ip, #0
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mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache
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mcr p15, 0, ip, c9, c0, 0 @ invalidate RB
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mcr p15, 0, ip, c7, c10, 4 @ drain WB
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mcr p15, 0, r0, c2, c0, 0 @ load page table pointer
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mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
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mov pc, lr
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/*
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* cpu_sa1100_set_pte(ptep, pte)
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*
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* Set a PTE and flush it out
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*/
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.align 5
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ENTRY(cpu_sa1100_set_pte)
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str r1, [r0], #-2048 @ linux version
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eor r1, r1, #L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_WRITE | L_PTE_DIRTY
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bic r2, r1, #PTE_SMALL_AP_MASK
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bic r2, r2, #PTE_TYPE_MASK
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orr r2, r2, #PTE_TYPE_SMALL
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tst r1, #L_PTE_USER @ User?
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orrne r2, r2, #PTE_SMALL_AP_URO_SRW
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tst r1, #L_PTE_WRITE | L_PTE_DIRTY @ Write and Dirty?
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orreq r2, r2, #PTE_SMALL_AP_UNO_SRW
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tst r1, #L_PTE_PRESENT | L_PTE_YOUNG @ Present and Young?
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movne r2, #0
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str r2, [r0] @ hardware version
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mov r0, r0
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mcr p15, 0, r0, c7, c10, 1 @ clean D entry
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mcr p15, 0, r0, c7, c10, 4 @ drain WB
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mov pc, lr
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__INIT
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.type __sa1100_setup, #function
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__sa1100_setup:
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mov r0, #0
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mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4
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mcr p15, 0, r0, c7, c10, 4 @ drain write buffer on v4
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mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4
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mrc p15, 0, r0, c1, c0 @ get control register v4
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ldr r5, sa1100_cr1_clear
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bic r0, r0, r5
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ldr r5, sa1100_cr1_set
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orr r0, r0, r5
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mov pc, lr
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.size __sa1100_setup, . - __sa1100_setup
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/*
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* R
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* .RVI ZFRS BLDP WCAM
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* ..11 0001 ..11 1101
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*
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*/
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.type sa1100_cr1_clear, #object
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.type sa1100_cr1_set, #object
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sa1100_cr1_clear:
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.word 0x3f3f
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sa1100_cr1_set:
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.word 0x313d
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__INITDATA
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/*
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* Purpose : Function pointers used to access above functions - all calls
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* come through these
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*/
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/*
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* SA1100 and SA1110 share the same function calls
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*/
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.type sa1100_processor_functions, #object
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ENTRY(sa1100_processor_functions)
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.word v4_early_abort
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.word cpu_sa1100_proc_init
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.word cpu_sa1100_proc_fin
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.word cpu_sa1100_reset
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.word cpu_sa1100_do_idle
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.word cpu_sa1100_dcache_clean_area
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.word cpu_sa1100_switch_mm
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.word cpu_sa1100_set_pte
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.size sa1100_processor_functions, . - sa1100_processor_functions
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.section ".rodata"
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.type cpu_arch_name, #object
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cpu_arch_name:
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.asciz "armv4"
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.size cpu_arch_name, . - cpu_arch_name
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.type cpu_elf_name, #object
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cpu_elf_name:
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.asciz "v4"
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.size cpu_elf_name, . - cpu_elf_name
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.type cpu_sa1100_name, #object
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cpu_sa1100_name:
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.asciz "StrongARM-1100"
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.size cpu_sa1100_name, . - cpu_sa1100_name
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.type cpu_sa1110_name, #object
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cpu_sa1110_name:
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.asciz "StrongARM-1110"
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.size cpu_sa1110_name, . - cpu_sa1110_name
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.align
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.section ".proc.info.init", #alloc, #execinstr
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.type __sa1100_proc_info,#object
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__sa1100_proc_info:
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.long 0x4401a110
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.long 0xfffffff0
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.long PMD_TYPE_SECT | \
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PMD_SECT_BUFFERABLE | \
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PMD_SECT_CACHEABLE | \
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PMD_SECT_AP_WRITE | \
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PMD_SECT_AP_READ
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b __sa1100_setup
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.long cpu_arch_name
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.long cpu_elf_name
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.long HWCAP_SWP | HWCAP_HALF | HWCAP_26BIT | HWCAP_FAST_MULT
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.long cpu_sa1100_name
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.long sa1100_processor_functions
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.long v4wb_tlb_fns
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.long v4_mc_user_fns
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.long v4wb_cache_fns
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.size __sa1100_proc_info, . - __sa1100_proc_info
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.type __sa1110_proc_info,#object
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__sa1110_proc_info:
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.long 0x6901b110
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.long 0xfffffff0
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.long PMD_TYPE_SECT | \
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PMD_SECT_BUFFERABLE | \
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PMD_SECT_CACHEABLE | \
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PMD_SECT_AP_WRITE | \
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PMD_SECT_AP_READ
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b __sa1100_setup
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.long cpu_arch_name
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.long cpu_elf_name
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.long HWCAP_SWP | HWCAP_HALF | HWCAP_26BIT | HWCAP_FAST_MULT
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.long cpu_sa1110_name
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.long sa1100_processor_functions
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.long v4wb_tlb_fns
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.long v4_mc_user_fns
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.long v4wb_cache_fns
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.size __sa1110_proc_info, . - __sa1110_proc_info
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