Conor Dooley 2a5303b499 Documentation: riscv: fix insufficient list item indent ... When adding the ISA string ordering rules, I didn't sufficiently indent one of the list items. Reported-by: kernel test robot <lkp@intel.com> Link: https://lore.kernel.org/linux-doc/202301300743.bp7Dpazv-lkp@intel.com/ Fixes: f07b2b3f9d ("Documentation: riscv: add a section about ISA string ordering in /proc/cpuinfo") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Bagas Sanjaya <bagasdotme@gmail.com> Link: https://lore.kernel.org/r/20230129235701.2393241-1-conor@kernel.org Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>		2023-02-14 16:00:02 -08:00
..
boot-image-header.rst	RISC-V: Typo fixes in image header and documentation.	2019-12-19 09:32:45 -07:00
features.rst	docs: archis: add a per-architecture features list	2020-12-03 15:10:15 -07:00
index.rst	doc: RISC-V: Document that misaligned accesses are supported	2022-10-12 08:58:10 -07:00
patch-acceptance.rst	Documentation: RISC-V: patch-acceptance: s/implementor/implementer	2022-12-13 09:38:28 -08:00
uabi.rst	Documentation: riscv: fix insufficient list item indent	2023-02-14 16:00:02 -08:00
vm-layout.rst	Documentation: riscv: Document the sv57 VM layout	2022-11-21 14:40:26 -07:00