398 строки
8.9 KiB
C
398 строки
8.9 KiB
C
/*
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* Copyright (C) STMicroelectronics 2016
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*
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* Author: Gerald Baeza <gerald.baeza@st.com>
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*
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* License terms: GNU General Public License (GPL), version 2
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*
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* Inspired by timer-stm32.c from Maxime Coquelin
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* pwm-atmel.c from Bo Shen
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*/
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#include <linux/mfd/stm32-timers.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/platform_device.h>
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#include <linux/pwm.h>
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#define CCMR_CHANNEL_SHIFT 8
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#define CCMR_CHANNEL_MASK 0xFF
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#define MAX_BREAKINPUT 2
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struct stm32_pwm {
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struct pwm_chip chip;
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struct device *dev;
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struct clk *clk;
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struct regmap *regmap;
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u32 max_arr;
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bool have_complementary_output;
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};
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struct stm32_breakinput {
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u32 index;
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u32 level;
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u32 filter;
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};
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static inline struct stm32_pwm *to_stm32_pwm_dev(struct pwm_chip *chip)
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{
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return container_of(chip, struct stm32_pwm, chip);
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}
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static u32 active_channels(struct stm32_pwm *dev)
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{
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u32 ccer;
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regmap_read(dev->regmap, TIM_CCER, &ccer);
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return ccer & TIM_CCER_CCXE;
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}
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static int write_ccrx(struct stm32_pwm *dev, int ch, u32 value)
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{
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switch (ch) {
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case 0:
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return regmap_write(dev->regmap, TIM_CCR1, value);
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case 1:
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return regmap_write(dev->regmap, TIM_CCR2, value);
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case 2:
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return regmap_write(dev->regmap, TIM_CCR3, value);
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case 3:
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return regmap_write(dev->regmap, TIM_CCR4, value);
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}
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return -EINVAL;
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}
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static int stm32_pwm_config(struct stm32_pwm *priv, int ch,
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int duty_ns, int period_ns)
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{
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unsigned long long prd, div, dty;
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unsigned int prescaler = 0;
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u32 ccmr, mask, shift;
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/* Period and prescaler values depends on clock rate */
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div = (unsigned long long)clk_get_rate(priv->clk) * period_ns;
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do_div(div, NSEC_PER_SEC);
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prd = div;
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while (div > priv->max_arr) {
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prescaler++;
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div = prd;
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do_div(div, prescaler + 1);
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}
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prd = div;
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if (prescaler > MAX_TIM_PSC)
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return -EINVAL;
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/*
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* All channels share the same prescaler and counter so when two
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* channels are active at the same time we can't change them
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*/
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if (active_channels(priv) & ~(1 << ch * 4)) {
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u32 psc, arr;
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regmap_read(priv->regmap, TIM_PSC, &psc);
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regmap_read(priv->regmap, TIM_ARR, &arr);
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if ((psc != prescaler) || (arr != prd - 1))
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return -EBUSY;
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}
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regmap_write(priv->regmap, TIM_PSC, prescaler);
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regmap_write(priv->regmap, TIM_ARR, prd - 1);
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regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_ARPE, TIM_CR1_ARPE);
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/* Calculate the duty cycles */
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dty = prd * duty_ns;
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do_div(dty, period_ns);
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write_ccrx(priv, ch, dty);
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/* Configure output mode */
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shift = (ch & 0x1) * CCMR_CHANNEL_SHIFT;
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ccmr = (TIM_CCMR_PE | TIM_CCMR_M1) << shift;
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mask = CCMR_CHANNEL_MASK << shift;
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if (ch < 2)
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regmap_update_bits(priv->regmap, TIM_CCMR1, mask, ccmr);
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else
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regmap_update_bits(priv->regmap, TIM_CCMR2, mask, ccmr);
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regmap_update_bits(priv->regmap, TIM_BDTR,
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TIM_BDTR_MOE | TIM_BDTR_AOE,
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TIM_BDTR_MOE | TIM_BDTR_AOE);
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return 0;
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}
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static int stm32_pwm_set_polarity(struct stm32_pwm *priv, int ch,
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enum pwm_polarity polarity)
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{
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u32 mask;
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mask = TIM_CCER_CC1P << (ch * 4);
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if (priv->have_complementary_output)
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mask |= TIM_CCER_CC1NP << (ch * 4);
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regmap_update_bits(priv->regmap, TIM_CCER, mask,
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polarity == PWM_POLARITY_NORMAL ? 0 : mask);
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return 0;
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}
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static int stm32_pwm_enable(struct stm32_pwm *priv, int ch)
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{
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u32 mask;
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int ret;
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ret = clk_enable(priv->clk);
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if (ret)
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return ret;
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/* Enable channel */
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mask = TIM_CCER_CC1E << (ch * 4);
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if (priv->have_complementary_output)
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mask |= TIM_CCER_CC1NE << (ch * 4);
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regmap_update_bits(priv->regmap, TIM_CCER, mask, mask);
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/* Make sure that registers are updated */
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regmap_update_bits(priv->regmap, TIM_EGR, TIM_EGR_UG, TIM_EGR_UG);
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/* Enable controller */
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regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN, TIM_CR1_CEN);
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return 0;
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}
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static void stm32_pwm_disable(struct stm32_pwm *priv, int ch)
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{
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u32 mask;
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/* Disable channel */
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mask = TIM_CCER_CC1E << (ch * 4);
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if (priv->have_complementary_output)
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mask |= TIM_CCER_CC1NE << (ch * 4);
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regmap_update_bits(priv->regmap, TIM_CCER, mask, 0);
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/* When all channels are disabled, we can disable the controller */
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if (!active_channels(priv))
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regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN, 0);
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clk_disable(priv->clk);
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}
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static int stm32_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
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struct pwm_state *state)
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{
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bool enabled;
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struct stm32_pwm *priv = to_stm32_pwm_dev(chip);
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int ret;
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enabled = pwm->state.enabled;
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if (enabled && !state->enabled) {
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stm32_pwm_disable(priv, pwm->hwpwm);
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return 0;
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}
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if (state->polarity != pwm->state.polarity)
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stm32_pwm_set_polarity(priv, pwm->hwpwm, state->polarity);
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ret = stm32_pwm_config(priv, pwm->hwpwm,
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state->duty_cycle, state->period);
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if (ret)
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return ret;
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if (!enabled && state->enabled)
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ret = stm32_pwm_enable(priv, pwm->hwpwm);
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return ret;
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}
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static const struct pwm_ops stm32pwm_ops = {
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.owner = THIS_MODULE,
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.apply = stm32_pwm_apply,
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};
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static int stm32_pwm_set_breakinput(struct stm32_pwm *priv,
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int index, int level, int filter)
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{
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u32 bke = (index == 0) ? TIM_BDTR_BKE : TIM_BDTR_BK2E;
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int shift = (index == 0) ? TIM_BDTR_BKF_SHIFT : TIM_BDTR_BK2F_SHIFT;
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u32 mask = (index == 0) ? TIM_BDTR_BKE | TIM_BDTR_BKP | TIM_BDTR_BKF
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: TIM_BDTR_BK2E | TIM_BDTR_BK2P | TIM_BDTR_BK2F;
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u32 bdtr = bke;
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/*
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* The both bits could be set since only one will be wrote
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* due to mask value.
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*/
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if (level)
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bdtr |= TIM_BDTR_BKP | TIM_BDTR_BK2P;
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bdtr |= (filter & TIM_BDTR_BKF_MASK) << shift;
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regmap_update_bits(priv->regmap, TIM_BDTR, mask, bdtr);
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regmap_read(priv->regmap, TIM_BDTR, &bdtr);
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return (bdtr & bke) ? 0 : -EINVAL;
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}
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static int stm32_pwm_apply_breakinputs(struct stm32_pwm *priv,
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struct device_node *np)
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{
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struct stm32_breakinput breakinput[MAX_BREAKINPUT];
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int nb, ret, i, array_size;
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nb = of_property_count_elems_of_size(np, "st,breakinput",
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sizeof(struct stm32_breakinput));
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/*
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* Because "st,breakinput" parameter is optional do not make probe
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* failed if it doesn't exist.
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*/
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if (nb <= 0)
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return 0;
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if (nb > MAX_BREAKINPUT)
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return -EINVAL;
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array_size = nb * sizeof(struct stm32_breakinput) / sizeof(u32);
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ret = of_property_read_u32_array(np, "st,breakinput",
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(u32 *)breakinput, array_size);
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if (ret)
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return ret;
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for (i = 0; i < nb && !ret; i++) {
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ret = stm32_pwm_set_breakinput(priv,
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breakinput[i].index,
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breakinput[i].level,
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breakinput[i].filter);
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}
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return ret;
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}
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static void stm32_pwm_detect_complementary(struct stm32_pwm *priv)
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{
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u32 ccer;
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/*
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* If complementary bit doesn't exist writing 1 will have no
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* effect so we can detect it.
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*/
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regmap_update_bits(priv->regmap,
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TIM_CCER, TIM_CCER_CC1NE, TIM_CCER_CC1NE);
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regmap_read(priv->regmap, TIM_CCER, &ccer);
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regmap_update_bits(priv->regmap, TIM_CCER, TIM_CCER_CC1NE, 0);
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priv->have_complementary_output = (ccer != 0);
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}
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static int stm32_pwm_detect_channels(struct stm32_pwm *priv)
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{
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u32 ccer;
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int npwm = 0;
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/*
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* If channels enable bits don't exist writing 1 will have no
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* effect so we can detect and count them.
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*/
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regmap_update_bits(priv->regmap,
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TIM_CCER, TIM_CCER_CCXE, TIM_CCER_CCXE);
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regmap_read(priv->regmap, TIM_CCER, &ccer);
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regmap_update_bits(priv->regmap, TIM_CCER, TIM_CCER_CCXE, 0);
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if (ccer & TIM_CCER_CC1E)
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npwm++;
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if (ccer & TIM_CCER_CC2E)
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npwm++;
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if (ccer & TIM_CCER_CC3E)
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npwm++;
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if (ccer & TIM_CCER_CC4E)
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npwm++;
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return npwm;
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}
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static int stm32_pwm_probe(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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struct device_node *np = dev->of_node;
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struct stm32_timers *ddata = dev_get_drvdata(pdev->dev.parent);
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struct stm32_pwm *priv;
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int ret;
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priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
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if (!priv)
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return -ENOMEM;
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priv->regmap = ddata->regmap;
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priv->clk = ddata->clk;
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priv->max_arr = ddata->max_arr;
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if (!priv->regmap || !priv->clk)
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return -EINVAL;
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ret = stm32_pwm_apply_breakinputs(priv, np);
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if (ret)
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return ret;
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stm32_pwm_detect_complementary(priv);
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priv->chip.base = -1;
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priv->chip.dev = dev;
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priv->chip.ops = &stm32pwm_ops;
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priv->chip.npwm = stm32_pwm_detect_channels(priv);
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ret = pwmchip_add(&priv->chip);
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if (ret < 0)
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return ret;
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platform_set_drvdata(pdev, priv);
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return 0;
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}
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static int stm32_pwm_remove(struct platform_device *pdev)
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{
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struct stm32_pwm *priv = platform_get_drvdata(pdev);
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unsigned int i;
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for (i = 0; i < priv->chip.npwm; i++)
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pwm_disable(&priv->chip.pwms[i]);
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pwmchip_remove(&priv->chip);
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return 0;
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}
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static const struct of_device_id stm32_pwm_of_match[] = {
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{ .compatible = "st,stm32-pwm", },
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{ /* end node */ },
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};
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MODULE_DEVICE_TABLE(of, stm32_pwm_of_match);
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static struct platform_driver stm32_pwm_driver = {
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.probe = stm32_pwm_probe,
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.remove = stm32_pwm_remove,
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.driver = {
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.name = "stm32-pwm",
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.of_match_table = stm32_pwm_of_match,
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},
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};
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module_platform_driver(stm32_pwm_driver);
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MODULE_ALIAS("platform:stm32-pwm");
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MODULE_DESCRIPTION("STMicroelectronics STM32 PWM driver");
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MODULE_LICENSE("GPL v2");
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