483 строки
12 KiB
C
483 строки
12 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* S3C2416/2450 CPUfreq Support
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*
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* Copyright 2011 Heiko Stuebner <heiko@sntech.de>
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*
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* based on s3c64xx_cpufreq.c
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*
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* Copyright 2009 Wolfson Microelectronics plc
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*/
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#include <linux/kernel.h>
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#include <linux/types.h>
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#include <linux/init.h>
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#include <linux/cpufreq.h>
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#include <linux/clk.h>
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#include <linux/err.h>
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#include <linux/regulator/consumer.h>
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#include <linux/reboot.h>
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#include <linux/module.h>
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static DEFINE_MUTEX(cpufreq_lock);
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struct s3c2416_data {
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struct clk *armdiv;
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struct clk *armclk;
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struct clk *hclk;
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unsigned long regulator_latency;
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#ifdef CONFIG_ARM_S3C2416_CPUFREQ_VCORESCALE
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struct regulator *vddarm;
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#endif
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struct cpufreq_frequency_table *freq_table;
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bool is_dvs;
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bool disable_dvs;
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};
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static struct s3c2416_data s3c2416_cpufreq;
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struct s3c2416_dvfs {
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unsigned int vddarm_min;
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unsigned int vddarm_max;
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};
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/* pseudo-frequency for dvs mode */
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#define FREQ_DVS 132333
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/* frequency to sleep and reboot in
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* it's essential to leave dvs, as some boards do not reconfigure the
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* regulator on reboot
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*/
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#define FREQ_SLEEP 133333
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/* Sources for the ARMCLK */
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#define SOURCE_HCLK 0
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#define SOURCE_ARMDIV 1
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#ifdef CONFIG_ARM_S3C2416_CPUFREQ_VCORESCALE
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/* S3C2416 only supports changing the voltage in the dvs-mode.
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* Voltages down to 1.0V seem to work, so we take what the regulator
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* can get us.
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*/
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static struct s3c2416_dvfs s3c2416_dvfs_table[] = {
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[SOURCE_HCLK] = { 950000, 1250000 },
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[SOURCE_ARMDIV] = { 1250000, 1350000 },
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};
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#endif
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static struct cpufreq_frequency_table s3c2416_freq_table[] = {
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{ 0, SOURCE_HCLK, FREQ_DVS },
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{ 0, SOURCE_ARMDIV, 133333 },
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{ 0, SOURCE_ARMDIV, 266666 },
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{ 0, SOURCE_ARMDIV, 400000 },
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{ 0, 0, CPUFREQ_TABLE_END },
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};
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static struct cpufreq_frequency_table s3c2450_freq_table[] = {
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{ 0, SOURCE_HCLK, FREQ_DVS },
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{ 0, SOURCE_ARMDIV, 133500 },
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{ 0, SOURCE_ARMDIV, 267000 },
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{ 0, SOURCE_ARMDIV, 534000 },
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{ 0, 0, CPUFREQ_TABLE_END },
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};
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static unsigned int s3c2416_cpufreq_get_speed(unsigned int cpu)
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{
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struct s3c2416_data *s3c_freq = &s3c2416_cpufreq;
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if (cpu != 0)
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return 0;
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/* return our pseudo-frequency when in dvs mode */
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if (s3c_freq->is_dvs)
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return FREQ_DVS;
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return clk_get_rate(s3c_freq->armclk) / 1000;
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}
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static int s3c2416_cpufreq_set_armdiv(struct s3c2416_data *s3c_freq,
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unsigned int freq)
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{
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int ret;
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if (clk_get_rate(s3c_freq->armdiv) / 1000 != freq) {
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ret = clk_set_rate(s3c_freq->armdiv, freq * 1000);
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if (ret < 0) {
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pr_err("cpufreq: Failed to set armdiv rate %dkHz: %d\n",
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freq, ret);
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return ret;
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}
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}
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return 0;
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}
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static int s3c2416_cpufreq_enter_dvs(struct s3c2416_data *s3c_freq, int idx)
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{
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#ifdef CONFIG_ARM_S3C2416_CPUFREQ_VCORESCALE
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struct s3c2416_dvfs *dvfs;
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#endif
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int ret;
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if (s3c_freq->is_dvs) {
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pr_debug("cpufreq: already in dvs mode, nothing to do\n");
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return 0;
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}
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pr_debug("cpufreq: switching armclk to hclk (%lukHz)\n",
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clk_get_rate(s3c_freq->hclk) / 1000);
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ret = clk_set_parent(s3c_freq->armclk, s3c_freq->hclk);
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if (ret < 0) {
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pr_err("cpufreq: Failed to switch armclk to hclk: %d\n", ret);
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return ret;
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}
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#ifdef CONFIG_ARM_S3C2416_CPUFREQ_VCORESCALE
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/* changing the core voltage is only allowed when in dvs mode */
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if (s3c_freq->vddarm) {
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dvfs = &s3c2416_dvfs_table[idx];
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pr_debug("cpufreq: setting regulator to %d-%d\n",
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dvfs->vddarm_min, dvfs->vddarm_max);
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ret = regulator_set_voltage(s3c_freq->vddarm,
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dvfs->vddarm_min,
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dvfs->vddarm_max);
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/* when lowering the voltage failed, there is nothing to do */
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if (ret != 0)
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pr_err("cpufreq: Failed to set VDDARM: %d\n", ret);
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}
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#endif
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s3c_freq->is_dvs = 1;
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return 0;
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}
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static int s3c2416_cpufreq_leave_dvs(struct s3c2416_data *s3c_freq, int idx)
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{
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#ifdef CONFIG_ARM_S3C2416_CPUFREQ_VCORESCALE
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struct s3c2416_dvfs *dvfs;
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#endif
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int ret;
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if (!s3c_freq->is_dvs) {
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pr_debug("cpufreq: not in dvs mode, so can't leave\n");
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return 0;
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}
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#ifdef CONFIG_ARM_S3C2416_CPUFREQ_VCORESCALE
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if (s3c_freq->vddarm) {
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dvfs = &s3c2416_dvfs_table[idx];
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pr_debug("cpufreq: setting regulator to %d-%d\n",
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dvfs->vddarm_min, dvfs->vddarm_max);
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ret = regulator_set_voltage(s3c_freq->vddarm,
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dvfs->vddarm_min,
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dvfs->vddarm_max);
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if (ret != 0) {
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pr_err("cpufreq: Failed to set VDDARM: %d\n", ret);
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return ret;
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}
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}
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#endif
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/* force armdiv to hclk frequency for transition from dvs*/
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if (clk_get_rate(s3c_freq->armdiv) > clk_get_rate(s3c_freq->hclk)) {
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pr_debug("cpufreq: force armdiv to hclk frequency (%lukHz)\n",
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clk_get_rate(s3c_freq->hclk) / 1000);
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ret = s3c2416_cpufreq_set_armdiv(s3c_freq,
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clk_get_rate(s3c_freq->hclk) / 1000);
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if (ret < 0) {
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pr_err("cpufreq: Failed to set the armdiv to %lukHz: %d\n",
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clk_get_rate(s3c_freq->hclk) / 1000, ret);
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return ret;
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}
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}
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pr_debug("cpufreq: switching armclk parent to armdiv (%lukHz)\n",
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clk_get_rate(s3c_freq->armdiv) / 1000);
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ret = clk_set_parent(s3c_freq->armclk, s3c_freq->armdiv);
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if (ret < 0) {
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pr_err("cpufreq: Failed to switch armclk clock parent to armdiv: %d\n",
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ret);
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return ret;
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}
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s3c_freq->is_dvs = 0;
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return 0;
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}
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static int s3c2416_cpufreq_set_target(struct cpufreq_policy *policy,
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unsigned int index)
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{
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struct s3c2416_data *s3c_freq = &s3c2416_cpufreq;
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unsigned int new_freq;
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int idx, ret, to_dvs = 0;
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mutex_lock(&cpufreq_lock);
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idx = s3c_freq->freq_table[index].driver_data;
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if (idx == SOURCE_HCLK)
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to_dvs = 1;
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/* switching to dvs when it's not allowed */
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if (to_dvs && s3c_freq->disable_dvs) {
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pr_debug("cpufreq: entering dvs mode not allowed\n");
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ret = -EINVAL;
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goto out;
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}
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/* When leavin dvs mode, always switch the armdiv to the hclk rate
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* The S3C2416 has stability issues when switching directly to
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* higher frequencies.
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*/
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new_freq = (s3c_freq->is_dvs && !to_dvs)
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? clk_get_rate(s3c_freq->hclk) / 1000
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: s3c_freq->freq_table[index].frequency;
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if (to_dvs) {
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pr_debug("cpufreq: enter dvs\n");
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ret = s3c2416_cpufreq_enter_dvs(s3c_freq, idx);
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} else if (s3c_freq->is_dvs) {
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pr_debug("cpufreq: leave dvs\n");
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ret = s3c2416_cpufreq_leave_dvs(s3c_freq, idx);
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} else {
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pr_debug("cpufreq: change armdiv to %dkHz\n", new_freq);
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ret = s3c2416_cpufreq_set_armdiv(s3c_freq, new_freq);
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}
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out:
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mutex_unlock(&cpufreq_lock);
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return ret;
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}
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#ifdef CONFIG_ARM_S3C2416_CPUFREQ_VCORESCALE
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static void s3c2416_cpufreq_cfg_regulator(struct s3c2416_data *s3c_freq)
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{
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int count, v, i, found;
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struct cpufreq_frequency_table *pos;
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struct s3c2416_dvfs *dvfs;
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count = regulator_count_voltages(s3c_freq->vddarm);
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if (count < 0) {
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pr_err("cpufreq: Unable to check supported voltages\n");
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return;
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}
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if (!count)
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goto out;
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cpufreq_for_each_valid_entry(pos, s3c_freq->freq_table) {
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dvfs = &s3c2416_dvfs_table[pos->driver_data];
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found = 0;
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/* Check only the min-voltage, more is always ok on S3C2416 */
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for (i = 0; i < count; i++) {
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v = regulator_list_voltage(s3c_freq->vddarm, i);
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if (v >= dvfs->vddarm_min)
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found = 1;
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}
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if (!found) {
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pr_debug("cpufreq: %dkHz unsupported by regulator\n",
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pos->frequency);
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pos->frequency = CPUFREQ_ENTRY_INVALID;
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}
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}
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out:
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/* Guessed */
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s3c_freq->regulator_latency = 1 * 1000 * 1000;
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}
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#endif
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static int s3c2416_cpufreq_reboot_notifier_evt(struct notifier_block *this,
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unsigned long event, void *ptr)
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{
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struct s3c2416_data *s3c_freq = &s3c2416_cpufreq;
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int ret;
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mutex_lock(&cpufreq_lock);
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/* disable further changes */
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s3c_freq->disable_dvs = 1;
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mutex_unlock(&cpufreq_lock);
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/* some boards don't reconfigure the regulator on reboot, which
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* could lead to undervolting the cpu when the clock is reset.
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* Therefore we always leave the DVS mode on reboot.
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*/
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if (s3c_freq->is_dvs) {
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pr_debug("cpufreq: leave dvs on reboot\n");
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ret = cpufreq_driver_target(cpufreq_cpu_get(0), FREQ_SLEEP, 0);
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if (ret < 0)
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return NOTIFY_BAD;
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}
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return NOTIFY_DONE;
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}
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static struct notifier_block s3c2416_cpufreq_reboot_notifier = {
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.notifier_call = s3c2416_cpufreq_reboot_notifier_evt,
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};
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static int s3c2416_cpufreq_driver_init(struct cpufreq_policy *policy)
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{
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struct s3c2416_data *s3c_freq = &s3c2416_cpufreq;
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struct cpufreq_frequency_table *pos;
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struct clk *msysclk;
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unsigned long rate;
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int ret;
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if (policy->cpu != 0)
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return -EINVAL;
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msysclk = clk_get(NULL, "msysclk");
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if (IS_ERR(msysclk)) {
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ret = PTR_ERR(msysclk);
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pr_err("cpufreq: Unable to obtain msysclk: %d\n", ret);
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return ret;
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}
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/*
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* S3C2416 and S3C2450 share the same processor-ID and also provide no
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* other means to distinguish them other than through the rate of
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* msysclk. On S3C2416 msysclk runs at 800MHz and on S3C2450 at 533MHz.
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*/
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rate = clk_get_rate(msysclk);
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if (rate == 800 * 1000 * 1000) {
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pr_info("cpufreq: msysclk running at %lukHz, using S3C2416 frequency table\n",
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rate / 1000);
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s3c_freq->freq_table = s3c2416_freq_table;
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policy->cpuinfo.max_freq = 400000;
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} else if (rate / 1000 == 534000) {
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pr_info("cpufreq: msysclk running at %lukHz, using S3C2450 frequency table\n",
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rate / 1000);
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s3c_freq->freq_table = s3c2450_freq_table;
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policy->cpuinfo.max_freq = 534000;
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}
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/* not needed anymore */
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clk_put(msysclk);
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if (s3c_freq->freq_table == NULL) {
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pr_err("cpufreq: No frequency information for this CPU, msysclk at %lukHz\n",
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rate / 1000);
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return -ENODEV;
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}
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s3c_freq->is_dvs = 0;
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s3c_freq->armdiv = clk_get(NULL, "armdiv");
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if (IS_ERR(s3c_freq->armdiv)) {
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ret = PTR_ERR(s3c_freq->armdiv);
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pr_err("cpufreq: Unable to obtain ARMDIV: %d\n", ret);
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return ret;
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}
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s3c_freq->hclk = clk_get(NULL, "hclk");
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if (IS_ERR(s3c_freq->hclk)) {
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ret = PTR_ERR(s3c_freq->hclk);
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pr_err("cpufreq: Unable to obtain HCLK: %d\n", ret);
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goto err_hclk;
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}
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/* chech hclk rate, we only support the common 133MHz for now
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* hclk could also run at 66MHz, but this not often used
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*/
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rate = clk_get_rate(s3c_freq->hclk);
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if (rate < 133 * 1000 * 1000) {
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pr_err("cpufreq: HCLK not at 133MHz\n");
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ret = -EINVAL;
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goto err_armclk;
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}
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s3c_freq->armclk = clk_get(NULL, "armclk");
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if (IS_ERR(s3c_freq->armclk)) {
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ret = PTR_ERR(s3c_freq->armclk);
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pr_err("cpufreq: Unable to obtain ARMCLK: %d\n", ret);
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goto err_armclk;
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}
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#ifdef CONFIG_ARM_S3C2416_CPUFREQ_VCORESCALE
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s3c_freq->vddarm = regulator_get(NULL, "vddarm");
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if (IS_ERR(s3c_freq->vddarm)) {
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ret = PTR_ERR(s3c_freq->vddarm);
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pr_err("cpufreq: Failed to obtain VDDARM: %d\n", ret);
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goto err_vddarm;
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}
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s3c2416_cpufreq_cfg_regulator(s3c_freq);
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#else
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s3c_freq->regulator_latency = 0;
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#endif
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cpufreq_for_each_entry(pos, s3c_freq->freq_table) {
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/* special handling for dvs mode */
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if (pos->driver_data == 0) {
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if (!s3c_freq->hclk) {
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pr_debug("cpufreq: %dkHz unsupported as it would need unavailable dvs mode\n",
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pos->frequency);
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pos->frequency = CPUFREQ_ENTRY_INVALID;
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} else {
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continue;
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}
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}
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/* Check for frequencies we can generate */
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rate = clk_round_rate(s3c_freq->armdiv,
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pos->frequency * 1000);
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rate /= 1000;
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if (rate != pos->frequency) {
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pr_debug("cpufreq: %dkHz unsupported by clock (clk_round_rate return %lu)\n",
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pos->frequency, rate);
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pos->frequency = CPUFREQ_ENTRY_INVALID;
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}
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}
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/* Datasheet says PLL stabalisation time must be at least 300us,
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* so but add some fudge. (reference in LOCKCON0 register description)
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*/
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cpufreq_generic_init(policy, s3c_freq->freq_table,
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(500 * 1000) + s3c_freq->regulator_latency);
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register_reboot_notifier(&s3c2416_cpufreq_reboot_notifier);
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return 0;
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#ifdef CONFIG_ARM_S3C2416_CPUFREQ_VCORESCALE
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err_vddarm:
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clk_put(s3c_freq->armclk);
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#endif
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err_armclk:
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clk_put(s3c_freq->hclk);
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err_hclk:
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clk_put(s3c_freq->armdiv);
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return ret;
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}
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static struct cpufreq_driver s3c2416_cpufreq_driver = {
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.flags = CPUFREQ_NEED_INITIAL_FREQ_CHECK,
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.verify = cpufreq_generic_frequency_table_verify,
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.target_index = s3c2416_cpufreq_set_target,
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.get = s3c2416_cpufreq_get_speed,
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.init = s3c2416_cpufreq_driver_init,
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.name = "s3c2416",
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.attr = cpufreq_generic_attr,
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};
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static int __init s3c2416_cpufreq_init(void)
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{
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return cpufreq_register_driver(&s3c2416_cpufreq_driver);
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}
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module_init(s3c2416_cpufreq_init);
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