WSL2-Linux-Kernel/arch/riscv/boot
Palmer Dabbelt 241527bb84 RISC-V DTS changes for v5.16
Cleanups of RISC-V SiFive and Microchip DTSes with dtschema.  These are
 few minor fixes to make DTSes pass the dtschema, without actual
 functional effect.
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Merge tag 'riscv-sifive-dt-5.16' of git://gitolite.kernel.org/pub/scm/linux/kernel/git/krzk/linux into for-next

RISC-V DTS changes for v5.16

Cleanups of RISC-V SiFive and Microchip DTSes with dtschema.  These are
few minor fixes to make DTSes pass the dtschema, without actual
functional effect.

* tag 'riscv-sifive-dt-5.16' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/krzk/linux:
  riscv: dts: sifive: add missing compatible for plic
  riscv: dts: microchip: add missing compatibles for clint and plic
  riscv: dts: sifive: drop duplicated nodes and properties in sifive
  riscv: dts: sifive: fix Unleashed board compatible
  riscv: dts: sifive: use only generic JEDEC SPI NOR flash compatible
2021-10-21 08:22:37 -07:00
..
dts RISC-V DTS changes for v5.16 2021-10-21 08:22:37 -07:00
.gitignore riscv: Ignore Image.* and loader.bin 2020-11-09 11:54:46 -08:00
Makefile riscv: move the (z)install rules to arch/riscv/Makefile 2021-09-10 23:08:26 -07:00
install.sh RISC-V: Build flat and compressed kernel images 2018-11-20 05:19:09 -08:00
loader.S riscv: provide a flat image loader 2019-11-17 15:17:39 -08:00
loader.lds.S riscv: Move kernel mapping outside of linear mapping 2021-04-26 08:25:04 -07:00