867 строки
20 KiB
ArmAsm
867 строки
20 KiB
ArmAsm
/*
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* Low-level exception handling code
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*
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* Copyright (C) 2012 ARM Ltd.
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* Authors: Catalin Marinas <catalin.marinas@arm.com>
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* Will Deacon <will.deacon@arm.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <linux/init.h>
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#include <linux/linkage.h>
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#include <asm/alternative.h>
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#include <asm/assembler.h>
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#include <asm/asm-offsets.h>
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#include <asm/cpufeature.h>
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#include <asm/errno.h>
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#include <asm/esr.h>
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#include <asm/irq.h>
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#include <asm/memory.h>
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#include <asm/ptrace.h>
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#include <asm/thread_info.h>
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#include <asm/asm-uaccess.h>
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#include <asm/unistd.h>
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/*
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* Context tracking subsystem. Used to instrument transitions
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* between user and kernel mode.
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*/
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.macro ct_user_exit, syscall = 0
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#ifdef CONFIG_CONTEXT_TRACKING
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bl context_tracking_user_exit
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.if \syscall == 1
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/*
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* Save/restore needed during syscalls. Restore syscall arguments from
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* the values already saved on stack during kernel_entry.
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*/
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ldp x0, x1, [sp]
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ldp x2, x3, [sp, #S_X2]
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ldp x4, x5, [sp, #S_X4]
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ldp x6, x7, [sp, #S_X6]
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.endif
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#endif
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.endm
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.macro ct_user_enter
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#ifdef CONFIG_CONTEXT_TRACKING
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bl context_tracking_user_enter
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#endif
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.endm
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/*
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* Bad Abort numbers
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*-----------------
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*/
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#define BAD_SYNC 0
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#define BAD_IRQ 1
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#define BAD_FIQ 2
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#define BAD_ERROR 3
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.macro kernel_entry, el, regsize = 64
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sub sp, sp, #S_FRAME_SIZE
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.if \regsize == 32
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mov w0, w0 // zero upper 32 bits of x0
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.endif
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stp x0, x1, [sp, #16 * 0]
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stp x2, x3, [sp, #16 * 1]
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stp x4, x5, [sp, #16 * 2]
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stp x6, x7, [sp, #16 * 3]
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stp x8, x9, [sp, #16 * 4]
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stp x10, x11, [sp, #16 * 5]
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stp x12, x13, [sp, #16 * 6]
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stp x14, x15, [sp, #16 * 7]
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stp x16, x17, [sp, #16 * 8]
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stp x18, x19, [sp, #16 * 9]
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stp x20, x21, [sp, #16 * 10]
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stp x22, x23, [sp, #16 * 11]
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stp x24, x25, [sp, #16 * 12]
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stp x26, x27, [sp, #16 * 13]
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stp x28, x29, [sp, #16 * 14]
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.if \el == 0
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mrs x21, sp_el0
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ldr_this_cpu tsk, __entry_task, x20 // Ensure MDSCR_EL1.SS is clear,
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ldr x19, [tsk, #TSK_TI_FLAGS] // since we can unmask debug
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disable_step_tsk x19, x20 // exceptions when scheduling.
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mov x29, xzr // fp pointed to user-space
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.else
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add x21, sp, #S_FRAME_SIZE
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get_thread_info tsk
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/* Save the task's original addr_limit and set USER_DS (TASK_SIZE_64) */
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ldr x20, [tsk, #TSK_TI_ADDR_LIMIT]
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str x20, [sp, #S_ORIG_ADDR_LIMIT]
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mov x20, #TASK_SIZE_64
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str x20, [tsk, #TSK_TI_ADDR_LIMIT]
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/* No need to reset PSTATE.UAO, hardware's already set it to 0 for us */
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.endif /* \el == 0 */
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mrs x22, elr_el1
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mrs x23, spsr_el1
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stp lr, x21, [sp, #S_LR]
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#ifdef CONFIG_ARM64_SW_TTBR0_PAN
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/*
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* Set the TTBR0 PAN bit in SPSR. When the exception is taken from
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* EL0, there is no need to check the state of TTBR0_EL1 since
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* accesses are always enabled.
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* Note that the meaning of this bit differs from the ARMv8.1 PAN
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* feature as all TTBR0_EL1 accesses are disabled, not just those to
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* user mappings.
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*/
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alternative_if ARM64_HAS_PAN
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b 1f // skip TTBR0 PAN
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alternative_else_nop_endif
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.if \el != 0
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mrs x21, ttbr0_el1
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tst x21, #0xffff << 48 // Check for the reserved ASID
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orr x23, x23, #PSR_PAN_BIT // Set the emulated PAN in the saved SPSR
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b.eq 1f // TTBR0 access already disabled
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and x23, x23, #~PSR_PAN_BIT // Clear the emulated PAN in the saved SPSR
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.endif
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__uaccess_ttbr0_disable x21
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1:
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#endif
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stp x22, x23, [sp, #S_PC]
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/*
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* Set syscallno to -1 by default (overridden later if real syscall).
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*/
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.if \el == 0
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mvn x21, xzr
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str x21, [sp, #S_SYSCALLNO]
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.endif
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/*
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* Set sp_el0 to current thread_info.
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*/
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.if \el == 0
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msr sp_el0, tsk
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.endif
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/*
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* Registers that may be useful after this macro is invoked:
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*
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* x21 - aborted SP
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* x22 - aborted PC
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* x23 - aborted PSTATE
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*/
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.endm
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.macro kernel_exit, el
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.if \el != 0
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/* Restore the task's original addr_limit. */
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ldr x20, [sp, #S_ORIG_ADDR_LIMIT]
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str x20, [tsk, #TSK_TI_ADDR_LIMIT]
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/* No need to restore UAO, it will be restored from SPSR_EL1 */
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.endif
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ldp x21, x22, [sp, #S_PC] // load ELR, SPSR
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.if \el == 0
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ct_user_enter
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.endif
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#ifdef CONFIG_ARM64_SW_TTBR0_PAN
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/*
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* Restore access to TTBR0_EL1. If returning to EL0, no need for SPSR
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* PAN bit checking.
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*/
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alternative_if ARM64_HAS_PAN
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b 2f // skip TTBR0 PAN
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alternative_else_nop_endif
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.if \el != 0
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tbnz x22, #22, 1f // Skip re-enabling TTBR0 access if the PSR_PAN_BIT is set
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.endif
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__uaccess_ttbr0_enable x0
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.if \el == 0
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/*
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* Enable errata workarounds only if returning to user. The only
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* workaround currently required for TTBR0_EL1 changes are for the
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* Cavium erratum 27456 (broadcast TLBI instructions may cause I-cache
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* corruption).
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*/
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post_ttbr0_update_workaround
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.endif
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1:
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.if \el != 0
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and x22, x22, #~PSR_PAN_BIT // ARMv8.0 CPUs do not understand this bit
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.endif
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2:
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#endif
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.if \el == 0
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ldr x23, [sp, #S_SP] // load return stack pointer
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msr sp_el0, x23
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#ifdef CONFIG_ARM64_ERRATUM_845719
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alternative_if ARM64_WORKAROUND_845719
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tbz x22, #4, 1f
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#ifdef CONFIG_PID_IN_CONTEXTIDR
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mrs x29, contextidr_el1
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msr contextidr_el1, x29
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#else
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msr contextidr_el1, xzr
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#endif
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1:
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alternative_else_nop_endif
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#endif
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.endif
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msr elr_el1, x21 // set up the return data
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msr spsr_el1, x22
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ldp x0, x1, [sp, #16 * 0]
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ldp x2, x3, [sp, #16 * 1]
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ldp x4, x5, [sp, #16 * 2]
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ldp x6, x7, [sp, #16 * 3]
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ldp x8, x9, [sp, #16 * 4]
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ldp x10, x11, [sp, #16 * 5]
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ldp x12, x13, [sp, #16 * 6]
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ldp x14, x15, [sp, #16 * 7]
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ldp x16, x17, [sp, #16 * 8]
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ldp x18, x19, [sp, #16 * 9]
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ldp x20, x21, [sp, #16 * 10]
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ldp x22, x23, [sp, #16 * 11]
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ldp x24, x25, [sp, #16 * 12]
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ldp x26, x27, [sp, #16 * 13]
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ldp x28, x29, [sp, #16 * 14]
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ldr lr, [sp, #S_LR]
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add sp, sp, #S_FRAME_SIZE // restore sp
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eret // return to kernel
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.endm
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.macro irq_stack_entry
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mov x19, sp // preserve the original sp
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/*
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* Compare sp with the base of the task stack.
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* If the top ~(THREAD_SIZE - 1) bits match, we are on a task stack,
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* and should switch to the irq stack.
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*/
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ldr x25, [tsk, TSK_STACK]
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eor x25, x25, x19
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and x25, x25, #~(THREAD_SIZE - 1)
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cbnz x25, 9998f
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adr_this_cpu x25, irq_stack, x26
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mov x26, #IRQ_STACK_START_SP
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add x26, x25, x26
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/* switch to the irq stack */
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mov sp, x26
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/*
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* Add a dummy stack frame, this non-standard format is fixed up
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* by unwind_frame()
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*/
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stp x29, x19, [sp, #-16]!
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mov x29, sp
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9998:
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.endm
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/*
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* x19 should be preserved between irq_stack_entry and
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* irq_stack_exit.
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*/
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.macro irq_stack_exit
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mov sp, x19
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.endm
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/*
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* These are the registers used in the syscall handler, and allow us to
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* have in theory up to 7 arguments to a function - x0 to x6.
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*
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* x7 is reserved for the system call number in 32-bit mode.
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*/
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sc_nr .req x25 // number of system calls
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scno .req x26 // syscall number
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stbl .req x27 // syscall table pointer
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tsk .req x28 // current thread_info
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/*
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* Interrupt handling.
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*/
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.macro irq_handler
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ldr_l x1, handle_arch_irq
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mov x0, sp
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irq_stack_entry
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blr x1
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irq_stack_exit
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.endm
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.text
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/*
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* Exception vectors.
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*/
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.pushsection ".entry.text", "ax"
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.align 11
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ENTRY(vectors)
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ventry el1_sync_invalid // Synchronous EL1t
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ventry el1_irq_invalid // IRQ EL1t
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ventry el1_fiq_invalid // FIQ EL1t
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ventry el1_error_invalid // Error EL1t
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ventry el1_sync // Synchronous EL1h
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ventry el1_irq // IRQ EL1h
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ventry el1_fiq_invalid // FIQ EL1h
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ventry el1_error_invalid // Error EL1h
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ventry el0_sync // Synchronous 64-bit EL0
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ventry el0_irq // IRQ 64-bit EL0
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ventry el0_fiq_invalid // FIQ 64-bit EL0
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ventry el0_error_invalid // Error 64-bit EL0
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#ifdef CONFIG_COMPAT
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ventry el0_sync_compat // Synchronous 32-bit EL0
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ventry el0_irq_compat // IRQ 32-bit EL0
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ventry el0_fiq_invalid_compat // FIQ 32-bit EL0
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ventry el0_error_invalid_compat // Error 32-bit EL0
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#else
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ventry el0_sync_invalid // Synchronous 32-bit EL0
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ventry el0_irq_invalid // IRQ 32-bit EL0
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ventry el0_fiq_invalid // FIQ 32-bit EL0
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ventry el0_error_invalid // Error 32-bit EL0
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#endif
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END(vectors)
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/*
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* Invalid mode handlers
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*/
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.macro inv_entry, el, reason, regsize = 64
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kernel_entry \el, \regsize
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mov x0, sp
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mov x1, #\reason
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mrs x2, esr_el1
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b bad_mode
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.endm
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el0_sync_invalid:
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inv_entry 0, BAD_SYNC
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ENDPROC(el0_sync_invalid)
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el0_irq_invalid:
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inv_entry 0, BAD_IRQ
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ENDPROC(el0_irq_invalid)
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el0_fiq_invalid:
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inv_entry 0, BAD_FIQ
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ENDPROC(el0_fiq_invalid)
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el0_error_invalid:
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inv_entry 0, BAD_ERROR
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ENDPROC(el0_error_invalid)
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#ifdef CONFIG_COMPAT
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el0_fiq_invalid_compat:
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inv_entry 0, BAD_FIQ, 32
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ENDPROC(el0_fiq_invalid_compat)
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el0_error_invalid_compat:
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inv_entry 0, BAD_ERROR, 32
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ENDPROC(el0_error_invalid_compat)
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#endif
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el1_sync_invalid:
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inv_entry 1, BAD_SYNC
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ENDPROC(el1_sync_invalid)
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el1_irq_invalid:
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inv_entry 1, BAD_IRQ
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ENDPROC(el1_irq_invalid)
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el1_fiq_invalid:
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inv_entry 1, BAD_FIQ
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ENDPROC(el1_fiq_invalid)
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el1_error_invalid:
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inv_entry 1, BAD_ERROR
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ENDPROC(el1_error_invalid)
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/*
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* EL1 mode handlers.
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*/
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.align 6
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el1_sync:
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kernel_entry 1
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mrs x1, esr_el1 // read the syndrome register
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lsr x24, x1, #ESR_ELx_EC_SHIFT // exception class
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cmp x24, #ESR_ELx_EC_DABT_CUR // data abort in EL1
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b.eq el1_da
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cmp x24, #ESR_ELx_EC_IABT_CUR // instruction abort in EL1
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b.eq el1_ia
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cmp x24, #ESR_ELx_EC_SYS64 // configurable trap
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b.eq el1_undef
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cmp x24, #ESR_ELx_EC_SP_ALIGN // stack alignment exception
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b.eq el1_sp_pc
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cmp x24, #ESR_ELx_EC_PC_ALIGN // pc alignment exception
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b.eq el1_sp_pc
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cmp x24, #ESR_ELx_EC_UNKNOWN // unknown exception in EL1
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b.eq el1_undef
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cmp x24, #ESR_ELx_EC_BREAKPT_CUR // debug exception in EL1
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b.ge el1_dbg
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b el1_inv
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el1_ia:
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/*
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* Fall through to the Data abort case
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*/
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el1_da:
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/*
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* Data abort handling
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*/
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mrs x0, far_el1
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enable_dbg
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// re-enable interrupts if they were enabled in the aborted context
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tbnz x23, #7, 1f // PSR_I_BIT
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enable_irq
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1:
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mov x2, sp // struct pt_regs
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bl do_mem_abort
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// disable interrupts before pulling preserved data off the stack
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disable_irq
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kernel_exit 1
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el1_sp_pc:
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/*
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* Stack or PC alignment exception handling
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*/
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mrs x0, far_el1
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enable_dbg
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mov x2, sp
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b do_sp_pc_abort
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el1_undef:
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/*
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* Undefined instruction
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*/
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enable_dbg
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mov x0, sp
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b do_undefinstr
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el1_dbg:
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/*
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* Debug exception handling
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*/
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cmp x24, #ESR_ELx_EC_BRK64 // if BRK64
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cinc x24, x24, eq // set bit '0'
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tbz x24, #0, el1_inv // EL1 only
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mrs x0, far_el1
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mov x2, sp // struct pt_regs
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bl do_debug_exception
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kernel_exit 1
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el1_inv:
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// TODO: add support for undefined instructions in kernel mode
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enable_dbg
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mov x0, sp
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mov x2, x1
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mov x1, #BAD_SYNC
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b bad_mode
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ENDPROC(el1_sync)
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.align 6
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el1_irq:
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kernel_entry 1
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enable_dbg
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#ifdef CONFIG_TRACE_IRQFLAGS
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bl trace_hardirqs_off
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#endif
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irq_handler
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#ifdef CONFIG_PREEMPT
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ldr w24, [tsk, #TSK_TI_PREEMPT] // get preempt count
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cbnz w24, 1f // preempt count != 0
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ldr x0, [tsk, #TSK_TI_FLAGS] // get flags
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tbz x0, #TIF_NEED_RESCHED, 1f // needs rescheduling?
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bl el1_preempt
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1:
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#endif
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#ifdef CONFIG_TRACE_IRQFLAGS
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bl trace_hardirqs_on
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#endif
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kernel_exit 1
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ENDPROC(el1_irq)
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#ifdef CONFIG_PREEMPT
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el1_preempt:
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mov x24, lr
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1: bl preempt_schedule_irq // irq en/disable is done inside
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ldr x0, [tsk, #TSK_TI_FLAGS] // get new tasks TI_FLAGS
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tbnz x0, #TIF_NEED_RESCHED, 1b // needs rescheduling?
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ret x24
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#endif
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|
|
|
/*
|
|
* EL0 mode handlers.
|
|
*/
|
|
.align 6
|
|
el0_sync:
|
|
kernel_entry 0
|
|
mrs x25, esr_el1 // read the syndrome register
|
|
lsr x24, x25, #ESR_ELx_EC_SHIFT // exception class
|
|
cmp x24, #ESR_ELx_EC_SVC64 // SVC in 64-bit state
|
|
b.eq el0_svc
|
|
cmp x24, #ESR_ELx_EC_DABT_LOW // data abort in EL0
|
|
b.eq el0_da
|
|
cmp x24, #ESR_ELx_EC_IABT_LOW // instruction abort in EL0
|
|
b.eq el0_ia
|
|
cmp x24, #ESR_ELx_EC_FP_ASIMD // FP/ASIMD access
|
|
b.eq el0_fpsimd_acc
|
|
cmp x24, #ESR_ELx_EC_FP_EXC64 // FP/ASIMD exception
|
|
b.eq el0_fpsimd_exc
|
|
cmp x24, #ESR_ELx_EC_SYS64 // configurable trap
|
|
b.eq el0_sys
|
|
cmp x24, #ESR_ELx_EC_SP_ALIGN // stack alignment exception
|
|
b.eq el0_sp_pc
|
|
cmp x24, #ESR_ELx_EC_PC_ALIGN // pc alignment exception
|
|
b.eq el0_sp_pc
|
|
cmp x24, #ESR_ELx_EC_UNKNOWN // unknown exception in EL0
|
|
b.eq el0_undef
|
|
cmp x24, #ESR_ELx_EC_BREAKPT_LOW // debug exception in EL0
|
|
b.ge el0_dbg
|
|
b el0_inv
|
|
|
|
#ifdef CONFIG_COMPAT
|
|
.align 6
|
|
el0_sync_compat:
|
|
kernel_entry 0, 32
|
|
mrs x25, esr_el1 // read the syndrome register
|
|
lsr x24, x25, #ESR_ELx_EC_SHIFT // exception class
|
|
cmp x24, #ESR_ELx_EC_SVC32 // SVC in 32-bit state
|
|
b.eq el0_svc_compat
|
|
cmp x24, #ESR_ELx_EC_DABT_LOW // data abort in EL0
|
|
b.eq el0_da
|
|
cmp x24, #ESR_ELx_EC_IABT_LOW // instruction abort in EL0
|
|
b.eq el0_ia
|
|
cmp x24, #ESR_ELx_EC_FP_ASIMD // FP/ASIMD access
|
|
b.eq el0_fpsimd_acc
|
|
cmp x24, #ESR_ELx_EC_FP_EXC32 // FP/ASIMD exception
|
|
b.eq el0_fpsimd_exc
|
|
cmp x24, #ESR_ELx_EC_PC_ALIGN // pc alignment exception
|
|
b.eq el0_sp_pc
|
|
cmp x24, #ESR_ELx_EC_UNKNOWN // unknown exception in EL0
|
|
b.eq el0_undef
|
|
cmp x24, #ESR_ELx_EC_CP15_32 // CP15 MRC/MCR trap
|
|
b.eq el0_undef
|
|
cmp x24, #ESR_ELx_EC_CP15_64 // CP15 MRRC/MCRR trap
|
|
b.eq el0_undef
|
|
cmp x24, #ESR_ELx_EC_CP14_MR // CP14 MRC/MCR trap
|
|
b.eq el0_undef
|
|
cmp x24, #ESR_ELx_EC_CP14_LS // CP14 LDC/STC trap
|
|
b.eq el0_undef
|
|
cmp x24, #ESR_ELx_EC_CP14_64 // CP14 MRRC/MCRR trap
|
|
b.eq el0_undef
|
|
cmp x24, #ESR_ELx_EC_BREAKPT_LOW // debug exception in EL0
|
|
b.ge el0_dbg
|
|
b el0_inv
|
|
el0_svc_compat:
|
|
/*
|
|
* AArch32 syscall handling
|
|
*/
|
|
adrp stbl, compat_sys_call_table // load compat syscall table pointer
|
|
uxtw scno, w7 // syscall number in w7 (r7)
|
|
mov sc_nr, #__NR_compat_syscalls
|
|
b el0_svc_naked
|
|
|
|
.align 6
|
|
el0_irq_compat:
|
|
kernel_entry 0, 32
|
|
b el0_irq_naked
|
|
#endif
|
|
|
|
el0_da:
|
|
/*
|
|
* Data abort handling
|
|
*/
|
|
mrs x26, far_el1
|
|
// enable interrupts before calling the main handler
|
|
enable_dbg_and_irq
|
|
ct_user_exit
|
|
bic x0, x26, #(0xff << 56)
|
|
mov x1, x25
|
|
mov x2, sp
|
|
bl do_mem_abort
|
|
b ret_to_user
|
|
el0_ia:
|
|
/*
|
|
* Instruction abort handling
|
|
*/
|
|
mrs x26, far_el1
|
|
// enable interrupts before calling the main handler
|
|
enable_dbg_and_irq
|
|
ct_user_exit
|
|
mov x0, x26
|
|
mov x1, x25
|
|
mov x2, sp
|
|
bl do_mem_abort
|
|
b ret_to_user
|
|
el0_fpsimd_acc:
|
|
/*
|
|
* Floating Point or Advanced SIMD access
|
|
*/
|
|
enable_dbg
|
|
ct_user_exit
|
|
mov x0, x25
|
|
mov x1, sp
|
|
bl do_fpsimd_acc
|
|
b ret_to_user
|
|
el0_fpsimd_exc:
|
|
/*
|
|
* Floating Point or Advanced SIMD exception
|
|
*/
|
|
enable_dbg
|
|
ct_user_exit
|
|
mov x0, x25
|
|
mov x1, sp
|
|
bl do_fpsimd_exc
|
|
b ret_to_user
|
|
el0_sp_pc:
|
|
/*
|
|
* Stack or PC alignment exception handling
|
|
*/
|
|
mrs x26, far_el1
|
|
// enable interrupts before calling the main handler
|
|
enable_dbg_and_irq
|
|
ct_user_exit
|
|
mov x0, x26
|
|
mov x1, x25
|
|
mov x2, sp
|
|
bl do_sp_pc_abort
|
|
b ret_to_user
|
|
el0_undef:
|
|
/*
|
|
* Undefined instruction
|
|
*/
|
|
// enable interrupts before calling the main handler
|
|
enable_dbg_and_irq
|
|
ct_user_exit
|
|
mov x0, sp
|
|
bl do_undefinstr
|
|
b ret_to_user
|
|
el0_sys:
|
|
/*
|
|
* System instructions, for trapped cache maintenance instructions
|
|
*/
|
|
enable_dbg_and_irq
|
|
ct_user_exit
|
|
mov x0, x25
|
|
mov x1, sp
|
|
bl do_sysinstr
|
|
b ret_to_user
|
|
el0_dbg:
|
|
/*
|
|
* Debug exception handling
|
|
*/
|
|
tbnz x24, #0, el0_inv // EL0 only
|
|
mrs x0, far_el1
|
|
mov x1, x25
|
|
mov x2, sp
|
|
bl do_debug_exception
|
|
enable_dbg
|
|
ct_user_exit
|
|
b ret_to_user
|
|
el0_inv:
|
|
enable_dbg
|
|
ct_user_exit
|
|
mov x0, sp
|
|
mov x1, #BAD_SYNC
|
|
mov x2, x25
|
|
bl bad_el0_sync
|
|
b ret_to_user
|
|
ENDPROC(el0_sync)
|
|
|
|
.align 6
|
|
el0_irq:
|
|
kernel_entry 0
|
|
el0_irq_naked:
|
|
enable_dbg
|
|
#ifdef CONFIG_TRACE_IRQFLAGS
|
|
bl trace_hardirqs_off
|
|
#endif
|
|
|
|
ct_user_exit
|
|
irq_handler
|
|
|
|
#ifdef CONFIG_TRACE_IRQFLAGS
|
|
bl trace_hardirqs_on
|
|
#endif
|
|
b ret_to_user
|
|
ENDPROC(el0_irq)
|
|
|
|
/*
|
|
* Register switch for AArch64. The callee-saved registers need to be saved
|
|
* and restored. On entry:
|
|
* x0 = previous task_struct (must be preserved across the switch)
|
|
* x1 = next task_struct
|
|
* Previous and next are guaranteed not to be the same.
|
|
*
|
|
*/
|
|
ENTRY(cpu_switch_to)
|
|
mov x10, #THREAD_CPU_CONTEXT
|
|
add x8, x0, x10
|
|
mov x9, sp
|
|
stp x19, x20, [x8], #16 // store callee-saved registers
|
|
stp x21, x22, [x8], #16
|
|
stp x23, x24, [x8], #16
|
|
stp x25, x26, [x8], #16
|
|
stp x27, x28, [x8], #16
|
|
stp x29, x9, [x8], #16
|
|
str lr, [x8]
|
|
add x8, x1, x10
|
|
ldp x19, x20, [x8], #16 // restore callee-saved registers
|
|
ldp x21, x22, [x8], #16
|
|
ldp x23, x24, [x8], #16
|
|
ldp x25, x26, [x8], #16
|
|
ldp x27, x28, [x8], #16
|
|
ldp x29, x9, [x8], #16
|
|
ldr lr, [x8]
|
|
mov sp, x9
|
|
msr sp_el0, x1
|
|
ret
|
|
ENDPROC(cpu_switch_to)
|
|
|
|
/*
|
|
* This is the fast syscall return path. We do as little as possible here,
|
|
* and this includes saving x0 back into the kernel stack.
|
|
*/
|
|
ret_fast_syscall:
|
|
disable_irq // disable interrupts
|
|
str x0, [sp, #S_X0] // returned x0
|
|
ldr x1, [tsk, #TSK_TI_FLAGS] // re-check for syscall tracing
|
|
and x2, x1, #_TIF_SYSCALL_WORK
|
|
cbnz x2, ret_fast_syscall_trace
|
|
and x2, x1, #_TIF_WORK_MASK
|
|
cbnz x2, work_pending
|
|
enable_step_tsk x1, x2
|
|
kernel_exit 0
|
|
ret_fast_syscall_trace:
|
|
enable_irq // enable interrupts
|
|
b __sys_trace_return_skipped // we already saved x0
|
|
|
|
/*
|
|
* Ok, we need to do extra processing, enter the slow path.
|
|
*/
|
|
work_pending:
|
|
mov x0, sp // 'regs'
|
|
bl do_notify_resume
|
|
#ifdef CONFIG_TRACE_IRQFLAGS
|
|
bl trace_hardirqs_on // enabled while in userspace
|
|
#endif
|
|
ldr x1, [tsk, #TSK_TI_FLAGS] // re-check for single-step
|
|
b finish_ret_to_user
|
|
/*
|
|
* "slow" syscall return path.
|
|
*/
|
|
ret_to_user:
|
|
disable_irq // disable interrupts
|
|
ldr x1, [tsk, #TSK_TI_FLAGS]
|
|
and x2, x1, #_TIF_WORK_MASK
|
|
cbnz x2, work_pending
|
|
finish_ret_to_user:
|
|
enable_step_tsk x1, x2
|
|
kernel_exit 0
|
|
ENDPROC(ret_to_user)
|
|
|
|
/*
|
|
* This is how we return from a fork.
|
|
*/
|
|
ENTRY(ret_from_fork)
|
|
bl schedule_tail
|
|
cbz x19, 1f // not a kernel thread
|
|
mov x0, x20
|
|
blr x19
|
|
1: get_thread_info tsk
|
|
b ret_to_user
|
|
ENDPROC(ret_from_fork)
|
|
|
|
/*
|
|
* SVC handler.
|
|
*/
|
|
.align 6
|
|
el0_svc:
|
|
adrp stbl, sys_call_table // load syscall table pointer
|
|
uxtw scno, w8 // syscall number in w8
|
|
mov sc_nr, #__NR_syscalls
|
|
el0_svc_naked: // compat entry point
|
|
stp x0, scno, [sp, #S_ORIG_X0] // save the original x0 and syscall number
|
|
enable_dbg_and_irq
|
|
ct_user_exit 1
|
|
|
|
ldr x16, [tsk, #TSK_TI_FLAGS] // check for syscall hooks
|
|
tst x16, #_TIF_SYSCALL_WORK
|
|
b.ne __sys_trace
|
|
cmp scno, sc_nr // check upper syscall limit
|
|
b.hs ni_sys
|
|
ldr x16, [stbl, scno, lsl #3] // address in the syscall table
|
|
blr x16 // call sys_* routine
|
|
b ret_fast_syscall
|
|
ni_sys:
|
|
mov x0, sp
|
|
bl do_ni_syscall
|
|
b ret_fast_syscall
|
|
ENDPROC(el0_svc)
|
|
|
|
/*
|
|
* This is the really slow path. We're going to be doing context
|
|
* switches, and waiting for our parent to respond.
|
|
*/
|
|
__sys_trace:
|
|
mov w0, #-1 // set default errno for
|
|
cmp scno, x0 // user-issued syscall(-1)
|
|
b.ne 1f
|
|
mov x0, #-ENOSYS
|
|
str x0, [sp, #S_X0]
|
|
1: mov x0, sp
|
|
bl syscall_trace_enter
|
|
cmp w0, #-1 // skip the syscall?
|
|
b.eq __sys_trace_return_skipped
|
|
uxtw scno, w0 // syscall number (possibly new)
|
|
mov x1, sp // pointer to regs
|
|
cmp scno, sc_nr // check upper syscall limit
|
|
b.hs __ni_sys_trace
|
|
ldp x0, x1, [sp] // restore the syscall args
|
|
ldp x2, x3, [sp, #S_X2]
|
|
ldp x4, x5, [sp, #S_X4]
|
|
ldp x6, x7, [sp, #S_X6]
|
|
ldr x16, [stbl, scno, lsl #3] // address in the syscall table
|
|
blr x16 // call sys_* routine
|
|
|
|
__sys_trace_return:
|
|
str x0, [sp, #S_X0] // save returned x0
|
|
__sys_trace_return_skipped:
|
|
mov x0, sp
|
|
bl syscall_trace_exit
|
|
b ret_to_user
|
|
|
|
__ni_sys_trace:
|
|
mov x0, sp
|
|
bl do_ni_syscall
|
|
b __sys_trace_return
|
|
|
|
.popsection // .entry.text
|
|
|
|
/*
|
|
* Special system call wrappers.
|
|
*/
|
|
ENTRY(sys_rt_sigreturn_wrapper)
|
|
mov x0, sp
|
|
b sys_rt_sigreturn
|
|
ENDPROC(sys_rt_sigreturn_wrapper)
|