440 строки
11 KiB
C
440 строки
11 KiB
C
/*
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* net/dsa/mv88e6131.c - Marvell 88e6095/6095f/6131 switch chip support
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* Copyright (c) 2008-2009 Marvell Semiconductor
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*/
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#include <linux/list.h>
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#include <linux/netdevice.h>
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#include <linux/phy.h>
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#include "dsa_priv.h"
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#include "mv88e6xxx.h"
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/*
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* Switch product IDs
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*/
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#define ID_6085 0x04a0
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#define ID_6095 0x0950
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#define ID_6131 0x1060
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static char *mv88e6131_probe(struct mii_bus *bus, int sw_addr)
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{
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int ret;
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ret = __mv88e6xxx_reg_read(bus, sw_addr, REG_PORT(0), 0x03);
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if (ret >= 0) {
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ret &= 0xfff0;
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if (ret == ID_6085)
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return "Marvell 88E6085";
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if (ret == ID_6095)
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return "Marvell 88E6095/88E6095F";
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if (ret == ID_6131)
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return "Marvell 88E6131";
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}
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return NULL;
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}
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static int mv88e6131_switch_reset(struct dsa_switch *ds)
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{
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int i;
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int ret;
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/*
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* Set all ports to the disabled state.
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*/
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for (i = 0; i < 11; i++) {
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ret = REG_READ(REG_PORT(i), 0x04);
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REG_WRITE(REG_PORT(i), 0x04, ret & 0xfffc);
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}
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/*
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* Wait for transmit queues to drain.
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*/
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msleep(2);
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/*
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* Reset the switch.
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*/
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REG_WRITE(REG_GLOBAL, 0x04, 0xc400);
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/*
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* Wait up to one second for reset to complete.
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*/
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for (i = 0; i < 1000; i++) {
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ret = REG_READ(REG_GLOBAL, 0x00);
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if ((ret & 0xc800) == 0xc800)
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break;
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msleep(1);
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}
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if (i == 1000)
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return -ETIMEDOUT;
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return 0;
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}
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static int mv88e6131_setup_global(struct dsa_switch *ds)
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{
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int ret;
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int i;
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/*
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* Enable the PHY polling unit, don't discard packets with
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* excessive collisions, use a weighted fair queueing scheme
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* to arbitrate between packet queues, set the maximum frame
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* size to 1632, and mask all interrupt sources.
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*/
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REG_WRITE(REG_GLOBAL, 0x04, 0x4400);
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/*
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* Set the default address aging time to 5 minutes, and
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* enable address learn messages to be sent to all message
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* ports.
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*/
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REG_WRITE(REG_GLOBAL, 0x0a, 0x0148);
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/*
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* Configure the priority mapping registers.
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*/
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ret = mv88e6xxx_config_prio(ds);
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if (ret < 0)
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return ret;
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/*
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* Set the VLAN ethertype to 0x8100.
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*/
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REG_WRITE(REG_GLOBAL, 0x19, 0x8100);
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/*
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* Disable ARP mirroring, and configure the upstream port as
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* the port to which ingress and egress monitor frames are to
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* be sent.
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*/
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REG_WRITE(REG_GLOBAL, 0x1a, (dsa_upstream_port(ds) * 0x1100) | 0x00f0);
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/*
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* Disable cascade port functionality, and set the switch's
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* DSA device number.
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*/
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REG_WRITE(REG_GLOBAL, 0x1c, 0xe000 | (ds->index & 0x1f));
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/*
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* Send all frames with destination addresses matching
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* 01:80:c2:00:00:0x to the CPU port.
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*/
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REG_WRITE(REG_GLOBAL2, 0x03, 0xffff);
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/*
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* Ignore removed tag data on doubly tagged packets, disable
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* flow control messages, force flow control priority to the
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* highest, and send all special multicast frames to the CPU
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* port at the highest priority.
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*/
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REG_WRITE(REG_GLOBAL2, 0x05, 0x00ff);
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/*
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* Program the DSA routing table.
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*/
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for (i = 0; i < 32; i++) {
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int nexthop;
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nexthop = 0x1f;
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if (i != ds->index && i < ds->dst->pd->nr_chips)
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nexthop = ds->pd->rtable[i] & 0x1f;
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REG_WRITE(REG_GLOBAL2, 0x06, 0x8000 | (i << 8) | nexthop);
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}
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/*
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* Clear all trunk masks.
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*/
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for (i = 0; i < 8; i++)
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REG_WRITE(REG_GLOBAL2, 0x07, 0x8000 | (i << 12) | 0x7ff);
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/*
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* Clear all trunk mappings.
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*/
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for (i = 0; i < 16; i++)
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REG_WRITE(REG_GLOBAL2, 0x08, 0x8000 | (i << 11));
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/*
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* Force the priority of IGMP/MLD snoop frames and ARP frames
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* to the highest setting.
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*/
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REG_WRITE(REG_GLOBAL2, 0x0f, 0x00ff);
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return 0;
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}
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static int mv88e6131_setup_port(struct dsa_switch *ds, int p)
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{
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struct mv88e6xxx_priv_state *ps = (void *)(ds + 1);
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int addr = REG_PORT(p);
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u16 val;
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/*
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* MAC Forcing register: don't force link, speed, duplex
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* or flow control state to any particular values on physical
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* ports, but force the CPU port and all DSA ports to 1000 Mb/s
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* (100 Mb/s on 6085) full duplex.
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*/
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if (dsa_is_cpu_port(ds, p) || ds->dsa_port_mask & (1 << p))
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if (ps->id == ID_6085)
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REG_WRITE(addr, 0x01, 0x003d); /* 100 Mb/s */
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else
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REG_WRITE(addr, 0x01, 0x003e); /* 1000 Mb/s */
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else
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REG_WRITE(addr, 0x01, 0x0003);
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/*
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* Port Control: disable Core Tag, disable Drop-on-Lock,
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* transmit frames unmodified, disable Header mode,
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* enable IGMP/MLD snoop, disable DoubleTag, disable VLAN
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* tunneling, determine priority by looking at 802.1p and
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* IP priority fields (IP prio has precedence), and set STP
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* state to Forwarding.
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*
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* If this is the upstream port for this switch, enable
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* forwarding of unknown unicasts, and enable DSA tagging
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* mode.
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*
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* If this is the link to another switch, use DSA tagging
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* mode, but do not enable forwarding of unknown unicasts.
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*/
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val = 0x0433;
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if (p == dsa_upstream_port(ds)) {
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val |= 0x0104;
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/*
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* On 6085, unknown multicast forward is controlled
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* here rather than in Port Control 2 register.
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*/
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if (ps->id == ID_6085)
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val |= 0x0008;
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}
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if (ds->dsa_port_mask & (1 << p))
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val |= 0x0100;
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REG_WRITE(addr, 0x04, val);
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/*
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* Port Control 1: disable trunking. Also, if this is the
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* CPU port, enable learn messages to be sent to this port.
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*/
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REG_WRITE(addr, 0x05, dsa_is_cpu_port(ds, p) ? 0x8000 : 0x0000);
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/*
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* Port based VLAN map: give each port its own address
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* database, allow the CPU port to talk to each of the 'real'
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* ports, and allow each of the 'real' ports to only talk to
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* the upstream port.
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*/
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val = (p & 0xf) << 12;
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if (dsa_is_cpu_port(ds, p))
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val |= ds->phys_port_mask;
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else
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val |= 1 << dsa_upstream_port(ds);
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REG_WRITE(addr, 0x06, val);
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/*
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* Default VLAN ID and priority: don't set a default VLAN
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* ID, and set the default packet priority to zero.
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*/
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REG_WRITE(addr, 0x07, 0x0000);
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/*
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* Port Control 2: don't force a good FCS, don't use
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* VLAN-based, source address-based or destination
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* address-based priority overrides, don't let the switch
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* add or strip 802.1q tags, don't discard tagged or
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* untagged frames on this port, do a destination address
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* lookup on received packets as usual, don't send a copy
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* of all transmitted/received frames on this port to the
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* CPU, and configure the upstream port number.
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*
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* If this is the upstream port for this switch, enable
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* forwarding of unknown multicast addresses.
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*/
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if (ps->id == ID_6085)
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/*
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* on 6085, bits 3:0 are reserved, bit 6 control ARP
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* mirroring, and multicast forward is handled in
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* Port Control register.
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*/
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REG_WRITE(addr, 0x08, 0x0080);
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else {
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val = 0x0080 | dsa_upstream_port(ds);
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if (p == dsa_upstream_port(ds))
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val |= 0x0040;
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REG_WRITE(addr, 0x08, val);
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}
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/*
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* Rate Control: disable ingress rate limiting.
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*/
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REG_WRITE(addr, 0x09, 0x0000);
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/*
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* Rate Control 2: disable egress rate limiting.
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*/
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REG_WRITE(addr, 0x0a, 0x0000);
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/*
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* Port Association Vector: when learning source addresses
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* of packets, add the address to the address database using
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* a port bitmap that has only the bit for this port set and
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* the other bits clear.
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*/
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REG_WRITE(addr, 0x0b, 1 << p);
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/*
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* Tag Remap: use an identity 802.1p prio -> switch prio
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* mapping.
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*/
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REG_WRITE(addr, 0x18, 0x3210);
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/*
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* Tag Remap 2: use an identity 802.1p prio -> switch prio
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* mapping.
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*/
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REG_WRITE(addr, 0x19, 0x7654);
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return 0;
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}
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static int mv88e6131_setup(struct dsa_switch *ds)
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{
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struct mv88e6xxx_priv_state *ps = (void *)(ds + 1);
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int i;
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int ret;
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mutex_init(&ps->smi_mutex);
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mv88e6xxx_ppu_state_init(ds);
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mutex_init(&ps->stats_mutex);
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ps->id = REG_READ(REG_PORT(0), 0x03) & 0xfff0;
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ret = mv88e6131_switch_reset(ds);
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if (ret < 0)
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return ret;
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/* @@@ initialise vtu and atu */
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ret = mv88e6131_setup_global(ds);
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if (ret < 0)
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return ret;
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for (i = 0; i < 11; i++) {
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ret = mv88e6131_setup_port(ds, i);
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if (ret < 0)
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return ret;
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}
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return 0;
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}
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static int mv88e6131_port_to_phy_addr(int port)
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{
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if (port >= 0 && port <= 11)
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return port;
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return -1;
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}
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static int
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mv88e6131_phy_read(struct dsa_switch *ds, int port, int regnum)
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{
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int addr = mv88e6131_port_to_phy_addr(port);
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return mv88e6xxx_phy_read_ppu(ds, addr, regnum);
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}
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static int
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mv88e6131_phy_write(struct dsa_switch *ds,
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int port, int regnum, u16 val)
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{
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int addr = mv88e6131_port_to_phy_addr(port);
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return mv88e6xxx_phy_write_ppu(ds, addr, regnum, val);
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}
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static struct mv88e6xxx_hw_stat mv88e6131_hw_stats[] = {
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{ "in_good_octets", 8, 0x00, },
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{ "in_bad_octets", 4, 0x02, },
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{ "in_unicast", 4, 0x04, },
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{ "in_broadcasts", 4, 0x06, },
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{ "in_multicasts", 4, 0x07, },
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{ "in_pause", 4, 0x16, },
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{ "in_undersize", 4, 0x18, },
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{ "in_fragments", 4, 0x19, },
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{ "in_oversize", 4, 0x1a, },
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{ "in_jabber", 4, 0x1b, },
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{ "in_rx_error", 4, 0x1c, },
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{ "in_fcs_error", 4, 0x1d, },
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{ "out_octets", 8, 0x0e, },
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{ "out_unicast", 4, 0x10, },
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{ "out_broadcasts", 4, 0x13, },
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{ "out_multicasts", 4, 0x12, },
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{ "out_pause", 4, 0x15, },
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{ "excessive", 4, 0x11, },
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{ "collisions", 4, 0x1e, },
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{ "deferred", 4, 0x05, },
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{ "single", 4, 0x14, },
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{ "multiple", 4, 0x17, },
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{ "out_fcs_error", 4, 0x03, },
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{ "late", 4, 0x1f, },
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{ "hist_64bytes", 4, 0x08, },
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{ "hist_65_127bytes", 4, 0x09, },
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{ "hist_128_255bytes", 4, 0x0a, },
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{ "hist_256_511bytes", 4, 0x0b, },
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{ "hist_512_1023bytes", 4, 0x0c, },
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{ "hist_1024_max_bytes", 4, 0x0d, },
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};
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static void
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mv88e6131_get_strings(struct dsa_switch *ds, int port, uint8_t *data)
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{
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mv88e6xxx_get_strings(ds, ARRAY_SIZE(mv88e6131_hw_stats),
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mv88e6131_hw_stats, port, data);
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}
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static void
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mv88e6131_get_ethtool_stats(struct dsa_switch *ds,
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int port, uint64_t *data)
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{
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mv88e6xxx_get_ethtool_stats(ds, ARRAY_SIZE(mv88e6131_hw_stats),
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mv88e6131_hw_stats, port, data);
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}
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static int mv88e6131_get_sset_count(struct dsa_switch *ds)
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{
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return ARRAY_SIZE(mv88e6131_hw_stats);
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}
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static struct dsa_switch_driver mv88e6131_switch_driver = {
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.tag_protocol = cpu_to_be16(ETH_P_DSA),
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.priv_size = sizeof(struct mv88e6xxx_priv_state),
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.probe = mv88e6131_probe,
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.setup = mv88e6131_setup,
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.set_addr = mv88e6xxx_set_addr_direct,
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.phy_read = mv88e6131_phy_read,
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.phy_write = mv88e6131_phy_write,
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.poll_link = mv88e6xxx_poll_link,
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.get_strings = mv88e6131_get_strings,
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.get_ethtool_stats = mv88e6131_get_ethtool_stats,
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.get_sset_count = mv88e6131_get_sset_count,
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};
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static int __init mv88e6131_init(void)
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{
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register_switch_driver(&mv88e6131_switch_driver);
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return 0;
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}
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module_init(mv88e6131_init);
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static void __exit mv88e6131_cleanup(void)
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{
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unregister_switch_driver(&mv88e6131_switch_driver);
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}
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module_exit(mv88e6131_cleanup);
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