443 строки
11 KiB
C
443 строки
11 KiB
C
/*
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* hades-pci.c - Hardware specific PCI BIOS functions the Hades Atari clone.
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*
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* Written by Wout Klaren.
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*/
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#include <linux/init.h>
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#include <linux/kernel.h>
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#include <asm/io.h>
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#if 0
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# define DBG_DEVS(args) printk args
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#else
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# define DBG_DEVS(args)
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#endif
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#if defined(CONFIG_PCI) && defined(CONFIG_HADES)
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#include <linux/slab.h>
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#include <linux/mm.h>
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#include <linux/pci.h>
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#include <asm/atarihw.h>
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#include <asm/atariints.h>
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#include <asm/byteorder.h>
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#include <asm/pci.h>
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#define HADES_MEM_BASE 0x80000000
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#define HADES_MEM_SIZE 0x20000000
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#define HADES_CONFIG_BASE 0xA0000000
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#define HADES_CONFIG_SIZE 0x10000000
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#define HADES_IO_BASE 0xB0000000
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#define HADES_IO_SIZE 0x10000000
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#define HADES_VIRT_IO_SIZE 0x00010000 /* Only 64k is remapped and actually used. */
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#define N_SLOTS 4 /* Number of PCI slots. */
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static const char pci_mem_name[] = "PCI memory space";
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static const char pci_io_name[] = "PCI I/O space";
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static const char pci_config_name[] = "PCI config space";
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static struct resource config_space = {
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.name = pci_config_name,
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.start = HADES_CONFIG_BASE,
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.end = HADES_CONFIG_BASE + HADES_CONFIG_SIZE - 1
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};
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static struct resource io_space = {
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.name = pci_io_name,
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.start = HADES_IO_BASE,
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.end = HADES_IO_BASE + HADES_IO_SIZE - 1
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};
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static const unsigned long pci_conf_base_phys[] = {
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0xA0080000, 0xA0040000, 0xA0020000, 0xA0010000
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};
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static unsigned long pci_conf_base_virt[N_SLOTS];
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static unsigned long pci_io_base_virt;
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/*
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* static void *mk_conf_addr(unsigned char bus, unsigned char device_fn,
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* unsigned char where)
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*
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* Calculate the address of the PCI configuration area of the given
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* device.
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*
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* BUG: boards with multiple functions are probably not correctly
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* supported.
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*/
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static void *mk_conf_addr(struct pci_dev *dev, int where)
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{
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int device = dev->devfn >> 3, function = dev->devfn & 7;
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void *result;
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DBG_DEVS(("mk_conf_addr(bus=%d ,device_fn=0x%x, where=0x%x, pci_addr=0x%p)\n",
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dev->bus->number, dev->devfn, where, pci_addr));
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if (device > 3)
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{
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DBG_DEVS(("mk_conf_addr: device (%d) > 3, returning NULL\n", device));
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return NULL;
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}
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if (dev->bus->number != 0)
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{
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DBG_DEVS(("mk_conf_addr: bus (%d) > 0, returning NULL\n", device));
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return NULL;
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}
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result = (void *) (pci_conf_base_virt[device] | (function << 8) | (where));
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DBG_DEVS(("mk_conf_addr: returning pci_addr 0x%lx\n", (unsigned long) result));
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return result;
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}
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static int hades_read_config_byte(struct pci_dev *dev, int where, u8 *value)
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{
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volatile unsigned char *pci_addr;
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*value = 0xff;
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if ((pci_addr = (unsigned char *) mk_conf_addr(dev, where)) == NULL)
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return PCIBIOS_DEVICE_NOT_FOUND;
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*value = *pci_addr;
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return PCIBIOS_SUCCESSFUL;
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}
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static int hades_read_config_word(struct pci_dev *dev, int where, u16 *value)
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{
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volatile unsigned short *pci_addr;
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*value = 0xffff;
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if (where & 0x1)
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return PCIBIOS_BAD_REGISTER_NUMBER;
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if ((pci_addr = (unsigned short *) mk_conf_addr(dev, where)) == NULL)
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return PCIBIOS_DEVICE_NOT_FOUND;
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*value = le16_to_cpu(*pci_addr);
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return PCIBIOS_SUCCESSFUL;
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}
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static int hades_read_config_dword(struct pci_dev *dev, int where, u32 *value)
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{
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volatile unsigned int *pci_addr;
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unsigned char header_type;
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int result;
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*value = 0xffffffff;
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if (where & 0x3)
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return PCIBIOS_BAD_REGISTER_NUMBER;
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if ((pci_addr = (unsigned int *) mk_conf_addr(dev, where)) == NULL)
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return PCIBIOS_DEVICE_NOT_FOUND;
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*value = le32_to_cpu(*pci_addr);
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/*
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* Check if the value is an address on the bus. If true, add the
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* base address of the PCI memory or PCI I/O area on the Hades.
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*/
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if ((result = hades_read_config_byte(dev, PCI_HEADER_TYPE,
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&header_type)) != PCIBIOS_SUCCESSFUL)
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return result;
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if (((where >= PCI_BASE_ADDRESS_0) && (where <= PCI_BASE_ADDRESS_1)) ||
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((header_type != PCI_HEADER_TYPE_BRIDGE) && ((where >= PCI_BASE_ADDRESS_2) &&
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(where <= PCI_BASE_ADDRESS_5))))
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{
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if ((*value & PCI_BASE_ADDRESS_SPACE) == PCI_BASE_ADDRESS_SPACE_IO)
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{
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/*
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* Base address register that contains an I/O address. If the
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* address is valid on the Hades (0 <= *value < HADES_VIRT_IO_SIZE),
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* add 'pci_io_base_virt' to the value.
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*/
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if (*value < HADES_VIRT_IO_SIZE)
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*value += pci_io_base_virt;
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}
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else
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{
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/*
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* Base address register that contains an memory address. If the
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* address is valid on the Hades (0 <= *value < HADES_MEM_SIZE),
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* add HADES_MEM_BASE to the value.
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*/
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if (*value == 0)
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{
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/*
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* Base address is 0. Test if this base
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* address register is used.
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*/
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*pci_addr = 0xffffffff;
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if (*pci_addr != 0)
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{
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*pci_addr = *value;
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if (*value < HADES_MEM_SIZE)
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*value += HADES_MEM_BASE;
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}
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}
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else
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{
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if (*value < HADES_MEM_SIZE)
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*value += HADES_MEM_BASE;
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}
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}
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}
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return PCIBIOS_SUCCESSFUL;
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}
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static int hades_write_config_byte(struct pci_dev *dev, int where, u8 value)
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{
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volatile unsigned char *pci_addr;
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if ((pci_addr = (unsigned char *) mk_conf_addr(dev, where)) == NULL)
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return PCIBIOS_DEVICE_NOT_FOUND;
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*pci_addr = value;
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return PCIBIOS_SUCCESSFUL;
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}
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static int hades_write_config_word(struct pci_dev *dev, int where, u16 value)
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{
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volatile unsigned short *pci_addr;
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if ((pci_addr = (unsigned short *) mk_conf_addr(dev, where)) == NULL)
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return PCIBIOS_DEVICE_NOT_FOUND;
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*pci_addr = cpu_to_le16(value);
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return PCIBIOS_SUCCESSFUL;
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}
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static int hades_write_config_dword(struct pci_dev *dev, int where, u32 value)
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{
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volatile unsigned int *pci_addr;
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unsigned char header_type;
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int result;
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if ((pci_addr = (unsigned int *) mk_conf_addr(dev, where)) == NULL)
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return PCIBIOS_DEVICE_NOT_FOUND;
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/*
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* Check if the value is an address on the bus. If true, subtract the
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* base address of the PCI memory or PCI I/O area on the Hades.
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*/
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if ((result = hades_read_config_byte(dev, PCI_HEADER_TYPE,
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&header_type)) != PCIBIOS_SUCCESSFUL)
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return result;
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if (((where >= PCI_BASE_ADDRESS_0) && (where <= PCI_BASE_ADDRESS_1)) ||
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((header_type != PCI_HEADER_TYPE_BRIDGE) && ((where >= PCI_BASE_ADDRESS_2) &&
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(where <= PCI_BASE_ADDRESS_5))))
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{
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if ((value & PCI_BASE_ADDRESS_SPACE) ==
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PCI_BASE_ADDRESS_SPACE_IO)
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{
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/*
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* I/O address. Check if the address is valid address on
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* the Hades (pci_io_base_virt <= value < pci_io_base_virt +
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* HADES_VIRT_IO_SIZE) or if the value is 0xffffffff. If not
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* true do not write the base address register. If it is a
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* valid base address subtract 'pci_io_base_virt' from the value.
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*/
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if ((value >= pci_io_base_virt) && (value < (pci_io_base_virt +
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HADES_VIRT_IO_SIZE)))
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value -= pci_io_base_virt;
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else
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{
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if (value != 0xffffffff)
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return PCIBIOS_SET_FAILED;
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}
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}
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else
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{
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/*
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* Memory address. Check if the address is valid address on
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* the Hades (HADES_MEM_BASE <= value < HADES_MEM_BASE + HADES_MEM_SIZE) or
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* if the value is 0xffffffff. If not true do not write
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* the base address register. If it is a valid base address
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* subtract HADES_MEM_BASE from the value.
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*/
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if ((value >= HADES_MEM_BASE) && (value < (HADES_MEM_BASE + HADES_MEM_SIZE)))
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value -= HADES_MEM_BASE;
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else
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{
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if (value != 0xffffffff)
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return PCIBIOS_SET_FAILED;
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}
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}
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}
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*pci_addr = cpu_to_le32(value);
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return PCIBIOS_SUCCESSFUL;
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}
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/*
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* static inline void hades_fixup(void)
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*
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* Assign IRQ numbers as used by Linux to the interrupt pins
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* of the PCI cards.
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*/
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static void __init hades_fixup(int pci_modify)
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{
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char irq_tab[4] = {
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[0] = IRQ_TT_MFP_IO0, /* Slot 0. */
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[1] = IRQ_TT_MFP_IO1, /* Slot 1. */
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[2] = IRQ_TT_MFP_SCC, /* Slot 2. */
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[3] = IRQ_TT_MFP_SCSIDMA /* Slot 3. */
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};
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struct pci_dev *dev = NULL;
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unsigned char slot;
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/*
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* Go through all devices, fixing up irqs as we see fit:
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*/
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while ((dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev)) != NULL)
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{
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if (dev->class >> 16 != PCI_BASE_CLASS_BRIDGE)
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{
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slot = PCI_SLOT(dev->devfn); /* Determine slot number. */
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dev->irq = irq_tab[slot];
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if (pci_modify)
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pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq);
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}
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}
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}
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/*
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* static void hades_conf_device(struct pci_dev *dev)
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*
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* Machine dependent Configure the given device.
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*
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* Parameters:
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*
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* dev - the pci device.
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*/
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static void __init hades_conf_device(struct pci_dev *dev)
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{
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pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, 0);
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}
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static struct pci_ops hades_pci_ops = {
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.read_byte = hades_read_config_byte,
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.read_word = hades_read_config_word,
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.read_dword = hades_read_config_dword,
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.write_byte = hades_write_config_byte,
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.write_word = hades_write_config_word,
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.write_dword = hades_write_config_dword
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};
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/*
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* struct pci_bus_info *init_hades_pci(void)
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*
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* Machine specific initialisation:
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*
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* - Allocate and initialise a 'pci_bus_info' structure
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* - Initialise hardware
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*
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* Result: pointer to 'pci_bus_info' structure.
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*/
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struct pci_bus_info * __init init_hades_pci(void)
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{
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struct pci_bus_info *bus;
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int i;
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/*
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* Remap I/O and configuration space.
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*/
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pci_io_base_virt = (unsigned long) ioremap(HADES_IO_BASE, HADES_VIRT_IO_SIZE);
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for (i = 0; i < N_SLOTS; i++)
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pci_conf_base_virt[i] = (unsigned long) ioremap(pci_conf_base_phys[i], 0x10000);
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/*
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* Allocate memory for bus info structure.
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*/
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bus = kzalloc(sizeof(struct pci_bus_info), GFP_KERNEL);
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if (!bus)
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return NULL;
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/*
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* Claim resources. The m68k has no separate I/O space, both
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* PCI memory space and PCI I/O space are in memory space. Therefore
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* the I/O resources are requested in memory space as well.
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*/
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if (request_resource(&iomem_resource, &config_space) != 0)
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{
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kfree(bus);
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return NULL;
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}
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if (request_resource(&iomem_resource, &io_space) != 0)
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{
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release_resource(&config_space);
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kfree(bus);
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return NULL;
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}
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bus->mem_space.start = HADES_MEM_BASE;
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bus->mem_space.end = HADES_MEM_BASE + HADES_MEM_SIZE - 1;
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bus->mem_space.name = pci_mem_name;
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#if 1
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if (request_resource(&iomem_resource, &bus->mem_space) != 0)
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{
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release_resource(&io_space);
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release_resource(&config_space);
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kfree(bus);
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return NULL;
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}
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#endif
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bus->io_space.start = pci_io_base_virt;
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bus->io_space.end = pci_io_base_virt + HADES_VIRT_IO_SIZE - 1;
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bus->io_space.name = pci_io_name;
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#if 1
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if (request_resource(&ioport_resource, &bus->io_space) != 0)
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{
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release_resource(&bus->mem_space);
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release_resource(&io_space);
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release_resource(&config_space);
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kfree(bus);
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return NULL;
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}
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#endif
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/*
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* Set hardware dependent functions.
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*/
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bus->m68k_pci_ops = &hades_pci_ops;
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bus->fixup = hades_fixup;
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bus->conf_device = hades_conf_device;
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/*
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* Select high to low edge for PCI interrupts.
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*/
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tt_mfp.active_edge &= ~0x27;
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return bus;
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}
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#endif
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