589 строки
16 KiB
C
589 строки
16 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2018 Arm Limited. All rights reserved.
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*
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* Coresight Address Translation Unit support
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*
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* Author: Suzuki K Poulose <suzuki.poulose@arm.com>
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*/
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#include <linux/amba/bus.h>
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#include <linux/device.h>
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#include <linux/dma-mapping.h>
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#include <linux/io.h>
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#include <linux/kernel.h>
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#include <linux/slab.h>
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#include "coresight-catu.h"
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#include "coresight-priv.h"
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#include "coresight-tmc.h"
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#define csdev_to_catu_drvdata(csdev) \
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dev_get_drvdata(csdev->dev.parent)
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/* Verbose output for CATU table contents */
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#ifdef CATU_DEBUG
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#define catu_dbg(x, ...) dev_dbg(x, __VA_ARGS__)
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#else
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#define catu_dbg(x, ...) do {} while (0)
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#endif
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DEFINE_CORESIGHT_DEVLIST(catu_devs, "catu");
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struct catu_etr_buf {
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struct tmc_sg_table *catu_table;
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dma_addr_t sladdr;
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};
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/*
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* CATU uses a page size of 4KB for page tables as well as data pages.
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* Each 64bit entry in the table has the following format.
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*
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* 63 12 1 0
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* ------------------------------------
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* | Address [63-12] | SBZ | V|
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* ------------------------------------
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*
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* Where bit[0] V indicates if the address is valid or not.
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* Each 4K table pages have upto 256 data page pointers, taking upto 2K
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* size. There are two Link pointers, pointing to the previous and next
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* table pages respectively at the end of the 4K page. (i.e, entry 510
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* and 511).
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* E.g, a table of two pages could look like :
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*
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* Table Page 0 Table Page 1
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* SLADDR ===> x------------------x x--> x-----------------x
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* INADDR ->| Page 0 | V | | | Page 256 | V | <- INADDR+1M
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* |------------------| | |-----------------|
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* INADDR+4K ->| Page 1 | V | | | |
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* |------------------| | |-----------------|
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* | Page 2 | V | | | |
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* |------------------| | |-----------------|
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* | ... | V | | | ... |
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* |------------------| | |-----------------|
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* INADDR+1020K| Page 255 | V | | | Page 511 | V |
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* SLADDR+2K==>|------------------| | |-----------------|
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* | UNUSED | | | | |
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* |------------------| | | |
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* | UNUSED | | | | |
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* |------------------| | | |
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* | ... | | | | |
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* |------------------| | |-----------------|
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* | IGNORED | 0 | | | Table Page 0| 1 |
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* |------------------| | |-----------------|
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* | Table Page 1| 1 |--x | IGNORED | 0 |
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* x------------------x x-----------------x
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* SLADDR+4K==>
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*
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* The base input address (used by the ETR, programmed in INADDR_{LO,HI})
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* must be aligned to 1MB (the size addressable by a single page table).
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* The CATU maps INADDR{LO:HI} to the first page in the table pointed
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* to by SLADDR{LO:HI} and so on.
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*
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*/
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typedef u64 cate_t;
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#define CATU_PAGE_SHIFT 12
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#define CATU_PAGE_SIZE (1UL << CATU_PAGE_SHIFT)
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#define CATU_PAGES_PER_SYSPAGE (PAGE_SIZE / CATU_PAGE_SIZE)
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/* Page pointers are only allocated in the first 2K half */
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#define CATU_PTRS_PER_PAGE ((CATU_PAGE_SIZE >> 1) / sizeof(cate_t))
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#define CATU_PTRS_PER_SYSPAGE (CATU_PAGES_PER_SYSPAGE * CATU_PTRS_PER_PAGE)
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#define CATU_LINK_PREV ((CATU_PAGE_SIZE / sizeof(cate_t)) - 2)
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#define CATU_LINK_NEXT ((CATU_PAGE_SIZE / sizeof(cate_t)) - 1)
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#define CATU_ADDR_SHIFT 12
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#define CATU_ADDR_MASK ~(((cate_t)1 << CATU_ADDR_SHIFT) - 1)
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#define CATU_ENTRY_VALID ((cate_t)0x1)
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#define CATU_VALID_ENTRY(addr) \
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(((cate_t)(addr) & CATU_ADDR_MASK) | CATU_ENTRY_VALID)
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#define CATU_ENTRY_ADDR(entry) ((cate_t)(entry) & ~((cate_t)CATU_ENTRY_VALID))
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/* CATU expects the INADDR to be aligned to 1M. */
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#define CATU_DEFAULT_INADDR (1ULL << 20)
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/*
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* catu_get_table : Retrieve the table pointers for the given @offset
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* within the buffer. The buffer is wrapped around to a valid offset.
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*
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* Returns : The CPU virtual address for the beginning of the table
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* containing the data page pointer for @offset. If @daddrp is not NULL,
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* @daddrp points the DMA address of the beginning of the table.
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*/
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static inline cate_t *catu_get_table(struct tmc_sg_table *catu_table,
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unsigned long offset,
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dma_addr_t *daddrp)
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{
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unsigned long buf_size = tmc_sg_table_buf_size(catu_table);
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unsigned int table_nr, pg_idx, pg_offset;
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struct tmc_pages *table_pages = &catu_table->table_pages;
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void *ptr;
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/* Make sure offset is within the range */
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offset %= buf_size;
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/*
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* Each table can address 1MB and a single kernel page can
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* contain "CATU_PAGES_PER_SYSPAGE" CATU tables.
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*/
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table_nr = offset >> 20;
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/* Find the table page where the table_nr lies in */
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pg_idx = table_nr / CATU_PAGES_PER_SYSPAGE;
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pg_offset = (table_nr % CATU_PAGES_PER_SYSPAGE) * CATU_PAGE_SIZE;
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if (daddrp)
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*daddrp = table_pages->daddrs[pg_idx] + pg_offset;
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ptr = page_address(table_pages->pages[pg_idx]);
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return (cate_t *)((unsigned long)ptr + pg_offset);
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}
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#ifdef CATU_DEBUG
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static void catu_dump_table(struct tmc_sg_table *catu_table)
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{
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int i;
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cate_t *table;
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unsigned long table_end, buf_size, offset = 0;
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buf_size = tmc_sg_table_buf_size(catu_table);
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dev_dbg(catu_table->dev,
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"Dump table %p, tdaddr: %llx\n",
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catu_table, catu_table->table_daddr);
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while (offset < buf_size) {
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table_end = offset + SZ_1M < buf_size ?
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offset + SZ_1M : buf_size;
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table = catu_get_table(catu_table, offset, NULL);
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for (i = 0; offset < table_end; i++, offset += CATU_PAGE_SIZE)
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dev_dbg(catu_table->dev, "%d: %llx\n", i, table[i]);
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dev_dbg(catu_table->dev, "Prev : %llx, Next: %llx\n",
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table[CATU_LINK_PREV], table[CATU_LINK_NEXT]);
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dev_dbg(catu_table->dev, "== End of sub-table ===");
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}
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dev_dbg(catu_table->dev, "== End of Table ===");
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}
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#else
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static inline void catu_dump_table(struct tmc_sg_table *catu_table)
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{
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}
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#endif
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static inline cate_t catu_make_entry(dma_addr_t addr)
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{
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return addr ? CATU_VALID_ENTRY(addr) : 0;
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}
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/*
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* catu_populate_table : Populate the given CATU table.
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* The table is always populated as a circular table.
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* i.e, the "prev" link of the "first" table points to the "last"
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* table and the "next" link of the "last" table points to the
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* "first" table. The buffer should be made linear by calling
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* catu_set_table().
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*/
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static void
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catu_populate_table(struct tmc_sg_table *catu_table)
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{
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int i;
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int sys_pidx; /* Index to current system data page */
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int catu_pidx; /* Index of CATU page within the system data page */
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unsigned long offset, buf_size, table_end;
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dma_addr_t data_daddr;
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dma_addr_t prev_taddr, next_taddr, cur_taddr;
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cate_t *table_ptr, *next_table;
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buf_size = tmc_sg_table_buf_size(catu_table);
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sys_pidx = catu_pidx = 0;
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offset = 0;
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table_ptr = catu_get_table(catu_table, 0, &cur_taddr);
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prev_taddr = 0; /* Prev link for the first table */
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while (offset < buf_size) {
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/*
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* The @offset is always 1M aligned here and we have an
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* empty table @table_ptr to fill. Each table can address
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* upto 1MB data buffer. The last table may have fewer
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* entries if the buffer size is not aligned.
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*/
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table_end = (offset + SZ_1M) < buf_size ?
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(offset + SZ_1M) : buf_size;
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for (i = 0; offset < table_end;
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i++, offset += CATU_PAGE_SIZE) {
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data_daddr = catu_table->data_pages.daddrs[sys_pidx] +
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catu_pidx * CATU_PAGE_SIZE;
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catu_dbg(catu_table->dev,
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"[table %5ld:%03d] 0x%llx\n",
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(offset >> 20), i, data_daddr);
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table_ptr[i] = catu_make_entry(data_daddr);
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/* Move the pointers for data pages */
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catu_pidx = (catu_pidx + 1) % CATU_PAGES_PER_SYSPAGE;
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if (catu_pidx == 0)
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sys_pidx++;
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}
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/*
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* If we have finished all the valid entries, fill the rest of
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* the table (i.e, last table page) with invalid entries,
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* to fail the lookups.
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*/
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if (offset == buf_size) {
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memset(&table_ptr[i], 0,
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sizeof(cate_t) * (CATU_PTRS_PER_PAGE - i));
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next_taddr = 0;
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} else {
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next_table = catu_get_table(catu_table,
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offset, &next_taddr);
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}
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table_ptr[CATU_LINK_PREV] = catu_make_entry(prev_taddr);
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table_ptr[CATU_LINK_NEXT] = catu_make_entry(next_taddr);
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catu_dbg(catu_table->dev,
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"[table%5ld]: Cur: 0x%llx Prev: 0x%llx, Next: 0x%llx\n",
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(offset >> 20) - 1, cur_taddr, prev_taddr, next_taddr);
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/* Update the prev/next addresses */
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if (next_taddr) {
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prev_taddr = cur_taddr;
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cur_taddr = next_taddr;
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table_ptr = next_table;
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}
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}
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/* Sync the table for device */
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tmc_sg_table_sync_table(catu_table);
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}
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static struct tmc_sg_table *
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catu_init_sg_table(struct device *catu_dev, int node,
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ssize_t size, void **pages)
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{
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int nr_tpages;
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struct tmc_sg_table *catu_table;
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/*
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* Each table can address upto 1MB and we can have
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* CATU_PAGES_PER_SYSPAGE tables in a system page.
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*/
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nr_tpages = DIV_ROUND_UP(size, SZ_1M) / CATU_PAGES_PER_SYSPAGE;
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catu_table = tmc_alloc_sg_table(catu_dev, node, nr_tpages,
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size >> PAGE_SHIFT, pages);
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if (IS_ERR(catu_table))
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return catu_table;
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catu_populate_table(catu_table);
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dev_dbg(catu_dev,
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"Setup table %p, size %ldKB, %d table pages\n",
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catu_table, (unsigned long)size >> 10, nr_tpages);
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catu_dump_table(catu_table);
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return catu_table;
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}
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static void catu_free_etr_buf(struct etr_buf *etr_buf)
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{
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struct catu_etr_buf *catu_buf;
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if (!etr_buf || etr_buf->mode != ETR_MODE_CATU || !etr_buf->private)
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return;
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catu_buf = etr_buf->private;
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tmc_free_sg_table(catu_buf->catu_table);
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kfree(catu_buf);
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}
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static ssize_t catu_get_data_etr_buf(struct etr_buf *etr_buf, u64 offset,
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size_t len, char **bufpp)
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{
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struct catu_etr_buf *catu_buf = etr_buf->private;
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return tmc_sg_table_get_data(catu_buf->catu_table, offset, len, bufpp);
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}
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static void catu_sync_etr_buf(struct etr_buf *etr_buf, u64 rrp, u64 rwp)
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{
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struct catu_etr_buf *catu_buf = etr_buf->private;
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struct tmc_sg_table *catu_table = catu_buf->catu_table;
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u64 r_offset, w_offset;
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/*
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* ETR started off at etr_buf->hwaddr. Convert the RRP/RWP to
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* offsets within the trace buffer.
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*/
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r_offset = rrp - etr_buf->hwaddr;
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w_offset = rwp - etr_buf->hwaddr;
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if (!etr_buf->full) {
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etr_buf->len = w_offset - r_offset;
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if (w_offset < r_offset)
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etr_buf->len += etr_buf->size;
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} else {
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etr_buf->len = etr_buf->size;
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}
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etr_buf->offset = r_offset;
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tmc_sg_table_sync_data_range(catu_table, r_offset, etr_buf->len);
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}
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static int catu_alloc_etr_buf(struct tmc_drvdata *tmc_drvdata,
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struct etr_buf *etr_buf, int node, void **pages)
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{
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struct coresight_device *csdev;
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struct tmc_sg_table *catu_table;
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struct catu_etr_buf *catu_buf;
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csdev = tmc_etr_get_catu_device(tmc_drvdata);
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if (!csdev)
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return -ENODEV;
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catu_buf = kzalloc(sizeof(*catu_buf), GFP_KERNEL);
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if (!catu_buf)
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return -ENOMEM;
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catu_table = catu_init_sg_table(&csdev->dev, node,
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etr_buf->size, pages);
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if (IS_ERR(catu_table)) {
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kfree(catu_buf);
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return PTR_ERR(catu_table);
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}
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etr_buf->mode = ETR_MODE_CATU;
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etr_buf->private = catu_buf;
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etr_buf->hwaddr = CATU_DEFAULT_INADDR;
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catu_buf->catu_table = catu_table;
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/* Get the table base address */
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catu_buf->sladdr = catu_table->table_daddr;
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return 0;
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}
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const struct etr_buf_operations etr_catu_buf_ops = {
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.alloc = catu_alloc_etr_buf,
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.free = catu_free_etr_buf,
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.sync = catu_sync_etr_buf,
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.get_data = catu_get_data_etr_buf,
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};
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coresight_simple_reg32(struct catu_drvdata, devid, CORESIGHT_DEVID);
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coresight_simple_reg32(struct catu_drvdata, control, CATU_CONTROL);
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coresight_simple_reg32(struct catu_drvdata, status, CATU_STATUS);
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coresight_simple_reg32(struct catu_drvdata, mode, CATU_MODE);
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coresight_simple_reg32(struct catu_drvdata, axictrl, CATU_AXICTRL);
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coresight_simple_reg32(struct catu_drvdata, irqen, CATU_IRQEN);
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coresight_simple_reg64(struct catu_drvdata, sladdr,
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CATU_SLADDRLO, CATU_SLADDRHI);
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coresight_simple_reg64(struct catu_drvdata, inaddr,
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CATU_INADDRLO, CATU_INADDRHI);
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static struct attribute *catu_mgmt_attrs[] = {
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&dev_attr_devid.attr,
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&dev_attr_control.attr,
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&dev_attr_status.attr,
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&dev_attr_mode.attr,
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&dev_attr_axictrl.attr,
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&dev_attr_irqen.attr,
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&dev_attr_sladdr.attr,
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&dev_attr_inaddr.attr,
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NULL,
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};
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static const struct attribute_group catu_mgmt_group = {
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.attrs = catu_mgmt_attrs,
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.name = "mgmt",
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};
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static const struct attribute_group *catu_groups[] = {
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&catu_mgmt_group,
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NULL,
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};
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static inline int catu_wait_for_ready(struct catu_drvdata *drvdata)
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{
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return coresight_timeout(drvdata->base,
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CATU_STATUS, CATU_STATUS_READY, 1);
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}
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static int catu_enable_hw(struct catu_drvdata *drvdata, void *data)
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{
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int rc;
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u32 control, mode;
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struct etr_buf *etr_buf = data;
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struct device *dev = &drvdata->csdev->dev;
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if (catu_wait_for_ready(drvdata))
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dev_warn(dev, "Timeout while waiting for READY\n");
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control = catu_read_control(drvdata);
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if (control & BIT(CATU_CONTROL_ENABLE)) {
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dev_warn(dev, "CATU is already enabled\n");
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return -EBUSY;
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}
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rc = coresight_claim_device_unlocked(drvdata->base);
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if (rc)
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return rc;
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control |= BIT(CATU_CONTROL_ENABLE);
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if (etr_buf && etr_buf->mode == ETR_MODE_CATU) {
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struct catu_etr_buf *catu_buf = etr_buf->private;
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mode = CATU_MODE_TRANSLATE;
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catu_write_axictrl(drvdata, CATU_OS_AXICTRL);
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catu_write_sladdr(drvdata, catu_buf->sladdr);
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catu_write_inaddr(drvdata, CATU_DEFAULT_INADDR);
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} else {
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mode = CATU_MODE_PASS_THROUGH;
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catu_write_sladdr(drvdata, 0);
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catu_write_inaddr(drvdata, 0);
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}
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catu_write_irqen(drvdata, 0);
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catu_write_mode(drvdata, mode);
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catu_write_control(drvdata, control);
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dev_dbg(dev, "Enabled in %s mode\n",
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(mode == CATU_MODE_PASS_THROUGH) ?
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"Pass through" :
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"Translate");
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return 0;
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}
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static int catu_enable(struct coresight_device *csdev, void *data)
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{
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int rc;
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struct catu_drvdata *catu_drvdata = csdev_to_catu_drvdata(csdev);
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|
|
|
CS_UNLOCK(catu_drvdata->base);
|
|
rc = catu_enable_hw(catu_drvdata, data);
|
|
CS_LOCK(catu_drvdata->base);
|
|
return rc;
|
|
}
|
|
|
|
static int catu_disable_hw(struct catu_drvdata *drvdata)
|
|
{
|
|
int rc = 0;
|
|
struct device *dev = &drvdata->csdev->dev;
|
|
|
|
catu_write_control(drvdata, 0);
|
|
coresight_disclaim_device_unlocked(drvdata->base);
|
|
if (catu_wait_for_ready(drvdata)) {
|
|
dev_info(dev, "Timeout while waiting for READY\n");
|
|
rc = -EAGAIN;
|
|
}
|
|
|
|
dev_dbg(dev, "Disabled\n");
|
|
return rc;
|
|
}
|
|
|
|
static int catu_disable(struct coresight_device *csdev, void *__unused)
|
|
{
|
|
int rc;
|
|
struct catu_drvdata *catu_drvdata = csdev_to_catu_drvdata(csdev);
|
|
|
|
CS_UNLOCK(catu_drvdata->base);
|
|
rc = catu_disable_hw(catu_drvdata);
|
|
CS_LOCK(catu_drvdata->base);
|
|
return rc;
|
|
}
|
|
|
|
static const struct coresight_ops_helper catu_helper_ops = {
|
|
.enable = catu_enable,
|
|
.disable = catu_disable,
|
|
};
|
|
|
|
static const struct coresight_ops catu_ops = {
|
|
.helper_ops = &catu_helper_ops,
|
|
};
|
|
|
|
static int catu_probe(struct amba_device *adev, const struct amba_id *id)
|
|
{
|
|
int ret = 0;
|
|
u32 dma_mask;
|
|
struct catu_drvdata *drvdata;
|
|
struct coresight_desc catu_desc;
|
|
struct coresight_platform_data *pdata = NULL;
|
|
struct device *dev = &adev->dev;
|
|
void __iomem *base;
|
|
|
|
catu_desc.name = coresight_alloc_device_name(&catu_devs, dev);
|
|
if (!catu_desc.name)
|
|
return -ENOMEM;
|
|
|
|
drvdata = devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL);
|
|
if (!drvdata) {
|
|
ret = -ENOMEM;
|
|
goto out;
|
|
}
|
|
|
|
dev_set_drvdata(dev, drvdata);
|
|
base = devm_ioremap_resource(dev, &adev->res);
|
|
if (IS_ERR(base)) {
|
|
ret = PTR_ERR(base);
|
|
goto out;
|
|
}
|
|
|
|
/* Setup dma mask for the device */
|
|
dma_mask = readl_relaxed(base + CORESIGHT_DEVID) & 0x3f;
|
|
switch (dma_mask) {
|
|
case 32:
|
|
case 40:
|
|
case 44:
|
|
case 48:
|
|
case 52:
|
|
case 56:
|
|
case 64:
|
|
break;
|
|
default:
|
|
/* Default to the 40bits as supported by TMC-ETR */
|
|
dma_mask = 40;
|
|
}
|
|
ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(dma_mask));
|
|
if (ret)
|
|
goto out;
|
|
|
|
pdata = coresight_get_platform_data(dev);
|
|
if (IS_ERR(pdata)) {
|
|
ret = PTR_ERR(pdata);
|
|
goto out;
|
|
}
|
|
dev->platform_data = pdata;
|
|
|
|
drvdata->base = base;
|
|
catu_desc.pdata = pdata;
|
|
catu_desc.dev = dev;
|
|
catu_desc.groups = catu_groups;
|
|
catu_desc.type = CORESIGHT_DEV_TYPE_HELPER;
|
|
catu_desc.subtype.helper_subtype = CORESIGHT_DEV_SUBTYPE_HELPER_CATU;
|
|
catu_desc.ops = &catu_ops;
|
|
|
|
drvdata->csdev = coresight_register(&catu_desc);
|
|
if (IS_ERR(drvdata->csdev))
|
|
ret = PTR_ERR(drvdata->csdev);
|
|
else
|
|
pm_runtime_put(&adev->dev);
|
|
out:
|
|
return ret;
|
|
}
|
|
|
|
static struct amba_id catu_ids[] = {
|
|
{
|
|
.id = 0x000bb9ee,
|
|
.mask = 0x000fffff,
|
|
},
|
|
{},
|
|
};
|
|
|
|
static struct amba_driver catu_driver = {
|
|
.drv = {
|
|
.name = "coresight-catu",
|
|
.owner = THIS_MODULE,
|
|
.suppress_bind_attrs = true,
|
|
},
|
|
.probe = catu_probe,
|
|
.id_table = catu_ids,
|
|
};
|
|
|
|
builtin_amba_driver(catu_driver);
|