646 строки
16 KiB
C
646 строки
16 KiB
C
/*
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* MPC82xx_ads setup and early boot code plus other random bits.
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*
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* Author: Vitaly Bordug <vbordug@ru.mvista.com>
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* m82xx_restart fix by Wade Farnsworth <wfarnsworth@mvista.com>
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*
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* Copyright (c) 2006 MontaVista Software, Inc.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*/
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#include <linux/stddef.h>
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/errno.h>
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#include <linux/reboot.h>
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#include <linux/pci.h>
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#include <linux/interrupt.h>
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#include <linux/kdev_t.h>
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#include <linux/major.h>
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#include <linux/console.h>
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#include <linux/delay.h>
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#include <linux/seq_file.h>
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#include <linux/root_dev.h>
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#include <linux/initrd.h>
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#include <linux/module.h>
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#include <linux/fsl_devices.h>
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#include <linux/fs_uart_pd.h>
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#include <asm/system.h>
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#include <asm/pgtable.h>
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#include <asm/page.h>
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#include <asm/atomic.h>
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#include <asm/time.h>
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#include <asm/io.h>
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#include <asm/machdep.h>
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#include <asm/bootinfo.h>
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#include <asm/pci-bridge.h>
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#include <asm/mpc8260.h>
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#include <asm/irq.h>
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#include <mm/mmu_decl.h>
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#include <asm/prom.h>
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#include <asm/cpm2.h>
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#include <asm/udbg.h>
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#include <asm/i8259.h>
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#include <linux/fs_enet_pd.h>
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#include <sysdev/fsl_soc.h>
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#include <../sysdev/cpm2_pic.h>
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#include "pq2ads_pd.h"
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#ifdef CONFIG_PCI
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static uint pci_clk_frq;
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static struct {
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unsigned long *pci_int_stat_reg;
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unsigned long *pci_int_mask_reg;
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} pci_regs;
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static unsigned long pci_int_base;
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static struct irq_host *pci_pic_host;
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static struct device_node *pci_pic_node;
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#endif
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static void __init mpc82xx_ads_pic_init(void)
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{
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struct device_node *np = of_find_compatible_node(NULL, "cpm-pic", "CPM2");
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struct resource r;
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cpm2_map_t *cpm_reg;
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if (np == NULL) {
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printk(KERN_ERR "PIC init: can not find cpm-pic node\n");
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return;
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}
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if (of_address_to_resource(np, 0, &r)) {
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printk(KERN_ERR "PIC init: invalid resource\n");
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of_node_put(np);
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return;
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}
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cpm2_pic_init(np);
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of_node_put(np);
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/* Initialize the default interrupt mapping priorities,
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* in case the boot rom changed something on us.
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*/
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cpm_reg = (cpm2_map_t *) ioremap(get_immrbase(), sizeof(cpm2_map_t));
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cpm_reg->im_intctl.ic_siprr = 0x05309770;
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iounmap(cpm_reg);
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#ifdef CONFIG_PCI
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/* Initialize stuff for the 82xx CPLD IC and install demux */
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m82xx_pci_init_irq();
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#endif
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}
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static void init_fcc1_ioports(struct fs_platform_info *fpi)
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{
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struct io_port *io;
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u32 tempval;
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cpm2_map_t *immap = ioremap(get_immrbase(), sizeof(cpm2_map_t));
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struct device_node *np;
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struct resource r;
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u32 *bcsr;
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np = of_find_node_by_type(NULL, "memory");
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if (!np) {
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printk(KERN_INFO "No memory node in device tree\n");
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return;
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}
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if (of_address_to_resource(np, 1, &r)) {
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printk(KERN_INFO "No memory reg property [1] in devicetree\n");
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return;
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}
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of_node_put(np);
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bcsr = ioremap(r.start + 4, sizeof(u32));
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io = &immap->im_ioport;
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/* Enable the PHY */
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clrbits32(bcsr, BCSR1_FETHIEN);
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setbits32(bcsr, BCSR1_FETH_RST);
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/* FCC1 pins are on port A/C. */
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/* Configure port A and C pins for FCC1 Ethernet. */
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tempval = in_be32(&io->iop_pdira);
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tempval &= ~PA1_DIRA0;
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tempval |= PA1_DIRA1;
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out_be32(&io->iop_pdira, tempval);
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tempval = in_be32(&io->iop_psora);
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tempval &= ~PA1_PSORA0;
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tempval |= PA1_PSORA1;
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out_be32(&io->iop_psora, tempval);
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setbits32(&io->iop_ppara, PA1_DIRA0 | PA1_DIRA1);
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/* Alter clocks */
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tempval = PC_CLK(fpi->clk_tx - 8) | PC_CLK(fpi->clk_rx - 8);
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clrbits32(&io->iop_psorc, tempval);
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clrbits32(&io->iop_pdirc, tempval);
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setbits32(&io->iop_pparc, tempval);
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cpm2_clk_setup(CPM_CLK_FCC1, fpi->clk_rx, CPM_CLK_RX);
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cpm2_clk_setup(CPM_CLK_FCC1, fpi->clk_tx, CPM_CLK_TX);
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iounmap(bcsr);
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iounmap(immap);
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}
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static void init_fcc2_ioports(struct fs_platform_info *fpi)
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{
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cpm2_map_t *immap = ioremap(get_immrbase(), sizeof(cpm2_map_t));
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struct device_node *np;
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struct resource r;
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u32 *bcsr;
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struct io_port *io;
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u32 tempval;
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np = of_find_node_by_type(NULL, "memory");
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if (!np) {
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printk(KERN_INFO "No memory node in device tree\n");
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return;
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}
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if (of_address_to_resource(np, 1, &r)) {
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printk(KERN_INFO "No memory reg property [1] in devicetree\n");
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return;
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}
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of_node_put(np);
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io = &immap->im_ioport;
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bcsr = ioremap(r.start + 12, sizeof(u32));
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/* Enable the PHY */
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clrbits32(bcsr, BCSR3_FETHIEN2);
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setbits32(bcsr, BCSR3_FETH2_RST);
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/* FCC2 are port B/C. */
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/* Configure port A and C pins for FCC2 Ethernet. */
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tempval = in_be32(&io->iop_pdirb);
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tempval &= ~PB2_DIRB0;
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tempval |= PB2_DIRB1;
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out_be32(&io->iop_pdirb, tempval);
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tempval = in_be32(&io->iop_psorb);
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tempval &= ~PB2_PSORB0;
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tempval |= PB2_PSORB1;
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out_be32(&io->iop_psorb, tempval);
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setbits32(&io->iop_pparb, PB2_DIRB0 | PB2_DIRB1);
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tempval = PC_CLK(fpi->clk_tx - 8) | PC_CLK(fpi->clk_rx - 8);
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/* Alter clocks */
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clrbits32(&io->iop_psorc, tempval);
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clrbits32(&io->iop_pdirc, tempval);
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setbits32(&io->iop_pparc, tempval);
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cpm2_clk_setup(CPM_CLK_FCC2, fpi->clk_rx, CPM_CLK_RX);
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cpm2_clk_setup(CPM_CLK_FCC2, fpi->clk_tx, CPM_CLK_TX);
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iounmap(bcsr);
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iounmap(immap);
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}
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void init_fcc_ioports(struct fs_platform_info *fpi)
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{
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int fcc_no = fs_get_fcc_index(fpi->fs_no);
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switch (fcc_no) {
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case 0:
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init_fcc1_ioports(fpi);
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break;
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case 1:
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init_fcc2_ioports(fpi);
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break;
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default:
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printk(KERN_ERR "init_fcc_ioports: invalid FCC number\n");
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return;
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}
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}
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static void init_scc1_uart_ioports(struct fs_uart_platform_info *data)
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{
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cpm2_map_t *immap = ioremap(get_immrbase(), sizeof(cpm2_map_t));
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/* SCC1 is only on port D */
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setbits32(&immap->im_ioport.iop_ppard, 0x00000003);
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clrbits32(&immap->im_ioport.iop_psord, 0x00000001);
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setbits32(&immap->im_ioport.iop_psord, 0x00000002);
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clrbits32(&immap->im_ioport.iop_pdird, 0x00000001);
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setbits32(&immap->im_ioport.iop_pdird, 0x00000002);
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clrbits32(&immap->im_cpmux.cmx_scr, (0x00000007 << (4 - data->clk_tx)));
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clrbits32(&immap->im_cpmux.cmx_scr, (0x00000038 << (4 - data->clk_rx)));
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setbits32(&immap->im_cpmux.cmx_scr,
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((data->clk_tx - 1) << (4 - data->clk_tx)));
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setbits32(&immap->im_cpmux.cmx_scr,
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((data->clk_rx - 1) << (4 - data->clk_rx)));
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iounmap(immap);
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}
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static void init_scc4_uart_ioports(struct fs_uart_platform_info *data)
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{
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cpm2_map_t *immap = ioremap(get_immrbase(), sizeof(cpm2_map_t));
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setbits32(&immap->im_ioport.iop_ppard, 0x00000600);
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clrbits32(&immap->im_ioport.iop_psord, 0x00000600);
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clrbits32(&immap->im_ioport.iop_pdird, 0x00000200);
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setbits32(&immap->im_ioport.iop_pdird, 0x00000400);
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clrbits32(&immap->im_cpmux.cmx_scr, (0x00000007 << (4 - data->clk_tx)));
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clrbits32(&immap->im_cpmux.cmx_scr, (0x00000038 << (4 - data->clk_rx)));
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setbits32(&immap->im_cpmux.cmx_scr,
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((data->clk_tx - 1) << (4 - data->clk_tx)));
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setbits32(&immap->im_cpmux.cmx_scr,
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((data->clk_rx - 1) << (4 - data->clk_rx)));
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iounmap(immap);
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}
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void init_scc_ioports(struct fs_uart_platform_info *data)
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{
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int scc_no = fs_get_scc_index(data->fs_no);
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switch (scc_no) {
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case 0:
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init_scc1_uart_ioports(data);
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data->brg = data->clk_rx;
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break;
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case 3:
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init_scc4_uart_ioports(data);
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data->brg = data->clk_rx;
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break;
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default:
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printk(KERN_ERR "init_scc_ioports: invalid SCC number\n");
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return;
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}
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}
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void __init m82xx_board_setup(void)
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{
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cpm2_map_t *immap = ioremap(get_immrbase(), sizeof(cpm2_map_t));
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struct device_node *np;
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struct resource r;
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u32 *bcsr;
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np = of_find_node_by_type(NULL, "memory");
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if (!np) {
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printk(KERN_INFO "No memory node in device tree\n");
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return;
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}
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if (of_address_to_resource(np, 1, &r)) {
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printk(KERN_INFO "No memory reg property [1] in devicetree\n");
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return;
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}
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of_node_put(np);
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bcsr = ioremap(r.start + 4, sizeof(u32));
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/* Enable the 2nd UART port */
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clrbits32(bcsr, BCSR1_RS232_EN2);
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#ifdef CONFIG_SERIAL_CPM_SCC1
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clrbits32((u32 *) & immap->im_scc[0].scc_sccm,
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UART_SCCM_TX | UART_SCCM_RX);
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clrbits32((u32 *) & immap->im_scc[0].scc_gsmrl,
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SCC_GSMRL_ENR | SCC_GSMRL_ENT);
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#endif
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#ifdef CONFIG_SERIAL_CPM_SCC2
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clrbits32((u32 *) & immap->im_scc[1].scc_sccm,
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UART_SCCM_TX | UART_SCCM_RX);
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clrbits32((u32 *) & immap->im_scc[1].scc_gsmrl,
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SCC_GSMRL_ENR | SCC_GSMRL_ENT);
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#endif
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#ifdef CONFIG_SERIAL_CPM_SCC3
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clrbits32((u32 *) & immap->im_scc[2].scc_sccm,
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UART_SCCM_TX | UART_SCCM_RX);
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clrbits32((u32 *) & immap->im_scc[2].scc_gsmrl,
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SCC_GSMRL_ENR | SCC_GSMRL_ENT);
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#endif
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#ifdef CONFIG_SERIAL_CPM_SCC4
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clrbits32((u32 *) & immap->im_scc[3].scc_sccm,
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UART_SCCM_TX | UART_SCCM_RX);
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clrbits32((u32 *) & immap->im_scc[3].scc_gsmrl,
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SCC_GSMRL_ENR | SCC_GSMRL_ENT);
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#endif
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iounmap(bcsr);
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iounmap(immap);
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}
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#ifdef CONFIG_PCI
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static void m82xx_pci_mask_irq(unsigned int irq)
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{
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int bit = irq - pci_int_base;
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*pci_regs.pci_int_mask_reg |= (1 << (31 - bit));
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return;
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}
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static void m82xx_pci_unmask_irq(unsigned int irq)
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{
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int bit = irq - pci_int_base;
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*pci_regs.pci_int_mask_reg &= ~(1 << (31 - bit));
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return;
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}
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static void m82xx_pci_mask_and_ack(unsigned int irq)
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{
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int bit = irq - pci_int_base;
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*pci_regs.pci_int_mask_reg |= (1 << (31 - bit));
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return;
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}
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static void m82xx_pci_end_irq(unsigned int irq)
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{
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int bit = irq - pci_int_base;
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*pci_regs.pci_int_mask_reg &= ~(1 << (31 - bit));
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return;
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}
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struct hw_interrupt_type m82xx_pci_ic = {
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.typename = "MPC82xx ADS PCI",
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.name = "MPC82xx ADS PCI",
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.enable = m82xx_pci_unmask_irq,
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.disable = m82xx_pci_mask_irq,
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.ack = m82xx_pci_mask_and_ack,
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.end = m82xx_pci_end_irq,
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.mask = m82xx_pci_mask_irq,
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.mask_ack = m82xx_pci_mask_and_ack,
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.unmask = m82xx_pci_unmask_irq,
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.eoi = m82xx_pci_end_irq,
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};
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static void
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m82xx_pci_irq_demux(unsigned int irq, struct irq_desc *desc)
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{
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unsigned long stat, mask, pend;
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int bit;
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for (;;) {
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stat = *pci_regs.pci_int_stat_reg;
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mask = *pci_regs.pci_int_mask_reg;
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pend = stat & ~mask & 0xf0000000;
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if (!pend)
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break;
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for (bit = 0; pend != 0; ++bit, pend <<= 1) {
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if (pend & 0x80000000)
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__do_IRQ(pci_int_base + bit);
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}
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}
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}
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static int pci_pic_host_match(struct irq_host *h, struct device_node *node)
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{
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return node == pci_pic_node;
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}
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static int pci_pic_host_map(struct irq_host *h, unsigned int virq,
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irq_hw_number_t hw)
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{
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get_irq_desc(virq)->status |= IRQ_LEVEL;
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set_irq_chip(virq, &m82xx_pci_ic);
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return 0;
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}
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static void pci_host_unmap(struct irq_host *h, unsigned int virq)
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{
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/* remove chip and handler */
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set_irq_chip(virq, NULL);
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}
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static struct irq_host_ops pci_pic_host_ops = {
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.match = pci_pic_host_match,
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.map = pci_pic_host_map,
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.unmap = pci_host_unmap,
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};
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void m82xx_pci_init_irq(void)
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{
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int irq;
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cpm2_map_t *immap;
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struct device_node *np;
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struct resource r;
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const u32 *regs;
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unsigned int size;
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const u32 *irq_map;
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int i;
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unsigned int irq_max, irq_min;
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if ((np = of_find_node_by_type(NULL, "soc")) == NULL) {
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printk(KERN_INFO "No SOC node in device tree\n");
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return;
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}
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memset(&r, 0, sizeof(r));
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if (of_address_to_resource(np, 0, &r)) {
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printk(KERN_INFO "No SOC reg property in device tree\n");
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return;
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}
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immap = ioremap(r.start, sizeof(*immap));
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of_node_put(np);
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/* install the demultiplexer for the PCI cascade interrupt */
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np = of_find_node_by_type(NULL, "pci");
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if (!np) {
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printk(KERN_INFO "No pci node on device tree\n");
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iounmap(immap);
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return;
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}
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irq_map = get_property(np, "interrupt-map", &size);
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if ((!irq_map) || (size <= 7)) {
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printk(KERN_INFO "No interrupt-map property of pci node\n");
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iounmap(immap);
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return;
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}
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size /= sizeof(irq_map[0]);
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for (i = 0, irq_max = 0, irq_min = 512; i < size; i += 7, irq_map += 7) {
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if (irq_map[5] < irq_min)
|
|
irq_min = irq_map[5];
|
|
if (irq_map[5] > irq_max)
|
|
irq_max = irq_map[5];
|
|
}
|
|
pci_int_base = irq_min;
|
|
irq = irq_of_parse_and_map(np, 0);
|
|
set_irq_chained_handler(irq, m82xx_pci_irq_demux);
|
|
of_node_put(np);
|
|
np = of_find_node_by_type(NULL, "pci-pic");
|
|
if (!np) {
|
|
printk(KERN_INFO "No pci pic node on device tree\n");
|
|
iounmap(immap);
|
|
return;
|
|
}
|
|
pci_pic_node = of_node_get(np);
|
|
/* PCI interrupt controller registers: status and mask */
|
|
regs = get_property(np, "reg", &size);
|
|
if ((!regs) || (size <= 2)) {
|
|
printk(KERN_INFO "No reg property in pci pic node\n");
|
|
iounmap(immap);
|
|
return;
|
|
}
|
|
pci_regs.pci_int_stat_reg =
|
|
ioremap(regs[0], sizeof(*pci_regs.pci_int_stat_reg));
|
|
pci_regs.pci_int_mask_reg =
|
|
ioremap(regs[1], sizeof(*pci_regs.pci_int_mask_reg));
|
|
of_node_put(np);
|
|
/* configure chip select for PCI interrupt controller */
|
|
immap->im_memctl.memc_br3 = regs[0] | 0x00001801;
|
|
immap->im_memctl.memc_or3 = 0xffff8010;
|
|
/* make PCI IRQ level sensitive */
|
|
immap->im_intctl.ic_siexr &= ~(1 << (14 - (irq - SIU_INT_IRQ1)));
|
|
|
|
/* mask all PCI interrupts */
|
|
*pci_regs.pci_int_mask_reg |= 0xfff00000;
|
|
iounmap(immap);
|
|
pci_pic_host =
|
|
irq_alloc_host(IRQ_HOST_MAP_LINEAR, irq_max - irq_min + 1,
|
|
&pci_pic_host_ops, irq_max + 1);
|
|
return;
|
|
}
|
|
|
|
static int m82xx_pci_exclude_device(u_char bus, u_char devfn)
|
|
{
|
|
if (bus == 0 && PCI_SLOT(devfn) == 0)
|
|
return PCIBIOS_DEVICE_NOT_FOUND;
|
|
else
|
|
return PCIBIOS_SUCCESSFUL;
|
|
}
|
|
|
|
void __init add_bridge(struct device_node *np)
|
|
{
|
|
int len;
|
|
struct pci_controller *hose;
|
|
struct resource r;
|
|
const int *bus_range;
|
|
const void *ptr;
|
|
|
|
memset(&r, 0, sizeof(r));
|
|
if (of_address_to_resource(np, 0, &r)) {
|
|
printk(KERN_INFO "No PCI reg property in device tree\n");
|
|
return;
|
|
}
|
|
if (!(ptr = get_property(np, "clock-frequency", NULL))) {
|
|
printk(KERN_INFO "No clock-frequency property in PCI node");
|
|
return;
|
|
}
|
|
pci_clk_frq = *(uint *) ptr;
|
|
of_node_put(np);
|
|
bus_range = get_property(np, "bus-range", &len);
|
|
if (bus_range == NULL || len < 2 * sizeof(int)) {
|
|
printk(KERN_WARNING "Can't get bus-range for %s, assume"
|
|
" bus 0\n", np->full_name);
|
|
}
|
|
|
|
pci_assign_all_buses = 1;
|
|
|
|
hose = pcibios_alloc_controller();
|
|
|
|
if (!hose)
|
|
return;
|
|
|
|
hose->arch_data = np;
|
|
hose->set_cfg_type = 1;
|
|
|
|
hose->first_busno = bus_range ? bus_range[0] : 0;
|
|
hose->last_busno = bus_range ? bus_range[1] : 0xff;
|
|
hose->bus_offset = 0;
|
|
|
|
hose->set_cfg_type = 1;
|
|
|
|
setup_indirect_pci(hose,
|
|
r.start + offsetof(pci_cpm2_t, pci_cfg_addr),
|
|
r.start + offsetof(pci_cpm2_t, pci_cfg_data));
|
|
|
|
pci_process_bridge_OF_ranges(hose, np, 1);
|
|
}
|
|
#endif
|
|
|
|
/*
|
|
* Setup the architecture
|
|
*/
|
|
static void __init mpc82xx_ads_setup_arch(void)
|
|
{
|
|
#ifdef CONFIG_PCI
|
|
struct device_node *np;
|
|
#endif
|
|
|
|
if (ppc_md.progress)
|
|
ppc_md.progress("mpc82xx_ads_setup_arch()", 0);
|
|
cpm2_reset();
|
|
|
|
/* Map I/O region to a 256MB BAT */
|
|
|
|
m82xx_board_setup();
|
|
|
|
#ifdef CONFIG_PCI
|
|
ppc_md.pci_exclude_device = m82xx_pci_exclude_device;
|
|
for (np = NULL; (np = of_find_node_by_type(np, "pci")) != NULL;)
|
|
add_bridge(np);
|
|
|
|
of_node_put(np);
|
|
#endif
|
|
|
|
#ifdef CONFIG_ROOT_NFS
|
|
ROOT_DEV = Root_NFS;
|
|
#else
|
|
ROOT_DEV = Root_HDA1;
|
|
#endif
|
|
|
|
if (ppc_md.progress)
|
|
ppc_md.progress("mpc82xx_ads_setup_arch(), finish", 0);
|
|
}
|
|
|
|
/*
|
|
* Called very early, device-tree isn't unflattened
|
|
*/
|
|
static int __init mpc82xx_ads_probe(void)
|
|
{
|
|
/* We always match for now, eventually we should look at
|
|
* the flat dev tree to ensure this is the board we are
|
|
* supposed to run on
|
|
*/
|
|
return 1;
|
|
}
|
|
|
|
#define RMR_CSRE 0x00000001
|
|
static void m82xx_restart(char *cmd)
|
|
{
|
|
__volatile__ unsigned char dummy;
|
|
|
|
local_irq_disable();
|
|
((cpm2_map_t *) cpm2_immr)->im_clkrst.car_rmr |= RMR_CSRE;
|
|
|
|
/* Clear the ME,EE,IR & DR bits in MSR to cause checkstop */
|
|
mtmsr(mfmsr() & ~(MSR_ME | MSR_EE | MSR_IR | MSR_DR));
|
|
dummy = ((cpm2_map_t *) cpm2_immr)->im_clkrst.res[0];
|
|
printk("Restart failed\n");
|
|
while (1) ;
|
|
}
|
|
|
|
static void m82xx_halt(void)
|
|
{
|
|
local_irq_disable();
|
|
while (1) ;
|
|
}
|
|
|
|
define_machine(mpc82xx_ads)
|
|
{
|
|
.name = "MPC82xx ADS",
|
|
.probe = mpc82xx_ads_probe,
|
|
.setup_arch = mpc82xx_ads_setup_arch,
|
|
.init_IRQ = mpc82xx_ads_pic_init,
|
|
.show_cpuinfo = mpc82xx_ads_show_cpuinfo,
|
|
.get_irq = cpm2_get_irq,
|
|
.calibrate_decr = m82xx_calibrate_decr,
|
|
.restart = m82xx_restart,.halt = m82xx_halt,
|
|
};
|