538 строки
15 KiB
C
538 строки
15 KiB
C
/*
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* arch/arm/include/asm/cacheflush.h
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*
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* Copyright (C) 1999-2002 Russell King
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef _ASMARM_CACHEFLUSH_H
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#define _ASMARM_CACHEFLUSH_H
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#include <linux/sched.h>
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#include <linux/mm.h>
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#include <asm/glue.h>
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#include <asm/shmparam.h>
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#define CACHE_COLOUR(vaddr) ((vaddr & (SHMLBA - 1)) >> PAGE_SHIFT)
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/*
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* Cache Model
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* ===========
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*/
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#undef _CACHE
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#undef MULTI_CACHE
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#if defined(CONFIG_CPU_CACHE_V3)
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# ifdef _CACHE
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# define MULTI_CACHE 1
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# else
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# define _CACHE v3
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# endif
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#endif
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#if defined(CONFIG_CPU_CACHE_V4)
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# ifdef _CACHE
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# define MULTI_CACHE 1
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# else
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# define _CACHE v4
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# endif
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#endif
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#if defined(CONFIG_CPU_ARM920T) || defined(CONFIG_CPU_ARM922T) || \
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defined(CONFIG_CPU_ARM925T) || defined(CONFIG_CPU_ARM1020)
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# define MULTI_CACHE 1
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#endif
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#if defined(CONFIG_CPU_ARM926T)
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# ifdef _CACHE
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# define MULTI_CACHE 1
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# else
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# define _CACHE arm926
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# endif
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#endif
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#if defined(CONFIG_CPU_ARM940T)
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# ifdef _CACHE
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# define MULTI_CACHE 1
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# else
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# define _CACHE arm940
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# endif
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#endif
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#if defined(CONFIG_CPU_ARM946E)
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# ifdef _CACHE
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# define MULTI_CACHE 1
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# else
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# define _CACHE arm946
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# endif
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#endif
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#if defined(CONFIG_CPU_CACHE_V4WB)
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# ifdef _CACHE
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# define MULTI_CACHE 1
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# else
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# define _CACHE v4wb
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# endif
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#endif
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#if defined(CONFIG_CPU_XSCALE)
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# ifdef _CACHE
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# define MULTI_CACHE 1
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# else
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# define _CACHE xscale
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# endif
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#endif
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#if defined(CONFIG_CPU_XSC3)
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# ifdef _CACHE
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# define MULTI_CACHE 1
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# else
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# define _CACHE xsc3
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# endif
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#endif
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#if defined(CONFIG_CPU_FEROCEON)
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# define MULTI_CACHE 1
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#endif
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#if defined(CONFIG_CPU_V6)
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//# ifdef _CACHE
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# define MULTI_CACHE 1
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//# else
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//# define _CACHE v6
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//# endif
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#endif
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#if defined(CONFIG_CPU_V7)
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//# ifdef _CACHE
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# define MULTI_CACHE 1
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//# else
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//# define _CACHE v7
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//# endif
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#endif
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#if !defined(_CACHE) && !defined(MULTI_CACHE)
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#error Unknown cache maintainence model
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#endif
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/*
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* This flag is used to indicate that the page pointed to by a pte
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* is dirty and requires cleaning before returning it to the user.
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*/
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#define PG_dcache_dirty PG_arch_1
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/*
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* MM Cache Management
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* ===================
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*
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* The arch/arm/mm/cache-*.S and arch/arm/mm/proc-*.S files
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* implement these methods.
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*
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* Start addresses are inclusive and end addresses are exclusive;
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* start addresses should be rounded down, end addresses up.
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*
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* See Documentation/cachetlb.txt for more information.
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* Please note that the implementation of these, and the required
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* effects are cache-type (VIVT/VIPT/PIPT) specific.
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*
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* flush_cache_kern_all()
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*
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* Unconditionally clean and invalidate the entire cache.
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*
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* flush_cache_user_mm(mm)
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*
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* Clean and invalidate all user space cache entries
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* before a change of page tables.
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*
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* flush_cache_user_range(start, end, flags)
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*
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* Clean and invalidate a range of cache entries in the
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* specified address space before a change of page tables.
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* - start - user start address (inclusive, page aligned)
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* - end - user end address (exclusive, page aligned)
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* - flags - vma->vm_flags field
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*
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* coherent_kern_range(start, end)
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*
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* Ensure coherency between the Icache and the Dcache in the
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* region described by start, end. If you have non-snooping
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* Harvard caches, you need to implement this function.
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* - start - virtual start address
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* - end - virtual end address
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*
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* DMA Cache Coherency
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* ===================
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*
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* dma_inv_range(start, end)
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*
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* Invalidate (discard) the specified virtual address range.
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* May not write back any entries. If 'start' or 'end'
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* are not cache line aligned, those lines must be written
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* back.
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* - start - virtual start address
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* - end - virtual end address
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*
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* dma_clean_range(start, end)
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*
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* Clean (write back) the specified virtual address range.
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* - start - virtual start address
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* - end - virtual end address
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*
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* dma_flush_range(start, end)
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*
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* Clean and invalidate the specified virtual address range.
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* - start - virtual start address
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* - end - virtual end address
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*/
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struct cpu_cache_fns {
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void (*flush_kern_all)(void);
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void (*flush_user_all)(void);
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void (*flush_user_range)(unsigned long, unsigned long, unsigned int);
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void (*coherent_kern_range)(unsigned long, unsigned long);
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void (*coherent_user_range)(unsigned long, unsigned long);
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void (*flush_kern_dcache_page)(void *);
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void (*dma_inv_range)(const void *, const void *);
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void (*dma_clean_range)(const void *, const void *);
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void (*dma_flush_range)(const void *, const void *);
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};
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struct outer_cache_fns {
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void (*inv_range)(unsigned long, unsigned long);
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void (*clean_range)(unsigned long, unsigned long);
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void (*flush_range)(unsigned long, unsigned long);
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};
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/*
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* Select the calling method
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*/
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#ifdef MULTI_CACHE
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extern struct cpu_cache_fns cpu_cache;
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#define __cpuc_flush_kern_all cpu_cache.flush_kern_all
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#define __cpuc_flush_user_all cpu_cache.flush_user_all
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#define __cpuc_flush_user_range cpu_cache.flush_user_range
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#define __cpuc_coherent_kern_range cpu_cache.coherent_kern_range
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#define __cpuc_coherent_user_range cpu_cache.coherent_user_range
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#define __cpuc_flush_dcache_page cpu_cache.flush_kern_dcache_page
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/*
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* These are private to the dma-mapping API. Do not use directly.
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* Their sole purpose is to ensure that data held in the cache
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* is visible to DMA, or data written by DMA to system memory is
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* visible to the CPU.
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*/
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#define dmac_inv_range cpu_cache.dma_inv_range
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#define dmac_clean_range cpu_cache.dma_clean_range
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#define dmac_flush_range cpu_cache.dma_flush_range
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#else
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#define __cpuc_flush_kern_all __glue(_CACHE,_flush_kern_cache_all)
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#define __cpuc_flush_user_all __glue(_CACHE,_flush_user_cache_all)
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#define __cpuc_flush_user_range __glue(_CACHE,_flush_user_cache_range)
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#define __cpuc_coherent_kern_range __glue(_CACHE,_coherent_kern_range)
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#define __cpuc_coherent_user_range __glue(_CACHE,_coherent_user_range)
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#define __cpuc_flush_dcache_page __glue(_CACHE,_flush_kern_dcache_page)
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extern void __cpuc_flush_kern_all(void);
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extern void __cpuc_flush_user_all(void);
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extern void __cpuc_flush_user_range(unsigned long, unsigned long, unsigned int);
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extern void __cpuc_coherent_kern_range(unsigned long, unsigned long);
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extern void __cpuc_coherent_user_range(unsigned long, unsigned long);
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extern void __cpuc_flush_dcache_page(void *);
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/*
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* These are private to the dma-mapping API. Do not use directly.
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* Their sole purpose is to ensure that data held in the cache
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* is visible to DMA, or data written by DMA to system memory is
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* visible to the CPU.
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*/
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#define dmac_inv_range __glue(_CACHE,_dma_inv_range)
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#define dmac_clean_range __glue(_CACHE,_dma_clean_range)
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#define dmac_flush_range __glue(_CACHE,_dma_flush_range)
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extern void dmac_inv_range(const void *, const void *);
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extern void dmac_clean_range(const void *, const void *);
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extern void dmac_flush_range(const void *, const void *);
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#endif
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#ifdef CONFIG_OUTER_CACHE
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extern struct outer_cache_fns outer_cache;
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static inline void outer_inv_range(unsigned long start, unsigned long end)
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{
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if (outer_cache.inv_range)
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outer_cache.inv_range(start, end);
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}
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static inline void outer_clean_range(unsigned long start, unsigned long end)
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{
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if (outer_cache.clean_range)
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outer_cache.clean_range(start, end);
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}
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static inline void outer_flush_range(unsigned long start, unsigned long end)
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{
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if (outer_cache.flush_range)
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outer_cache.flush_range(start, end);
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}
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#else
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static inline void outer_inv_range(unsigned long start, unsigned long end)
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{ }
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static inline void outer_clean_range(unsigned long start, unsigned long end)
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{ }
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static inline void outer_flush_range(unsigned long start, unsigned long end)
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{ }
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#endif
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/*
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* flush_cache_vmap() is used when creating mappings (eg, via vmap,
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* vmalloc, ioremap etc) in kernel space for pages. Since the
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* direct-mappings of these pages may contain cached data, we need
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* to do a full cache flush to ensure that writebacks don't corrupt
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* data placed into these pages via the new mappings.
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*/
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#define flush_cache_vmap(start, end) flush_cache_all()
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#define flush_cache_vunmap(start, end) flush_cache_all()
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/*
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* Copy user data from/to a page which is mapped into a different
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* processes address space. Really, we want to allow our "user
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* space" model to handle this.
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*/
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#define copy_to_user_page(vma, page, vaddr, dst, src, len) \
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do { \
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memcpy(dst, src, len); \
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flush_ptrace_access(vma, page, vaddr, dst, len, 1);\
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} while (0)
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#define copy_from_user_page(vma, page, vaddr, dst, src, len) \
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do { \
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memcpy(dst, src, len); \
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} while (0)
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/*
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* Convert calls to our calling convention.
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*/
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#define flush_cache_all() __cpuc_flush_kern_all()
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#ifndef CONFIG_CPU_CACHE_VIPT
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static inline void flush_cache_mm(struct mm_struct *mm)
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{
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if (cpu_isset(smp_processor_id(), mm->cpu_vm_mask))
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__cpuc_flush_user_all();
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}
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static inline void
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flush_cache_range(struct vm_area_struct *vma, unsigned long start, unsigned long end)
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{
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if (cpu_isset(smp_processor_id(), vma->vm_mm->cpu_vm_mask))
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__cpuc_flush_user_range(start & PAGE_MASK, PAGE_ALIGN(end),
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vma->vm_flags);
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}
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static inline void
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flush_cache_page(struct vm_area_struct *vma, unsigned long user_addr, unsigned long pfn)
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{
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if (cpu_isset(smp_processor_id(), vma->vm_mm->cpu_vm_mask)) {
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unsigned long addr = user_addr & PAGE_MASK;
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__cpuc_flush_user_range(addr, addr + PAGE_SIZE, vma->vm_flags);
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}
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}
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static inline void
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flush_ptrace_access(struct vm_area_struct *vma, struct page *page,
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unsigned long uaddr, void *kaddr,
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unsigned long len, int write)
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{
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if (cpu_isset(smp_processor_id(), vma->vm_mm->cpu_vm_mask)) {
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unsigned long addr = (unsigned long)kaddr;
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__cpuc_coherent_kern_range(addr, addr + len);
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}
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}
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#else
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extern void flush_cache_mm(struct mm_struct *mm);
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extern void flush_cache_range(struct vm_area_struct *vma, unsigned long start, unsigned long end);
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extern void flush_cache_page(struct vm_area_struct *vma, unsigned long user_addr, unsigned long pfn);
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extern void flush_ptrace_access(struct vm_area_struct *vma, struct page *page,
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unsigned long uaddr, void *kaddr,
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unsigned long len, int write);
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#endif
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#define flush_cache_dup_mm(mm) flush_cache_mm(mm)
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/*
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* flush_cache_user_range is used when we want to ensure that the
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* Harvard caches are synchronised for the user space address range.
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* This is used for the ARM private sys_cacheflush system call.
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*/
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#define flush_cache_user_range(vma,start,end) \
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__cpuc_coherent_user_range((start) & PAGE_MASK, PAGE_ALIGN(end))
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/*
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* Perform necessary cache operations to ensure that data previously
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* stored within this range of addresses can be executed by the CPU.
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*/
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#define flush_icache_range(s,e) __cpuc_coherent_kern_range(s,e)
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/*
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* Perform necessary cache operations to ensure that the TLB will
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* see data written in the specified area.
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*/
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#define clean_dcache_area(start,size) cpu_dcache_clean_area(start, size)
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/*
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* flush_dcache_page is used when the kernel has written to the page
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* cache page at virtual address page->virtual.
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*
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* If this page isn't mapped (ie, page_mapping == NULL), or it might
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* have userspace mappings, then we _must_ always clean + invalidate
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* the dcache entries associated with the kernel mapping.
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*
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* Otherwise we can defer the operation, and clean the cache when we are
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* about to change to user space. This is the same method as used on SPARC64.
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* See update_mmu_cache for the user space part.
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*/
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extern void flush_dcache_page(struct page *);
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extern void __flush_dcache_page(struct address_space *mapping, struct page *page);
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static inline void __flush_icache_all(void)
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{
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asm("mcr p15, 0, %0, c7, c5, 0 @ invalidate I-cache\n"
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:
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: "r" (0));
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}
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#define ARCH_HAS_FLUSH_ANON_PAGE
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static inline void flush_anon_page(struct vm_area_struct *vma,
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struct page *page, unsigned long vmaddr)
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{
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extern void __flush_anon_page(struct vm_area_struct *vma,
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struct page *, unsigned long);
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if (PageAnon(page))
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__flush_anon_page(vma, page, vmaddr);
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}
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#define flush_dcache_mmap_lock(mapping) \
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spin_lock_irq(&(mapping)->tree_lock)
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#define flush_dcache_mmap_unlock(mapping) \
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spin_unlock_irq(&(mapping)->tree_lock)
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#define flush_icache_user_range(vma,page,addr,len) \
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flush_dcache_page(page)
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/*
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* We don't appear to need to do anything here. In fact, if we did, we'd
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* duplicate cache flushing elsewhere performed by flush_dcache_page().
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*/
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#define flush_icache_page(vma,page) do { } while (0)
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static inline void flush_ioremap_region(unsigned long phys, void __iomem *virt,
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unsigned offset, size_t size)
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{
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const void *start = (void __force *)virt + offset;
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dmac_inv_range(start, start + size);
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}
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#define __cacheid_present(val) (val != read_cpuid(CPUID_ID))
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#define __cacheid_type_v7(val) ((val & (7 << 29)) == (4 << 29))
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#define __cacheid_vivt_prev7(val) ((val & (15 << 25)) != (14 << 25))
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#define __cacheid_vipt_prev7(val) ((val & (15 << 25)) == (14 << 25))
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#define __cacheid_vipt_nonaliasing_prev7(val) ((val & (15 << 25 | 1 << 23)) == (14 << 25))
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#define __cacheid_vipt_aliasing_prev7(val) ((val & (15 << 25 | 1 << 23)) == (14 << 25 | 1 << 23))
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#define __cacheid_vivt(val) (__cacheid_type_v7(val) ? 0 : __cacheid_vivt_prev7(val))
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#define __cacheid_vipt(val) (__cacheid_type_v7(val) ? 1 : __cacheid_vipt_prev7(val))
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#define __cacheid_vipt_nonaliasing(val) (__cacheid_type_v7(val) ? 1 : __cacheid_vipt_nonaliasing_prev7(val))
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#define __cacheid_vipt_aliasing(val) (__cacheid_type_v7(val) ? 0 : __cacheid_vipt_aliasing_prev7(val))
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#define __cacheid_vivt_asid_tagged_instr(val) (__cacheid_type_v7(val) ? ((val & (3 << 14)) == (1 << 14)) : 0)
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#if defined(CONFIG_CPU_CACHE_VIVT) && !defined(CONFIG_CPU_CACHE_VIPT)
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/*
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* VIVT caches only
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*/
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#define cache_is_vivt() 1
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#define cache_is_vipt() 0
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#define cache_is_vipt_nonaliasing() 0
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#define cache_is_vipt_aliasing() 0
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#define icache_is_vivt_asid_tagged() 0
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#elif !defined(CONFIG_CPU_CACHE_VIVT) && defined(CONFIG_CPU_CACHE_VIPT)
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/*
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* VIPT caches only
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*/
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#define cache_is_vivt() 0
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#define cache_is_vipt() 1
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#define cache_is_vipt_nonaliasing() \
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({ \
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unsigned int __val = read_cpuid(CPUID_CACHETYPE); \
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__cacheid_vipt_nonaliasing(__val); \
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})
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#define cache_is_vipt_aliasing() \
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({ \
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unsigned int __val = read_cpuid(CPUID_CACHETYPE); \
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__cacheid_vipt_aliasing(__val); \
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})
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#define icache_is_vivt_asid_tagged() \
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({ \
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unsigned int __val = read_cpuid(CPUID_CACHETYPE); \
|
|
__cacheid_vivt_asid_tagged_instr(__val); \
|
|
})
|
|
|
|
#else
|
|
/*
|
|
* VIVT or VIPT caches. Note that this is unreliable since ARM926
|
|
* and V6 CPUs satisfy the "(val & (15 << 25)) == (14 << 25)" test.
|
|
* There's no way to tell from the CacheType register what type (!)
|
|
* the cache is.
|
|
*/
|
|
#define cache_is_vivt() \
|
|
({ \
|
|
unsigned int __val = read_cpuid(CPUID_CACHETYPE); \
|
|
(!__cacheid_present(__val)) || __cacheid_vivt(__val); \
|
|
})
|
|
|
|
#define cache_is_vipt() \
|
|
({ \
|
|
unsigned int __val = read_cpuid(CPUID_CACHETYPE); \
|
|
__cacheid_present(__val) && __cacheid_vipt(__val); \
|
|
})
|
|
|
|
#define cache_is_vipt_nonaliasing() \
|
|
({ \
|
|
unsigned int __val = read_cpuid(CPUID_CACHETYPE); \
|
|
__cacheid_present(__val) && \
|
|
__cacheid_vipt_nonaliasing(__val); \
|
|
})
|
|
|
|
#define cache_is_vipt_aliasing() \
|
|
({ \
|
|
unsigned int __val = read_cpuid(CPUID_CACHETYPE); \
|
|
__cacheid_present(__val) && \
|
|
__cacheid_vipt_aliasing(__val); \
|
|
})
|
|
|
|
#define icache_is_vivt_asid_tagged() \
|
|
({ \
|
|
unsigned int __val = read_cpuid(CPUID_CACHETYPE); \
|
|
__cacheid_present(__val) && \
|
|
__cacheid_vivt_asid_tagged_instr(__val); \
|
|
})
|
|
|
|
#endif
|
|
|
|
#endif
|