128 строки
4.1 KiB
C
128 строки
4.1 KiB
C
/*
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* rcar_du_group.c -- R-Car Display Unit Channels Pair
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*
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* Copyright (C) 2013 Renesas Corporation
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*
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* Contact: Laurent Pinchart (laurent.pinchart@ideasonboard.com)
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*/
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/*
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* The R8A7779 DU is split in per-CRTC resources (scan-out engine, blending
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* unit, timings generator, ...) and device-global resources (start/stop
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* control, planes, ...) shared between the two CRTCs.
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*
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* The R8A7790 introduced a third CRTC with its own set of global resources.
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* This would be modeled as two separate DU device instances if it wasn't for
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* a handful or resources that are shared between the three CRTCs (mostly
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* related to input and output routing). For this reason the R8A7790 DU must be
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* modeled as a single device with three CRTCs, two sets of "semi-global"
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* resources, and a few device-global resources.
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*
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* The rcar_du_group object is a driver specific object, without any real
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* counterpart in the DU documentation, that models those semi-global resources.
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*/
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#include <linux/io.h>
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#include "rcar_du_drv.h"
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#include "rcar_du_group.h"
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#include "rcar_du_regs.h"
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static u32 rcar_du_group_read(struct rcar_du_group *rgrp, u32 reg)
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{
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return rcar_du_read(rgrp->dev, rgrp->mmio_offset + reg);
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}
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static void rcar_du_group_write(struct rcar_du_group *rgrp, u32 reg, u32 data)
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{
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rcar_du_write(rgrp->dev, rgrp->mmio_offset + reg, data);
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}
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static void rcar_du_group_setup(struct rcar_du_group *rgrp)
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{
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/* Enable extended features */
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rcar_du_group_write(rgrp, DEFR, DEFR_CODE | DEFR_DEFE);
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rcar_du_group_write(rgrp, DEFR2, DEFR2_CODE | DEFR2_DEFE2G);
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rcar_du_group_write(rgrp, DEFR3, DEFR3_CODE | DEFR3_DEFE3);
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rcar_du_group_write(rgrp, DEFR4, DEFR4_CODE);
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rcar_du_group_write(rgrp, DEFR5, DEFR5_CODE | DEFR5_DEFE5);
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/* Use DS1PR and DS2PR to configure planes priorities and connects the
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* superposition 0 to DU0 pins. DU1 pins will be configured dynamically.
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*/
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rcar_du_group_write(rgrp, DORCR, DORCR_PG1D_DS1 | DORCR_DPRS);
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}
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/*
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* rcar_du_group_get - Acquire a reference to the DU channels group
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*
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* Acquiring the first reference setups core registers. A reference must be held
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* before accessing any hardware registers.
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*
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* This function must be called with the DRM mode_config lock held.
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*
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* Return 0 in case of success or a negative error code otherwise.
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*/
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int rcar_du_group_get(struct rcar_du_group *rgrp)
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{
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if (rgrp->use_count)
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goto done;
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rcar_du_group_setup(rgrp);
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done:
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rgrp->use_count++;
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return 0;
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}
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/*
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* rcar_du_group_put - Release a reference to the DU
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*
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* This function must be called with the DRM mode_config lock held.
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*/
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void rcar_du_group_put(struct rcar_du_group *rgrp)
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{
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--rgrp->use_count;
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}
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static void __rcar_du_group_start_stop(struct rcar_du_group *rgrp, bool start)
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{
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rcar_du_group_write(rgrp, DSYSR,
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(rcar_du_group_read(rgrp, DSYSR) & ~(DSYSR_DRES | DSYSR_DEN)) |
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(start ? DSYSR_DEN : DSYSR_DRES));
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}
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void rcar_du_group_start_stop(struct rcar_du_group *rgrp, bool start)
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{
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/* Many of the configuration bits are only updated when the display
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* reset (DRES) bit in DSYSR is set to 1, disabling *both* CRTCs. Some
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* of those bits could be pre-configured, but others (especially the
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* bits related to plane assignment to display timing controllers) need
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* to be modified at runtime.
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*
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* Restart the display controller if a start is requested. Sorry for the
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* flicker. It should be possible to move most of the "DRES-update" bits
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* setup to driver initialization time and minimize the number of cases
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* when the display controller will have to be restarted.
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*/
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if (start) {
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if (rgrp->used_crtcs++ != 0)
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__rcar_du_group_start_stop(rgrp, false);
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__rcar_du_group_start_stop(rgrp, true);
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} else {
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if (--rgrp->used_crtcs == 0)
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__rcar_du_group_start_stop(rgrp, false);
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}
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}
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void rcar_du_group_restart(struct rcar_du_group *rgrp)
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{
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__rcar_du_group_start_stop(rgrp, false);
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__rcar_du_group_start_stop(rgrp, true);
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}
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