608 строки
17 KiB
C
608 строки
17 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2018 Marvell
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*
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* Author: Thomas Petazzoni <thomas.petazzoni@bootlin.com>
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*
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* This file helps PCI controller drivers implement a fake root port
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* PCI bridge when the HW doesn't provide such a root port PCI
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* bridge.
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*
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* It emulates a PCI bridge by providing a fake PCI configuration
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* space (and optionally a PCIe capability configuration space) in
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* memory. By default the read/write operations simply read and update
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* this fake configuration space in memory. However, PCI controller
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* drivers can provide through the 'struct pci_sw_bridge_ops'
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* structure a set of operations to override or complement this
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* default behavior.
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*/
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#include <linux/pci.h>
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#include "pci-bridge-emul.h"
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#define PCI_BRIDGE_CONF_END PCI_STD_HEADER_SIZEOF
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#define PCI_CAP_SSID_SIZEOF (PCI_SSVID_DEVICE_ID + 2)
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#define PCI_CAP_SSID_START PCI_BRIDGE_CONF_END
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#define PCI_CAP_SSID_END (PCI_CAP_SSID_START + PCI_CAP_SSID_SIZEOF)
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#define PCI_CAP_PCIE_SIZEOF (PCI_EXP_SLTSTA2 + 2)
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#define PCI_CAP_PCIE_START PCI_CAP_SSID_END
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#define PCI_CAP_PCIE_END (PCI_CAP_PCIE_START + PCI_CAP_PCIE_SIZEOF)
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/**
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* struct pci_bridge_reg_behavior - register bits behaviors
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* @ro: Read-Only bits
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* @rw: Read-Write bits
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* @w1c: Write-1-to-Clear bits
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*
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* Reads and Writes will be filtered by specified behavior. All other bits not
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* declared are assumed 'Reserved' and will return 0 on reads, per PCIe 5.0:
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* "Reserved register fields must be read only and must return 0 (all 0's for
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* multi-bit fields) when read".
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*/
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struct pci_bridge_reg_behavior {
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/* Read-only bits */
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u32 ro;
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/* Read-write bits */
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u32 rw;
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/* Write-1-to-clear bits */
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u32 w1c;
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};
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static const
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struct pci_bridge_reg_behavior pci_regs_behavior[PCI_STD_HEADER_SIZEOF / 4] = {
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[PCI_VENDOR_ID / 4] = { .ro = ~0 },
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[PCI_COMMAND / 4] = {
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.rw = (PCI_COMMAND_IO | PCI_COMMAND_MEMORY |
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PCI_COMMAND_MASTER | PCI_COMMAND_PARITY |
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PCI_COMMAND_SERR),
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.ro = ((PCI_COMMAND_SPECIAL | PCI_COMMAND_INVALIDATE |
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PCI_COMMAND_VGA_PALETTE | PCI_COMMAND_WAIT |
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PCI_COMMAND_FAST_BACK) |
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(PCI_STATUS_CAP_LIST | PCI_STATUS_66MHZ |
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PCI_STATUS_FAST_BACK | PCI_STATUS_DEVSEL_MASK) << 16),
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.w1c = PCI_STATUS_ERROR_BITS << 16,
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},
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[PCI_CLASS_REVISION / 4] = { .ro = ~0 },
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/*
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* Cache Line Size register: implement as read-only, we do not
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* pretend implementing "Memory Write and Invalidate"
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* transactions"
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*
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* Latency Timer Register: implemented as read-only, as "A
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* bridge that is not capable of a burst transfer of more than
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* two data phases on its primary interface is permitted to
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* hardwire the Latency Timer to a value of 16 or less"
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*
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* Header Type: always read-only
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*
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* BIST register: implemented as read-only, as "A bridge that
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* does not support BIST must implement this register as a
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* read-only register that returns 0 when read"
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*/
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[PCI_CACHE_LINE_SIZE / 4] = { .ro = ~0 },
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/*
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* Base Address registers not used must be implemented as
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* read-only registers that return 0 when read.
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*/
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[PCI_BASE_ADDRESS_0 / 4] = { .ro = ~0 },
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[PCI_BASE_ADDRESS_1 / 4] = { .ro = ~0 },
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[PCI_PRIMARY_BUS / 4] = {
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/* Primary, secondary and subordinate bus are RW */
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.rw = GENMASK(24, 0),
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/* Secondary latency is read-only */
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.ro = GENMASK(31, 24),
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},
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[PCI_IO_BASE / 4] = {
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/* The high four bits of I/O base/limit are RW */
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.rw = (GENMASK(15, 12) | GENMASK(7, 4)),
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/* The low four bits of I/O base/limit are RO */
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.ro = (((PCI_STATUS_66MHZ | PCI_STATUS_FAST_BACK |
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PCI_STATUS_DEVSEL_MASK) << 16) |
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GENMASK(11, 8) | GENMASK(3, 0)),
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.w1c = PCI_STATUS_ERROR_BITS << 16,
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},
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[PCI_MEMORY_BASE / 4] = {
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/* The high 12-bits of mem base/limit are RW */
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.rw = GENMASK(31, 20) | GENMASK(15, 4),
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/* The low four bits of mem base/limit are RO */
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.ro = GENMASK(19, 16) | GENMASK(3, 0),
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},
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[PCI_PREF_MEMORY_BASE / 4] = {
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/* The high 12-bits of pref mem base/limit are RW */
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.rw = GENMASK(31, 20) | GENMASK(15, 4),
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/* The low four bits of pref mem base/limit are RO */
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.ro = GENMASK(19, 16) | GENMASK(3, 0),
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},
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[PCI_PREF_BASE_UPPER32 / 4] = {
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.rw = ~0,
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},
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[PCI_PREF_LIMIT_UPPER32 / 4] = {
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.rw = ~0,
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},
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[PCI_IO_BASE_UPPER16 / 4] = {
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.rw = ~0,
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},
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[PCI_CAPABILITY_LIST / 4] = {
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.ro = GENMASK(7, 0),
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},
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/*
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* If expansion ROM is unsupported then ROM Base Address register must
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* be implemented as read-only register that return 0 when read, same
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* as for unused Base Address registers.
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*/
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[PCI_ROM_ADDRESS1 / 4] = {
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.ro = ~0,
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},
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/*
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* Interrupt line (bits 7:0) are RW, interrupt pin (bits 15:8)
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* are RO, and bridge control (31:16) are a mix of RW, RO,
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* reserved and W1C bits
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*/
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[PCI_INTERRUPT_LINE / 4] = {
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/* Interrupt line is RW */
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.rw = (GENMASK(7, 0) |
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((PCI_BRIDGE_CTL_PARITY |
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PCI_BRIDGE_CTL_SERR |
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PCI_BRIDGE_CTL_ISA |
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PCI_BRIDGE_CTL_VGA |
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PCI_BRIDGE_CTL_MASTER_ABORT |
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PCI_BRIDGE_CTL_BUS_RESET |
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BIT(8) | BIT(9) | BIT(11)) << 16)),
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/* Interrupt pin is RO */
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.ro = (GENMASK(15, 8) | ((PCI_BRIDGE_CTL_FAST_BACK) << 16)),
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.w1c = BIT(10) << 16,
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},
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};
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static const
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struct pci_bridge_reg_behavior pcie_cap_regs_behavior[PCI_CAP_PCIE_SIZEOF / 4] = {
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[PCI_CAP_LIST_ID / 4] = {
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/*
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* Capability ID, Next Capability Pointer and
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* bits [14:0] of Capabilities register are all read-only.
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* Bit 15 of Capabilities register is reserved.
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*/
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.ro = GENMASK(30, 0),
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},
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[PCI_EXP_DEVCAP / 4] = {
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/*
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* Bits [31:29] and [17:16] are reserved.
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* Bits [27:18] are reserved for non-upstream ports.
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* Bits 28 and [14:6] are reserved for non-endpoint devices.
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* Other bits are read-only.
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*/
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.ro = BIT(15) | GENMASK(5, 0),
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},
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[PCI_EXP_DEVCTL / 4] = {
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/*
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* Device control register is RW, except bit 15 which is
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* reserved for non-endpoints or non-PCIe-to-PCI/X bridges.
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*/
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.rw = GENMASK(14, 0),
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/*
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* Device status register has bits 6 and [3:0] W1C, [5:4] RO,
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* the rest is reserved. Also bit 6 is reserved for non-upstream
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* ports.
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*/
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.w1c = GENMASK(3, 0) << 16,
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.ro = GENMASK(5, 4) << 16,
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},
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[PCI_EXP_LNKCAP / 4] = {
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/*
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* All bits are RO, except bit 23 which is reserved and
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* bit 18 which is reserved for non-upstream ports.
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*/
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.ro = lower_32_bits(~(BIT(23) | PCI_EXP_LNKCAP_CLKPM)),
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},
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[PCI_EXP_LNKCTL / 4] = {
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/*
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* Link control has bits [15:14], [11:3] and [1:0] RW, the
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* rest is reserved. Bit 8 is reserved for non-upstream ports.
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*
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* Link status has bits [13:0] RO, and bits [15:14]
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* W1C.
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*/
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.rw = GENMASK(15, 14) | GENMASK(11, 9) | GENMASK(7, 3) | GENMASK(1, 0),
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.ro = GENMASK(13, 0) << 16,
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.w1c = GENMASK(15, 14) << 16,
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},
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[PCI_EXP_SLTCAP / 4] = {
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.ro = ~0,
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},
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[PCI_EXP_SLTCTL / 4] = {
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/*
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* Slot control has bits [14:0] RW, the rest is
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* reserved.
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*
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* Slot status has bits 8 and [4:0] W1C, bits [7:5] RO, the
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* rest is reserved.
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*/
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.rw = GENMASK(14, 0),
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.w1c = (PCI_EXP_SLTSTA_ABP | PCI_EXP_SLTSTA_PFD |
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PCI_EXP_SLTSTA_MRLSC | PCI_EXP_SLTSTA_PDC |
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PCI_EXP_SLTSTA_CC | PCI_EXP_SLTSTA_DLLSC) << 16,
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.ro = (PCI_EXP_SLTSTA_MRLSS | PCI_EXP_SLTSTA_PDS |
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PCI_EXP_SLTSTA_EIS) << 16,
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},
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[PCI_EXP_RTCTL / 4] = {
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/*
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* Root control has bits [4:0] RW, the rest is
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* reserved.
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*
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* Root capabilities has bit 0 RO, the rest is reserved.
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*/
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.rw = (PCI_EXP_RTCTL_SECEE | PCI_EXP_RTCTL_SENFEE |
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PCI_EXP_RTCTL_SEFEE | PCI_EXP_RTCTL_PMEIE |
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PCI_EXP_RTCTL_CRSSVE),
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.ro = PCI_EXP_RTCAP_CRSVIS << 16,
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},
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[PCI_EXP_RTSTA / 4] = {
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/*
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* Root status has bits 17 and [15:0] RO, bit 16 W1C, the rest
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* is reserved.
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*/
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.ro = GENMASK(15, 0) | PCI_EXP_RTSTA_PENDING,
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.w1c = PCI_EXP_RTSTA_PME,
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},
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[PCI_EXP_DEVCAP2 / 4] = {
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/*
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* Device capabilities 2 register has reserved bits [30:27].
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* Also bits [26:24] are reserved for non-upstream ports.
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*/
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.ro = BIT(31) | GENMASK(23, 0),
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},
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[PCI_EXP_DEVCTL2 / 4] = {
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/*
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* Device control 2 register is RW. Bit 11 is reserved for
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* non-upstream ports.
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*
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* Device status 2 register is reserved.
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*/
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.rw = GENMASK(15, 12) | GENMASK(10, 0),
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},
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[PCI_EXP_LNKCAP2 / 4] = {
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/* Link capabilities 2 register has reserved bits [30:25] and 0. */
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.ro = BIT(31) | GENMASK(24, 1),
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},
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[PCI_EXP_LNKCTL2 / 4] = {
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/*
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* Link control 2 register is RW.
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*
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* Link status 2 register has bits 5, 15 W1C;
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* bits 10, 11 reserved and others are RO.
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*/
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.rw = GENMASK(15, 0),
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.w1c = (BIT(15) | BIT(5)) << 16,
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.ro = (GENMASK(14, 12) | GENMASK(9, 6) | GENMASK(4, 0)) << 16,
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},
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[PCI_EXP_SLTCAP2 / 4] = {
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/* Slot capabilities 2 register is reserved. */
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},
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[PCI_EXP_SLTCTL2 / 4] = {
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/* Both Slot control 2 and Slot status 2 registers are reserved. */
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},
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};
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static pci_bridge_emul_read_status_t
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pci_bridge_emul_read_ssid(struct pci_bridge_emul *bridge, int reg, u32 *value)
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{
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switch (reg) {
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case PCI_CAP_LIST_ID:
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*value = PCI_CAP_ID_SSVID |
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(bridge->has_pcie ? (PCI_CAP_PCIE_START << 8) : 0);
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return PCI_BRIDGE_EMUL_HANDLED;
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case PCI_SSVID_VENDOR_ID:
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*value = bridge->subsystem_vendor_id |
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(bridge->subsystem_id << 16);
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return PCI_BRIDGE_EMUL_HANDLED;
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default:
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return PCI_BRIDGE_EMUL_NOT_HANDLED;
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}
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}
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/*
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* Initialize a pci_bridge_emul structure to represent a fake PCI
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* bridge configuration space. The caller needs to have initialized
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* the PCI configuration space with whatever values make sense
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* (typically at least vendor, device, revision), the ->ops pointer,
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* and optionally ->data and ->has_pcie.
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*/
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int pci_bridge_emul_init(struct pci_bridge_emul *bridge,
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unsigned int flags)
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{
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BUILD_BUG_ON(sizeof(bridge->conf) != PCI_BRIDGE_CONF_END);
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/*
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* class_revision: Class is high 24 bits and revision is low 8 bit
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* of this member, while class for PCI Bridge Normal Decode has the
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* 24-bit value: PCI_CLASS_BRIDGE_PCI_NORMAL
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*/
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bridge->conf.class_revision |=
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cpu_to_le32(PCI_CLASS_BRIDGE_PCI_NORMAL << 8);
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bridge->conf.header_type = PCI_HEADER_TYPE_BRIDGE;
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bridge->conf.cache_line_size = 0x10;
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bridge->conf.status = cpu_to_le16(PCI_STATUS_CAP_LIST);
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bridge->pci_regs_behavior = kmemdup(pci_regs_behavior,
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sizeof(pci_regs_behavior),
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GFP_KERNEL);
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if (!bridge->pci_regs_behavior)
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return -ENOMEM;
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if (bridge->subsystem_vendor_id)
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bridge->conf.capabilities_pointer = PCI_CAP_SSID_START;
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else if (bridge->has_pcie)
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bridge->conf.capabilities_pointer = PCI_CAP_PCIE_START;
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else
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bridge->conf.capabilities_pointer = 0;
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if (bridge->conf.capabilities_pointer)
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bridge->conf.status |= cpu_to_le16(PCI_STATUS_CAP_LIST);
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if (bridge->has_pcie) {
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bridge->pcie_conf.cap_id = PCI_CAP_ID_EXP;
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bridge->pcie_conf.cap |= cpu_to_le16(PCI_EXP_TYPE_ROOT_PORT << 4);
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bridge->pcie_cap_regs_behavior =
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kmemdup(pcie_cap_regs_behavior,
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sizeof(pcie_cap_regs_behavior),
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GFP_KERNEL);
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if (!bridge->pcie_cap_regs_behavior) {
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kfree(bridge->pci_regs_behavior);
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return -ENOMEM;
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}
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/* These bits are applicable only for PCI and reserved on PCIe */
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bridge->pci_regs_behavior[PCI_CACHE_LINE_SIZE / 4].ro &=
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~GENMASK(15, 8);
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bridge->pci_regs_behavior[PCI_COMMAND / 4].ro &=
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~((PCI_COMMAND_SPECIAL | PCI_COMMAND_INVALIDATE |
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PCI_COMMAND_VGA_PALETTE | PCI_COMMAND_WAIT |
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PCI_COMMAND_FAST_BACK) |
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(PCI_STATUS_66MHZ | PCI_STATUS_FAST_BACK |
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PCI_STATUS_DEVSEL_MASK) << 16);
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bridge->pci_regs_behavior[PCI_PRIMARY_BUS / 4].ro &=
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~GENMASK(31, 24);
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bridge->pci_regs_behavior[PCI_IO_BASE / 4].ro &=
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~((PCI_STATUS_66MHZ | PCI_STATUS_FAST_BACK |
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PCI_STATUS_DEVSEL_MASK) << 16);
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bridge->pci_regs_behavior[PCI_INTERRUPT_LINE / 4].rw &=
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~((PCI_BRIDGE_CTL_MASTER_ABORT |
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BIT(8) | BIT(9) | BIT(11)) << 16);
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bridge->pci_regs_behavior[PCI_INTERRUPT_LINE / 4].ro &=
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~((PCI_BRIDGE_CTL_FAST_BACK) << 16);
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bridge->pci_regs_behavior[PCI_INTERRUPT_LINE / 4].w1c &=
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~(BIT(10) << 16);
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}
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if (flags & PCI_BRIDGE_EMUL_NO_PREFMEM_FORWARD) {
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bridge->pci_regs_behavior[PCI_PREF_MEMORY_BASE / 4].ro = ~0;
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bridge->pci_regs_behavior[PCI_PREF_MEMORY_BASE / 4].rw = 0;
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}
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if (flags & PCI_BRIDGE_EMUL_NO_IO_FORWARD) {
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bridge->pci_regs_behavior[PCI_COMMAND / 4].ro |= PCI_COMMAND_IO;
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bridge->pci_regs_behavior[PCI_COMMAND / 4].rw &= ~PCI_COMMAND_IO;
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bridge->pci_regs_behavior[PCI_IO_BASE / 4].ro |= GENMASK(15, 0);
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bridge->pci_regs_behavior[PCI_IO_BASE / 4].rw &= ~GENMASK(15, 0);
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bridge->pci_regs_behavior[PCI_IO_BASE_UPPER16 / 4].ro = ~0;
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bridge->pci_regs_behavior[PCI_IO_BASE_UPPER16 / 4].rw = 0;
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}
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return 0;
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}
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EXPORT_SYMBOL_GPL(pci_bridge_emul_init);
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/*
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* Cleanup a pci_bridge_emul structure that was previously initialized
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* using pci_bridge_emul_init().
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*/
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void pci_bridge_emul_cleanup(struct pci_bridge_emul *bridge)
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{
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if (bridge->has_pcie)
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kfree(bridge->pcie_cap_regs_behavior);
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kfree(bridge->pci_regs_behavior);
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}
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EXPORT_SYMBOL_GPL(pci_bridge_emul_cleanup);
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/*
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* Should be called by the PCI controller driver when reading the PCI
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* configuration space of the fake bridge. It will call back the
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* ->ops->read_base or ->ops->read_pcie operations.
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*/
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int pci_bridge_emul_conf_read(struct pci_bridge_emul *bridge, int where,
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int size, u32 *value)
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{
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int ret;
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int reg = where & ~3;
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pci_bridge_emul_read_status_t (*read_op)(struct pci_bridge_emul *bridge,
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int reg, u32 *value);
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__le32 *cfgspace;
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const struct pci_bridge_reg_behavior *behavior;
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if (reg < PCI_BRIDGE_CONF_END) {
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/* Emulated PCI space */
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read_op = bridge->ops->read_base;
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cfgspace = (__le32 *) &bridge->conf;
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behavior = bridge->pci_regs_behavior;
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} else if (reg >= PCI_CAP_SSID_START && reg < PCI_CAP_SSID_END && bridge->subsystem_vendor_id) {
|
|
/* Emulated PCI Bridge Subsystem Vendor ID capability */
|
|
reg -= PCI_CAP_SSID_START;
|
|
read_op = pci_bridge_emul_read_ssid;
|
|
cfgspace = NULL;
|
|
behavior = NULL;
|
|
} else if (reg >= PCI_CAP_PCIE_START && reg < PCI_CAP_PCIE_END && bridge->has_pcie) {
|
|
/* Our emulated PCIe capability */
|
|
reg -= PCI_CAP_PCIE_START;
|
|
read_op = bridge->ops->read_pcie;
|
|
cfgspace = (__le32 *) &bridge->pcie_conf;
|
|
behavior = bridge->pcie_cap_regs_behavior;
|
|
} else if (reg >= PCI_CFG_SPACE_SIZE && bridge->has_pcie) {
|
|
/* PCIe extended capability space */
|
|
reg -= PCI_CFG_SPACE_SIZE;
|
|
read_op = bridge->ops->read_ext;
|
|
cfgspace = NULL;
|
|
behavior = NULL;
|
|
} else {
|
|
/* Not implemented */
|
|
*value = 0;
|
|
return PCIBIOS_SUCCESSFUL;
|
|
}
|
|
|
|
if (read_op)
|
|
ret = read_op(bridge, reg, value);
|
|
else
|
|
ret = PCI_BRIDGE_EMUL_NOT_HANDLED;
|
|
|
|
if (ret == PCI_BRIDGE_EMUL_NOT_HANDLED) {
|
|
if (cfgspace)
|
|
*value = le32_to_cpu(cfgspace[reg / 4]);
|
|
else
|
|
*value = 0;
|
|
}
|
|
|
|
/*
|
|
* Make sure we never return any reserved bit with a value
|
|
* different from 0.
|
|
*/
|
|
if (behavior)
|
|
*value &= behavior[reg / 4].ro | behavior[reg / 4].rw |
|
|
behavior[reg / 4].w1c;
|
|
|
|
if (size == 1)
|
|
*value = (*value >> (8 * (where & 3))) & 0xff;
|
|
else if (size == 2)
|
|
*value = (*value >> (8 * (where & 3))) & 0xffff;
|
|
else if (size != 4)
|
|
return PCIBIOS_BAD_REGISTER_NUMBER;
|
|
|
|
return PCIBIOS_SUCCESSFUL;
|
|
}
|
|
EXPORT_SYMBOL_GPL(pci_bridge_emul_conf_read);
|
|
|
|
/*
|
|
* Should be called by the PCI controller driver when writing the PCI
|
|
* configuration space of the fake bridge. It will call back the
|
|
* ->ops->write_base or ->ops->write_pcie operations.
|
|
*/
|
|
int pci_bridge_emul_conf_write(struct pci_bridge_emul *bridge, int where,
|
|
int size, u32 value)
|
|
{
|
|
int reg = where & ~3;
|
|
int mask, ret, old, new, shift;
|
|
void (*write_op)(struct pci_bridge_emul *bridge, int reg,
|
|
u32 old, u32 new, u32 mask);
|
|
__le32 *cfgspace;
|
|
const struct pci_bridge_reg_behavior *behavior;
|
|
|
|
ret = pci_bridge_emul_conf_read(bridge, reg, 4, &old);
|
|
if (ret != PCIBIOS_SUCCESSFUL)
|
|
return ret;
|
|
|
|
if (reg < PCI_BRIDGE_CONF_END) {
|
|
/* Emulated PCI space */
|
|
write_op = bridge->ops->write_base;
|
|
cfgspace = (__le32 *) &bridge->conf;
|
|
behavior = bridge->pci_regs_behavior;
|
|
} else if (reg >= PCI_CAP_PCIE_START && reg < PCI_CAP_PCIE_END && bridge->has_pcie) {
|
|
/* Our emulated PCIe capability */
|
|
reg -= PCI_CAP_PCIE_START;
|
|
write_op = bridge->ops->write_pcie;
|
|
cfgspace = (__le32 *) &bridge->pcie_conf;
|
|
behavior = bridge->pcie_cap_regs_behavior;
|
|
} else if (reg >= PCI_CFG_SPACE_SIZE && bridge->has_pcie) {
|
|
/* PCIe extended capability space */
|
|
reg -= PCI_CFG_SPACE_SIZE;
|
|
write_op = bridge->ops->write_ext;
|
|
cfgspace = NULL;
|
|
behavior = NULL;
|
|
} else {
|
|
/* Not implemented */
|
|
return PCIBIOS_SUCCESSFUL;
|
|
}
|
|
|
|
shift = (where & 0x3) * 8;
|
|
|
|
if (size == 4)
|
|
mask = 0xffffffff;
|
|
else if (size == 2)
|
|
mask = 0xffff << shift;
|
|
else if (size == 1)
|
|
mask = 0xff << shift;
|
|
else
|
|
return PCIBIOS_BAD_REGISTER_NUMBER;
|
|
|
|
if (behavior) {
|
|
/* Keep all bits, except the RW bits */
|
|
new = old & (~mask | ~behavior[reg / 4].rw);
|
|
|
|
/* Update the value of the RW bits */
|
|
new |= (value << shift) & (behavior[reg / 4].rw & mask);
|
|
|
|
/* Clear the W1C bits */
|
|
new &= ~((value << shift) & (behavior[reg / 4].w1c & mask));
|
|
} else {
|
|
new = old & ~mask;
|
|
new |= (value << shift) & mask;
|
|
}
|
|
|
|
if (cfgspace) {
|
|
/* Save the new value with the cleared W1C bits into the cfgspace */
|
|
cfgspace[reg / 4] = cpu_to_le32(new);
|
|
}
|
|
|
|
if (behavior) {
|
|
/*
|
|
* Clear the W1C bits not specified by the write mask, so that the
|
|
* write_op() does not clear them.
|
|
*/
|
|
new &= ~(behavior[reg / 4].w1c & ~mask);
|
|
|
|
/*
|
|
* Set the W1C bits specified by the write mask, so that write_op()
|
|
* knows about that they are to be cleared.
|
|
*/
|
|
new |= (value << shift) & (behavior[reg / 4].w1c & mask);
|
|
}
|
|
|
|
if (write_op)
|
|
write_op(bridge, reg, old, new, mask);
|
|
|
|
return PCIBIOS_SUCCESSFUL;
|
|
}
|
|
EXPORT_SYMBOL_GPL(pci_bridge_emul_conf_write);
|