167 строки
7.3 KiB
ReStructuredText
167 строки
7.3 KiB
ReStructuredText
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Generic bitfield packing and unpacking functions
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================================================
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Problem statement
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-----------------
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When working with hardware, one has to choose between several approaches of
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interfacing with it.
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One can memory-map a pointer to a carefully crafted struct over the hardware
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device's memory region, and access its fields as struct members (potentially
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declared as bitfields). But writing code this way would make it less portable,
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due to potential endianness mismatches between the CPU and the hardware device.
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Additionally, one has to pay close attention when translating register
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definitions from the hardware documentation into bit field indices for the
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structs. Also, some hardware (typically networking equipment) tends to group
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its register fields in ways that violate any reasonable word boundaries
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(sometimes even 64 bit ones). This creates the inconvenience of having to
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define "high" and "low" portions of register fields within the struct.
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A more robust alternative to struct field definitions would be to extract the
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required fields by shifting the appropriate number of bits. But this would
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still not protect from endianness mismatches, except if all memory accesses
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were performed byte-by-byte. Also the code can easily get cluttered, and the
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high-level idea might get lost among the many bit shifts required.
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Many drivers take the bit-shifting approach and then attempt to reduce the
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clutter with tailored macros, but more often than not these macros take
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shortcuts that still prevent the code from being truly portable.
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The solution
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------------
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This API deals with 2 basic operations:
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- Packing a CPU-usable number into a memory buffer (with hardware
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constraints/quirks)
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- Unpacking a memory buffer (which has hardware constraints/quirks)
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into a CPU-usable number.
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The API offers an abstraction over said hardware constraints and quirks,
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over CPU endianness and therefore between possible mismatches between
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the two.
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The basic unit of these API functions is the u64. From the CPU's
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perspective, bit 63 always means bit offset 7 of byte 7, albeit only
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logically. The question is: where do we lay this bit out in memory?
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The following examples cover the memory layout of a packed u64 field.
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The byte offsets in the packed buffer are always implicitly 0, 1, ... 7.
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What the examples show is where the logical bytes and bits sit.
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1. Normally (no quirks), we would do it like this:
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::
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63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
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7 6 5 4
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31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
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3 2 1 0
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That is, the MSByte (7) of the CPU-usable u64 sits at memory offset 0, and the
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LSByte (0) of the u64 sits at memory offset 7.
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This corresponds to what most folks would regard to as "big endian", where
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bit i corresponds to the number 2^i. This is also referred to in the code
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comments as "logical" notation.
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2. If QUIRK_MSB_ON_THE_RIGHT is set, we do it like this:
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56 57 58 59 60 61 62 63 48 49 50 51 52 53 54 55 40 41 42 43 44 45 46 47 32 33 34 35 36 37 38 39
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7 6 5 4
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24 25 26 27 28 29 30 31 16 17 18 19 20 21 22 23 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7
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3 2 1 0
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That is, QUIRK_MSB_ON_THE_RIGHT does not affect byte positioning, but
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inverts bit offsets inside a byte.
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3. If QUIRK_LITTLE_ENDIAN is set, we do it like this:
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::
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39 38 37 36 35 34 33 32 47 46 45 44 43 42 41 40 55 54 53 52 51 50 49 48 63 62 61 60 59 58 57 56
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4 5 6 7
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7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 23 22 21 20 19 18 17 16 31 30 29 28 27 26 25 24
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0 1 2 3
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Therefore, QUIRK_LITTLE_ENDIAN means that inside the memory region, every
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byte from each 4-byte word is placed at its mirrored position compared to
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the boundary of that word.
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4. If QUIRK_MSB_ON_THE_RIGHT and QUIRK_LITTLE_ENDIAN are both set, we do it
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like this:
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::
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32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63
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4 5 6 7
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0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
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0 1 2 3
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5. If just QUIRK_LSW32_IS_FIRST is set, we do it like this:
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31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
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3 2 1 0
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63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
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7 6 5 4
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In this case the 8 byte memory region is interpreted as follows: first
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4 bytes correspond to the least significant 4-byte word, next 4 bytes to
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the more significant 4-byte word.
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6. If QUIRK_LSW32_IS_FIRST and QUIRK_MSB_ON_THE_RIGHT are set, we do it like
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this:
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24 25 26 27 28 29 30 31 16 17 18 19 20 21 22 23 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7
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3 2 1 0
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56 57 58 59 60 61 62 63 48 49 50 51 52 53 54 55 40 41 42 43 44 45 46 47 32 33 34 35 36 37 38 39
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7 6 5 4
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7. If QUIRK_LSW32_IS_FIRST and QUIRK_LITTLE_ENDIAN are set, it looks like
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this:
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::
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7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 23 22 21 20 19 18 17 16 31 30 29 28 27 26 25 24
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0 1 2 3
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39 38 37 36 35 34 33 32 47 46 45 44 43 42 41 40 55 54 53 52 51 50 49 48 63 62 61 60 59 58 57 56
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4 5 6 7
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8. If QUIRK_LSW32_IS_FIRST, QUIRK_LITTLE_ENDIAN and QUIRK_MSB_ON_THE_RIGHT
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are set, it looks like this:
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::
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0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
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0 1 2 3
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32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63
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4 5 6 7
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We always think of our offsets as if there were no quirk, and we translate
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them afterwards, before accessing the memory region.
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Intended use
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------------
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Drivers that opt to use this API first need to identify which of the above 3
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quirk combinations (for a total of 8) match what the hardware documentation
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describes. Then they should wrap the packing() function, creating a new
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xxx_packing() that calls it using the proper QUIRK_* one-hot bits set.
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The packing() function returns an int-encoded error code, which protects the
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programmer against incorrect API use. The errors are not expected to occur
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durring runtime, therefore it is reasonable for xxx_packing() to return void
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and simply swallow those errors. Optionally it can dump stack or print the
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error description.
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