108 строки
2.8 KiB
C
108 строки
2.8 KiB
C
/*
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* arch/sh/mm/tlb-pteaex.c
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*
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* TLB operations for SH-X3 CPUs featuring PTE ASID Extensions.
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*
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* Copyright (C) 2009 Paul Mundt
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*/
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#include <linux/kernel.h>
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#include <linux/mm.h>
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#include <linux/io.h>
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#include <asm/system.h>
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#include <asm/mmu_context.h>
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#include <asm/cacheflush.h>
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void __update_tlb(struct vm_area_struct *vma, unsigned long address, pte_t pte)
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{
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unsigned long flags, pteval, vpn;
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/*
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* Handle debugger faulting in for debugee.
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*/
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if (vma && current->active_mm != vma->vm_mm)
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return;
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local_irq_save(flags);
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/* Set PTEH register */
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vpn = address & MMU_VPN_MASK;
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__raw_writel(vpn, MMU_PTEH);
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/* Set PTEAEX */
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__raw_writel(get_asid(), MMU_PTEAEX);
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pteval = pte.pte_low;
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/* Set PTEA register */
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#ifdef CONFIG_X2TLB
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/*
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* For the extended mode TLB this is trivial, only the ESZ and
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* EPR bits need to be written out to PTEA, with the remainder of
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* the protection bits (with the exception of the compat-mode SZ
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* and PR bits, which are cleared) being written out in PTEL.
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*/
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__raw_writel(pte.pte_high, MMU_PTEA);
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#endif
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/* Set PTEL register */
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pteval &= _PAGE_FLAGS_HARDWARE_MASK; /* drop software flags */
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#ifdef CONFIG_CACHE_WRITETHROUGH
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pteval |= _PAGE_WT;
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#endif
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/* conveniently, we want all the software flags to be 0 anyway */
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__raw_writel(pteval, MMU_PTEL);
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/* Load the TLB */
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asm volatile("ldtlb": /* no output */ : /* no input */ : "memory");
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local_irq_restore(flags);
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}
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/*
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* While SH-X2 extended TLB mode splits out the memory-mapped I/UTLB
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* data arrays, SH-X3 cores with PTEAEX split out the memory-mapped
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* address arrays. In compat mode the second array is inaccessible, while
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* in extended mode, the legacy 8-bit ASID field in address array 1 has
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* undefined behaviour.
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*/
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void local_flush_tlb_one(unsigned long asid, unsigned long page)
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{
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jump_to_uncached();
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__raw_writel(page, MMU_UTLB_ADDRESS_ARRAY | MMU_PAGE_ASSOC_BIT);
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__raw_writel(asid, MMU_UTLB_ADDRESS_ARRAY2 | MMU_PAGE_ASSOC_BIT);
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__raw_writel(page, MMU_ITLB_ADDRESS_ARRAY | MMU_PAGE_ASSOC_BIT);
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__raw_writel(asid, MMU_ITLB_ADDRESS_ARRAY2 | MMU_PAGE_ASSOC_BIT);
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back_to_cached();
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}
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void local_flush_tlb_all(void)
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{
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unsigned long flags, status;
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int i;
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/*
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* Flush all the TLB.
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*/
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local_irq_save(flags);
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jump_to_uncached();
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status = __raw_readl(MMUCR);
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status = ((status & MMUCR_URB) >> MMUCR_URB_SHIFT);
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if (status == 0)
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status = MMUCR_URB_NENTRIES;
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for (i = 0; i < status; i++)
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__raw_writel(0x0, MMU_UTLB_ADDRESS_ARRAY | (i << 8));
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for (i = 0; i < 4; i++)
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__raw_writel(0x0, MMU_ITLB_ADDRESS_ARRAY | (i << 8));
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back_to_cached();
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ctrl_barrier();
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local_irq_restore(flags);
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}
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