100 строки
3.6 KiB
Plaintext
100 строки
3.6 KiB
Plaintext
Intel(R) Trace Hub (TH)
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=======================
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Overview
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--------
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Intel(R) Trace Hub (TH) is a set of hardware blocks that produce,
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switch and output trace data from multiple hardware and software
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sources over several types of trace output ports encoded in System
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Trace Protocol (MIPI STPv2) and is intended to perform full system
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debugging. For more information on the hardware, see Intel(R) Trace
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Hub developer's manual [1].
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It consists of trace sources, trace destinations (outputs) and a
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switch (Global Trace Hub, GTH). These devices are placed on a bus of
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their own ("intel_th"), where they can be discovered and configured
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via sysfs attributes.
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Currently, the following Intel TH subdevices (blocks) are supported:
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- Software Trace Hub (STH), trace source, which is a System Trace
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Module (STM) device,
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- Memory Storage Unit (MSU), trace output, which allows storing
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trace hub output in system memory,
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- Parallel Trace Interface output (PTI), trace output to an external
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debug host via a PTI port,
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- Global Trace Hub (GTH), which is a switch and a central component
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of Intel(R) Trace Hub architecture.
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Common attributes for output devices are described in
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Documentation/ABI/testing/sysfs-bus-intel_th-output-devices, the most
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notable of them is "active", which enables or disables trace output
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into that particular output device.
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GTH allows directing different STP masters into different output ports
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via its "masters" attribute group. More detailed GTH interface
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description is at Documentation/ABI/testing/sysfs-bus-intel_th-devices-gth.
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STH registers an stm class device, through which it provides interface
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to userspace and kernelspace software trace sources. See
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Documentation/tracing/stm.txt for more information on that.
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MSU can be configured to collect trace data into a system memory
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buffer, which can later on be read from its device nodes via read() or
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mmap() interface.
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On the whole, Intel(R) Trace Hub does not require any special
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userspace software to function; everything can be configured, started
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and collected via sysfs attributes, and device nodes.
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[1] https://software.intel.com/sites/default/files/managed/d3/3c/intel-th-developer-manual.pdf
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Bus and Subdevices
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------------------
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For each Intel TH device in the system a bus of its own is
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created and assigned an id number that reflects the order in which TH
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devices were emumerated. All TH subdevices (devices on intel_th bus)
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begin with this id: 0-gth, 0-msc0, 0-msc1, 0-pti, 0-sth, which is
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followed by device's name and an optional index.
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Output devices also get a device node in /dev/intel_thN, where N is
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the Intel TH device id. For example, MSU's memory buffers, when
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allocated, are accessible via /dev/intel_th0/msc{0,1}.
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Quick example
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-------------
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# figure out which GTH port is the first memory controller:
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$ cat /sys/bus/intel_th/devices/0-msc0/port
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0
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# looks like it's port 0, configure master 33 to send data to port 0:
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$ echo 0 > /sys/bus/intel_th/devices/0-gth/masters/33
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# allocate a 2-windowed multiblock buffer on the first memory
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# controller, each with 64 pages:
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$ echo multi > /sys/bus/intel_th/devices/0-msc0/mode
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$ echo 64,64 > /sys/bus/intel_th/devices/0-msc0/nr_pages
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# enable wrapping for this controller, too:
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$ echo 1 > /sys/bus/intel_th/devices/0-msc0/wrap
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# and enable tracing into this port:
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$ echo 1 > /sys/bus/intel_th/devices/0-msc0/active
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# .. send data to master 33, see stm.txt for more details ..
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# .. wait for traces to pile up ..
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# .. and stop the trace:
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$ echo 0 > /sys/bus/intel_th/devices/0-msc0/active
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# and now you can collect the trace from the device node:
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$ cat /dev/intel_th0/msc0 > my_stp_trace
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